Pub Date : 2024-11-25DOI: 10.1109/TED.2024.3487814
Zewei Dong;Yun Bai;Chengyue Yang;Yidan Tang;Jilong Hao;Xuan Li;Xiaoli Tian;Xinyu Liu
This article reports the influence of temperature on digital ICs fabricated in 4H-SiC CMOS process technology. The performances of CMOS devices were compared and analyzed at different drain voltages from 25 °C to 500 °C. The current-output capability of n-channel MOSFET improves with increasing temperature up to 500 °C, while that of p-channel MOSFET reaches an optimum at nearly 350 °C. The current-output capability of n-channel MOSFET is limited to lower than that of p-channel MOSFET below a temperature point when the drain voltage rises, due to the velocity saturation of electrons. Furthermore, the value of temperature point increases with higher drain voltage. A typical inverter was characterized and analyzed in detail based on the characteristics of CMOS devices. The fall/rise time and high-to-low/low-to-high propagation delay time show a similar temperature characteristic of the drain current of n- and p-channel MOSFETs, respectively. Compared to fall and rise times, the high-to-low and low-to-high propagation delay times intersect at a higher temperature because of the different drain voltages when extracting parameters. The temperature characteristics, including the oscillation frequency of ring oscillators and the output current of gate driver, were also analyzed through the performances of CMOS devices.
{"title":"Impact of Temperature on Digital Integrated Circuits in a 4H-SiC CMOS Technology","authors":"Zewei Dong;Yun Bai;Chengyue Yang;Yidan Tang;Jilong Hao;Xuan Li;Xiaoli Tian;Xinyu Liu","doi":"10.1109/TED.2024.3487814","DOIUrl":"https://doi.org/10.1109/TED.2024.3487814","url":null,"abstract":"This article reports the influence of temperature on digital ICs fabricated in 4H-SiC CMOS process technology. The performances of CMOS devices were compared and analyzed at different drain voltages from 25 °C to 500 °C. The current-output capability of n-channel MOSFET improves with increasing temperature up to 500 °C, while that of p-channel MOSFET reaches an optimum at nearly 350 °C. The current-output capability of n-channel MOSFET is limited to lower than that of p-channel MOSFET below a temperature point when the drain voltage rises, due to the velocity saturation of electrons. Furthermore, the value of temperature point increases with higher drain voltage. A typical inverter was characterized and analyzed in detail based on the characteristics of CMOS devices. The fall/rise time and high-to-low/low-to-high propagation delay time show a similar temperature characteristic of the drain current of n- and p-channel MOSFETs, respectively. Compared to fall and rise times, the high-to-low and low-to-high propagation delay times intersect at a higher temperature because of the different drain voltages when extracting parameters. The temperature characteristics, including the oscillation frequency of ring oscillators and the output current of gate driver, were also analyzed through the performances of CMOS devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"97-103"},"PeriodicalIF":2.9,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TED.2024.3499936
Ting He;Muyu Yi;Xinyue Niu;Jinmei Yao;Tao Xun;Langning Wang;Ting Shu
The trade-off between microwave frequency and output power in VCSI 4H-silicon carbide (SiC) photoconductive semiconductor switch (PCSSs), based on carrier lifetime is investigated. PCSSs with two different vanadium doping concentrations are fabricated and tested across a frequency range of 0.5–2 GHz. The output power and modulation depth ratio trends with microwave frequency indicate a trade-off between microwave frequency and output power. The two devices exhibit output powers of approximately 40 W (@0.5 GHz) and 160 W (@0.5 GHz), respectively. Employing transient absorption (TA) techniques, the carrier lifetime of the two devices is determined to be 30 and 460 ps, revealing a relationship between longer carrier lifetime and increased output power. Nevertheless, the longer carrier lifetime also leads to a lower modulation depth ratio. Furthermore, when carrier lifetime ceases to be the primary constraining factor for the device’s frequency response, the upper cut-off frequency is constrained by the interstage capacitance.
{"title":"The Trade-Off Between Microwave Frequency and Output Power in SiC Photoconductive Switches Based on Carrier Lifetime","authors":"Ting He;Muyu Yi;Xinyue Niu;Jinmei Yao;Tao Xun;Langning Wang;Ting Shu","doi":"10.1109/TED.2024.3499936","DOIUrl":"https://doi.org/10.1109/TED.2024.3499936","url":null,"abstract":"The trade-off between microwave frequency and output power in VCSI 4H-silicon carbide (SiC) photoconductive semiconductor switch (PCSSs), based on carrier lifetime is investigated. PCSSs with two different vanadium doping concentrations are fabricated and tested across a frequency range of 0.5–2 GHz. The output power and modulation depth ratio trends with microwave frequency indicate a trade-off between microwave frequency and output power. The two devices exhibit output powers of approximately 40 W (@0.5 GHz) and 160 W (@0.5 GHz), respectively. Employing transient absorption (TA) techniques, the carrier lifetime of the two devices is determined to be 30 and 460 ps, revealing a relationship between longer carrier lifetime and increased output power. Nevertheless, the longer carrier lifetime also leads to a lower modulation depth ratio. Furthermore, when carrier lifetime ceases to be the primary constraining factor for the device’s frequency response, the upper cut-off frequency is constrained by the interstage capacitance.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"169-174"},"PeriodicalIF":2.9,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TED.2024.3496446
Yi Gu;Chengkang Tang;Xianghui Li;Qingqing Sun;David Wei Zhang;Hao Zhu
While excelling in device density and driving capability, the fin field-effect transistor (FinFET) development has highlighted the increasing impact of parasitic capacitance on high-frequency performance. Here, we report a comprehensive impact study of FinFET structures and key process on the parasitic capacitance, particularly the gate-source/drain (S/D) capacitance ( ${C} _{text {G-SD}}$ ). By TCAD simulation, the optimal structural parameters of the fin and S/D geometry have been identified with improved dc performance as well as ${C} _{text {G-SD}}$ characteristics. The parasitic ${C} _{text {G-SD}}$ is further suppressed by optimized high-k/metal gate (HKMG) critical process steps. Enhanced ac performance is experimentally achieved realizing over 20% improvement in cutoff frequency ( ${f} _{text {T}}$ ) and maximum oscillation frequency ( ${f} _{max }$ ) as compared to baseline (320.4-GHz ${f} _{text {T}}$ and 362.2-GHz ${f} _{max }$ for nMOS and 393-GHz ${f} _{text {T}}$ and 168-GHz ${f} _{max }$ for pMOS). The results demonstrate practical potential in both device-level and circuit-level engineering toward advanced FinFET-based high-frequency applications.
{"title":"A Structural Impact Study and Process Optimization of FinFET Parasitic Capacitance","authors":"Yi Gu;Chengkang Tang;Xianghui Li;Qingqing Sun;David Wei Zhang;Hao Zhu","doi":"10.1109/TED.2024.3496446","DOIUrl":"https://doi.org/10.1109/TED.2024.3496446","url":null,"abstract":"While excelling in device density and driving capability, the fin field-effect transistor (FinFET) development has highlighted the increasing impact of parasitic capacitance on high-frequency performance. Here, we report a comprehensive impact study of FinFET structures and key process on the parasitic capacitance, particularly the gate-source/drain (S/D) capacitance (\u0000<inline-formula> <tex-math>${C} _{text {G-SD}}$ </tex-math></inline-formula>\u0000). By TCAD simulation, the optimal structural parameters of the fin and S/D geometry have been identified with improved dc performance as well as \u0000<inline-formula> <tex-math>${C} _{text {G-SD}}$ </tex-math></inline-formula>\u0000 characteristics. The parasitic \u0000<inline-formula> <tex-math>${C} _{text {G-SD}}$ </tex-math></inline-formula>\u0000 is further suppressed by optimized high-k/metal gate (HKMG) critical process steps. Enhanced ac performance is experimentally achieved realizing over 20% improvement in cutoff frequency (\u0000<inline-formula> <tex-math>${f} _{text {T}}$ </tex-math></inline-formula>\u0000) and maximum oscillation frequency (\u0000<inline-formula> <tex-math>${f} _{max }$ </tex-math></inline-formula>\u0000) as compared to baseline (320.4-GHz \u0000<inline-formula> <tex-math>${f} _{text {T}}$ </tex-math></inline-formula>\u0000 and 362.2-GHz \u0000<inline-formula> <tex-math>${f} _{max }$ </tex-math></inline-formula>\u0000 for nMOS and 393-GHz \u0000<inline-formula> <tex-math>${f} _{text {T}}$ </tex-math></inline-formula>\u0000 and 168-GHz \u0000<inline-formula> <tex-math>${f} _{max }$ </tex-math></inline-formula>\u0000 for pMOS). The results demonstrate practical potential in both device-level and circuit-level engineering toward advanced FinFET-based high-frequency applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"17-23"},"PeriodicalIF":2.9,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TED.2024.3499948
Li Cheng;Gang He;Can Fu;Shanshan Jiang;Zebo Fang
A detailed investigation into the effects of atomic layer deposition (ALD)-derived AlN passivation layer on the interface chemistry, temperature stability, and leakage current conduction mechanism (LCCM) of ErxYyO/Si gate stacks has been carried out in this work. The findings have indicated that ALD-driven AlN passivation layer significantly suppresses the diffusion of substrate elements, thereby enhancing the quality of the interface. X-ray photoelectron spectroscopy (XPS) analysis revealed that the low valence oxides of silicon decrease with the increase of the passivation period, thus improving the interface state. Electrical characterizations demonstrated that the samples treated with 40 cycles of passivation exhibited the best electrical properties, including a high dielectric constant (17.69) and a low leakage current density of $7.16times 10^{-{8}}$ A/cm2. The interfacial state density, as determined by the conductivity method, indicated that the passivation treatment was effective in controlling the interfacial quality, demonstrating the lowest interfacial state density ( $3.79times 10^{{12}}$ eV $^{-{1}}cdot $ cm−2) observed for the S2 sample. Temperature stability studies have demonstrated that high temperature leads to the decrease device stability, which can be mitigated by the AlN passivation layer. LCCM analysis has revealed that Schottky emission (SE) dominates at low electric fields, while Poole-Frenkel (PF) emission dominates at medium to high electric fields, and Fowler-Nordheim (FN) tunneling is exhibited at high electric fields. These findings suggest that the ErxYyO gate dielectric treated with AlN passivation layer exhibits excellent electrical properties and improved interface quality. Consequently, ALD-processed AlN may be a promising candidate for the passivation layer of metal-oxide–semiconductor (MOS) devices in the future.
本文详细研究了原子层沉积（ALD）引发的AlN钝化层对ErxYyO/Si栅极堆界面化学、温度稳定性和漏电流传导机制（LCCM）的影响。结果表明，ald驱动的AlN钝化层显著抑制了衬底元素的扩散，从而提高了界面质量。x射线光电子能谱（XPS）分析表明，随着钝化时间的延长，硅的低价氧化物减少，从而改善了界面状态。电学表征表明，经过40次钝化循环处理的样品具有最佳的电学性能，包括高介电常数（17.69）和低漏电流密度（7.16 × 10^{-{8}}$ a /cm2）。电导率法测定的界面态密度表明，钝化处理对控制界面质量是有效的，S2样品的界面态密度最低（$3.79乘以10^{{12}}$ eV $^{-{1}}cdot $ cm−2）。温度稳定性研究表明，高温会导致器件稳定性下降，这可以通过AlN钝化层来缓解。LCCM分析表明，低电场条件下以肖特基发射（SE）为主，中、高电场条件下以普尔-弗伦克尔（PF）发射为主，高电场条件下以Fowler-Nordheim （FN）隧穿为主。这些结果表明，经过AlN钝化层处理的ErxYyO栅极电介质具有优异的电学性能和改善的界面质量。因此，ald处理的AlN可能是未来金属氧化物半导体（MOS）器件钝化层的有希望的候选者。
{"title":"Interface Optimization and Temperature Reliability Estimation of ErₓYyO/Si Gate Stacks by ALD-Derived AlN Passivation Layer","authors":"Li Cheng;Gang He;Can Fu;Shanshan Jiang;Zebo Fang","doi":"10.1109/TED.2024.3499948","DOIUrl":"https://doi.org/10.1109/TED.2024.3499948","url":null,"abstract":"A detailed investigation into the effects of atomic layer deposition (ALD)-derived AlN passivation layer on the interface chemistry, temperature stability, and leakage current conduction mechanism (LCCM) of ErxYyO/Si gate stacks has been carried out in this work. The findings have indicated that ALD-driven AlN passivation layer significantly suppresses the diffusion of substrate elements, thereby enhancing the quality of the interface. X-ray photoelectron spectroscopy (XPS) analysis revealed that the low valence oxides of silicon decrease with the increase of the passivation period, thus improving the interface state. Electrical characterizations demonstrated that the samples treated with 40 cycles of passivation exhibited the best electrical properties, including a high dielectric constant (17.69) and a low leakage current density of \u0000<inline-formula> <tex-math>$7.16times 10^{-{8}}$ </tex-math></inline-formula>\u0000 A/cm2. The interfacial state density, as determined by the conductivity method, indicated that the passivation treatment was effective in controlling the interfacial quality, demonstrating the lowest interfacial state density (\u0000<inline-formula> <tex-math>$3.79times 10^{{12}}$ </tex-math></inline-formula>\u0000 eV\u0000<inline-formula> <tex-math>$^{-{1}}cdot $ </tex-math></inline-formula>\u0000 cm−2) observed for the S2 sample. Temperature stability studies have demonstrated that high temperature leads to the decrease device stability, which can be mitigated by the AlN passivation layer. LCCM analysis has revealed that Schottky emission (SE) dominates at low electric fields, while Poole-Frenkel (PF) emission dominates at medium to high electric fields, and Fowler-Nordheim (FN) tunneling is exhibited at high electric fields. These findings suggest that the ErxYyO gate dielectric treated with AlN passivation layer exhibits excellent electrical properties and improved interface quality. Consequently, ALD-processed AlN may be a promising candidate for the passivation layer of metal-oxide–semiconductor (MOS) devices in the future.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"44-50"},"PeriodicalIF":2.9,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TED.2024.3495632
Zehao Lin;Zhuocheng Zhang;Chang Niu;Hongyi Dou;Ke Xu;Mir Md Fahimul Islam;Jian-Yu Lin;Changhyuck Sung;Minji Hong;Daewon Ha;Haiyan Wang;Muhammad Ashraful Alam;Peide. D. Ye
In this work, we report atomic-layer-deposited (ALD) based all-oxide transistors toward vertically stacked high-density logic and memory for 3-D integration. This structure utilizes thick degenerated ALD In2O3 as the conducting gate, and ALD In2O3 thin film itself serves as source/drain contacts to the ALD In2O3 channel without metal contacts and gate formation. The all-oxide field-effect transistors (AOFETs) not only survived under high-temperature annealing over $400~^{circ }$ C but also gained a boosted on-/off-ratio over $10^{{7}}$ with subthreshold swing (SS) close to 60 mV/dec at room temperature. AOFETs present high uniformity and very robust reliability with a threshold voltage instability ( $boldsymbol {Delta } {V}_{text {TH}}text {)}$ of −5 and −50 mV under positive bias stress (PBS) and negative bias stress (NBS) tests for $10^{{4}}$ s. The vertical AOFETs (V-AOFETs) demonstrate good gate modulation from sidewall In2O3 with thickness as well as gate length ( ${T}_{text {IO,{g}}}text {)}$ of 10 nm, achieving on-/off-ratio over $10^{{5}}$ and maximum current ( ${I}_{max }text {)}$ over $160~boldsymbol {mu } $ A/ $boldsymbol {mu } $ m. Vertical all-oxide ferroelectric FETs (V-AO-FeFETs) show a memory window (MW) of 1.85 V, with endurance and retention extended to $10^{{12}}$ cycles and ten years at room temperature, respectively. These findings illustrate that the vertical-channel all-oxide devices based on ALD oxide semiconductors (OS) are promising candidates for future high-density logic and memory applications in 3-D integration.
{"title":"Highly Robust All-Oxide Transistors Toward Vertical Logic and Memory","authors":"Zehao Lin;Zhuocheng Zhang;Chang Niu;Hongyi Dou;Ke Xu;Mir Md Fahimul Islam;Jian-Yu Lin;Changhyuck Sung;Minji Hong;Daewon Ha;Haiyan Wang;Muhammad Ashraful Alam;Peide. D. Ye","doi":"10.1109/TED.2024.3495632","DOIUrl":"https://doi.org/10.1109/TED.2024.3495632","url":null,"abstract":"In this work, we report atomic-layer-deposited (ALD) based all-oxide transistors toward vertically stacked high-density logic and memory for 3-D integration. This structure utilizes thick degenerated ALD In2O3 as the conducting gate, and ALD In2O3 thin film itself serves as source/drain contacts to the ALD In2O3 channel without metal contacts and gate formation. The all-oxide field-effect transistors (AOFETs) not only survived under high-temperature annealing over \u0000<inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>\u0000 C but also gained a boosted on-/off-ratio over \u0000<inline-formula> <tex-math>$10^{{7}}$ </tex-math></inline-formula>\u0000 with subthreshold swing (SS) close to 60 mV/dec at room temperature. AOFETs present high uniformity and very robust reliability with a threshold voltage instability (\u0000<inline-formula> <tex-math>$boldsymbol {Delta } {V}_{text {TH}}text {)}$ </tex-math></inline-formula>\u0000 of −5 and −50 mV under positive bias stress (PBS) and negative bias stress (NBS) tests for \u0000<inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula>\u0000 s. The vertical AOFETs (V-AOFETs) demonstrate good gate modulation from sidewall In2O3 with thickness as well as gate length (\u0000<inline-formula> <tex-math>${T}_{text {IO,{g}}}text {)}$ </tex-math></inline-formula>\u0000 of 10 nm, achieving on-/off-ratio over \u0000<inline-formula> <tex-math>$10^{{5}}$ </tex-math></inline-formula>\u0000 and maximum current (\u0000<inline-formula> <tex-math>${I}_{max }text {)}$ </tex-math></inline-formula>\u0000 over \u0000<inline-formula> <tex-math>$160~boldsymbol {mu } $ </tex-math></inline-formula>\u0000 A/\u0000<inline-formula> <tex-math>$boldsymbol {mu } $ </tex-math></inline-formula>\u0000 m. Vertical all-oxide ferroelectric FETs (V-AO-FeFETs) show a memory window (MW) of 1.85 V, with endurance and retention extended to \u0000<inline-formula> <tex-math>$10^{{12}}$ </tex-math></inline-formula>\u0000 cycles and ten years at room temperature, respectively. These findings illustrate that the vertical-channel all-oxide devices based on ALD oxide semiconductors (OS) are promising candidates for future high-density logic and memory applications in 3-D integration.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7984-7991"},"PeriodicalIF":2.9,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
By using the nonvolatile and stochastic properties of memristor, memristors crossbar arrays can efficiently accelerate Bayesian neural networks (BNNs). However, Bayesian convolutional neural networks (BCNNs), one of the representative algorithms of Bayesian deep learning, have not yet been implemented using memristors. The unique attribute of local weight connection of convolutional kernels poses a challenge in constructing Gaussian weights. In this work, a highly energy-efficient implementation method of probabilistic convolutional kernels in memristor-based BCNN is developed, which takes advantage of both the write and read variations of devices. Meanwhile, a Bayesian-based hardware-aware ex-situ training method for memristor-based BCNNs is proposed for further deployment on large-scale BCNNs. Incorporating HfOx-based memristor’s parameters, memristor BCNNs are used to demonstrate classification task and out-of-distribution detection (OOD) by estimating uncertainty for the first time. The two memristor BCNNs achieved accuracies of 98.67% on MNIST and 87.81% on CIFAR10 and area under the ROC curve (AUC) of 0.96 and 0.83, indicating comparable classification and OOD detection performance to the digital floating-point implementation. After analyzing the impact of various effects at the device and array level, including the read variation, write variation, retention, conductance weight level, and ADC bit widths, the proposed method shows high robustness. Moreover, compared with CMOS-based GPUs, our memristor-based system achieved a 12-fold speed increase and a 335-fold energy efficiency improvement during the prediction cycle.
利用忆阻器的非易失性和随机性，忆阻器交叉棒阵列可以有效地加速贝叶斯神经网络（BNNs）。然而，贝叶斯卷积神经网络（BCNNs）作为贝叶斯深度学习的代表算法之一，尚未使用忆阻器实现。卷积核局部权值连接的独特属性给高斯权值的构造带来了挑战。在这项工作中，开发了一种高效节能的基于记忆电阻器的BCNN概率卷积核实现方法，该方法充分利用了器件的写入和读取变化。同时，提出了一种基于贝叶斯的基于记忆电阻器的bcnn的硬件感知非原位训练方法，以便在大规模的bcnn上进一步部署。结合基于hfox的忆阻器参数，首次将忆阻器bcnn应用于分类任务和预估不确定性的out- distribution detection （OOD）。这两种忆阻器bcnn在MNIST和CIFAR10上的准确率分别为98.67%和87.81%，ROC曲线下面积（AUC）分别为0.96和0.83，表明分类和OOD检测性能与数字浮点实现相当。在分析了器件和阵列层面的各种影响（包括读变化、写变化、保持、电导权重水平和ADC位宽度）后，所提出的方法具有较高的鲁棒性。此外，与基于cmos的gpu相比，我们基于忆阻器的系统在预测周期内实现了12倍的速度提升和335倍的能效提升。
{"title":"High-Efficient Memristor-Based Bayesian Convolutional Neural Networks for Out-of-Distribution Detection by Uncertainty Estimation","authors":"Yudeng Lin;Qingtian Zhang;Bin Gao;Jianshi Tang;Han Zhao;Qi Qin;Ze Wang;He Qian;Huaqiang Wu","doi":"10.1109/TED.2024.3497917","DOIUrl":"https://doi.org/10.1109/TED.2024.3497917","url":null,"abstract":"By using the nonvolatile and stochastic properties of memristor, memristors crossbar arrays can efficiently accelerate Bayesian neural networks (BNNs). However, Bayesian convolutional neural networks (BCNNs), one of the representative algorithms of Bayesian deep learning, have not yet been implemented using memristors. The unique attribute of local weight connection of convolutional kernels poses a challenge in constructing Gaussian weights. In this work, a highly energy-efficient implementation method of probabilistic convolutional kernels in memristor-based BCNN is developed, which takes advantage of both the write and read variations of devices. Meanwhile, a Bayesian-based hardware-aware ex-situ training method for memristor-based BCNNs is proposed for further deployment on large-scale BCNNs. Incorporating HfOx-based memristor’s parameters, memristor BCNNs are used to demonstrate classification task and out-of-distribution detection (OOD) by estimating uncertainty for the first time. The two memristor BCNNs achieved accuracies of 98.67% on MNIST and 87.81% on CIFAR10 and area under the ROC curve (AUC) of 0.96 and 0.83, indicating comparable classification and OOD detection performance to the digital floating-point implementation. After analyzing the impact of various effects at the device and array level, including the read variation, write variation, retention, conductance weight level, and ADC bit widths, the proposed method shows high robustness. Moreover, compared with CMOS-based GPUs, our memristor-based system achieved a 12-fold speed increase and a 335-fold energy efficiency improvement during the prediction cycle.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"206-214"},"PeriodicalIF":2.9,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TED.2024.3496654
Karuna Kumari;Subhasmita Kar;Saurav Kumar;Soumya Jyoti Ray
The present work highlights the effect of reduced graphene oxide (rGO) on structural and charge transport properties of ( ${1} {-} {x}$ ) lanthanum manganite (LaMnO3). (x) rGO nanocomposites. The presence of dual phases within the nanocomposite specimens was well-established through comprehensive analysis employing characterization techniques, such as X-ray diffraction (XRD), Raman spectroscopy, and field-effect scanning electron microscopy (FESEM) etc. Furthermore, two distinct lattice spacings were identified by high-resolution transmission electron microscopy (HRTEM) measurements. Notably, the current versus voltage (I–V) profiles of the nanocomposites unveiled a distinctive bipolar resistive switching (RS) behavior. It was found that the increased concentration of rGO instigated an oxygen-deficient region, a phenomenon conclusively corroborated through X-ray photoelectron spectroscopy (XPS) analysis. Consequently, oxygen vacancies and ions alter the RS behavior of LaMnO3. Remarkably, the sample with ${x} =0.001$ exhibited superior RS characteristics when compared to ${x} =0.002$ and 0.005 samples. The conduction mechanism was found to be primarily governed by Ohmic and Schottky emission phenomena. The experimentally observed effect of rGO on RS property was also corroborated through first-principles-based calculations to offer a good degree of agreement. An increase in rGO concentration (x) reduces the bandgap, which brings about a semiconductor-to-metallic transition in the host material.
{"title":"Investigating the Role of Reduced Graphene Oxide on the Structural and Transport Properties of LaMnO3","authors":"Karuna Kumari;Subhasmita Kar;Saurav Kumar;Soumya Jyoti Ray","doi":"10.1109/TED.2024.3496654","DOIUrl":"https://doi.org/10.1109/TED.2024.3496654","url":null,"abstract":"The present work highlights the effect of reduced graphene oxide (rGO) on structural and charge transport properties of (\u0000<inline-formula> <tex-math>${1} {-} {x}$ </tex-math></inline-formula>\u0000) lanthanum manganite (LaMnO3). (x) rGO nanocomposites. The presence of dual phases within the nanocomposite specimens was well-established through comprehensive analysis employing characterization techniques, such as X-ray diffraction (XRD), Raman spectroscopy, and field-effect scanning electron microscopy (FESEM) etc. Furthermore, two distinct lattice spacings were identified by high-resolution transmission electron microscopy (HRTEM) measurements. Notably, the current versus voltage (I–V) profiles of the nanocomposites unveiled a distinctive bipolar resistive switching (RS) behavior. It was found that the increased concentration of rGO instigated an oxygen-deficient region, a phenomenon conclusively corroborated through X-ray photoelectron spectroscopy (XPS) analysis. Consequently, oxygen vacancies and ions alter the RS behavior of LaMnO3. Remarkably, the sample with \u0000<inline-formula> <tex-math>${x} =0.001$ </tex-math></inline-formula>\u0000 exhibited superior RS characteristics when compared to \u0000<inline-formula> <tex-math>${x} =0.002$ </tex-math></inline-formula>\u0000 and 0.005 samples. The conduction mechanism was found to be primarily governed by Ohmic and Schottky emission phenomena. The experimentally observed effect of rGO on RS property was also corroborated through first-principles-based calculations to offer a good degree of agreement. An increase in rGO concentration (x) reduces the bandgap, which brings about a semiconductor-to-metallic transition in the host material.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"482-487"},"PeriodicalIF":2.9,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-22DOI: 10.1109/TED.2024.3497927
Vitor A. P. Aguiar;Nilberto H. Medina;Nemitala Added;Saulo G. Alberton;Eduardo L. A. Macchione;Marcilei A. Guazzelli;Marco A. A. Melo;Juliano A. Oliveira;Renato C. Giacomini;Fernando R. Aguirre;Paula R. P. Allegro;Hellen C. S. Zaggato;Isaac J. Sayeg
Charge funneling is a widely used description of charge collection dynamics in semiconductor devices struck by ion irradiation, but it still relies on semiempirical parameters heavily dependent upon available data, which impacts its use for device or circuit-level simulations. The objective of this article is to analyze a comprehensive dataset from low-energy heavy-ion irradiations on a p-MOSFET, varying both the linear energy transfer (LET) and ion penetration depth within the device. A novel methodology is proposed to achieve this goal by analyzing devices without prior knowledge of their parameters, using data from light ion irradiations. Statistical analysis of the data and comparisons to simulated values showed that a LET-dependent funnel length is a more accurate description of the phenomenon than the conventional constant-length approach. A new, lower value for the funnel model’s shielding parameter k was identified, and the method also allowed for determining the metal and passivation layer thicknesses of the device. These results strengthen the reliability of the funnel model, making it a more robust tool for simulation applications.
{"title":"Evaluation of Funnel Models on Calculation of Ion-Induced Collected Charge","authors":"Vitor A. P. Aguiar;Nilberto H. Medina;Nemitala Added;Saulo G. Alberton;Eduardo L. A. Macchione;Marcilei A. Guazzelli;Marco A. A. Melo;Juliano A. Oliveira;Renato C. Giacomini;Fernando R. Aguirre;Paula R. P. Allegro;Hellen C. S. Zaggato;Isaac J. Sayeg","doi":"10.1109/TED.2024.3497927","DOIUrl":"https://doi.org/10.1109/TED.2024.3497927","url":null,"abstract":"Charge funneling is a widely used description of charge collection dynamics in semiconductor devices struck by ion irradiation, but it still relies on semiempirical parameters heavily dependent upon available data, which impacts its use for device or circuit-level simulations. The objective of this article is to analyze a comprehensive dataset from low-energy heavy-ion irradiations on a p-MOSFET, varying both the linear energy transfer (LET) and ion penetration depth within the device. A novel methodology is proposed to achieve this goal by analyzing devices without prior knowledge of their parameters, using data from light ion irradiations. Statistical analysis of the data and comparisons to simulated values showed that a LET-dependent funnel length is a more accurate description of the phenomenon than the conventional constant-length approach. A new, lower value for the funnel model’s shielding parameter k was identified, and the method also allowed for determining the metal and passivation layer thicknesses of the device. These results strengthen the reliability of the funnel model, making it a more robust tool for simulation applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"31-36"},"PeriodicalIF":2.9,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-22DOI: 10.1109/TED.2024.3499943
Z. Zhang;J. C. Cai;P. C. Yin;Z. X. Su;X. K. Zhang;C. Zhang;L. Zeng;J. Xu;L. N. Yue;H. R. Yin;Y. Xu;G. Q. Zhao;W. X. Wang;Y. Y. Wei
In order to overcome the low efficiency (usually less than 25%) of millimeter-wave and terahertz (MMW/THz) klystrons, an exploratory study is conducted to improve the efficiency in the design of W-band extended interaction klystrons (EIKs). In this article, fast large-signal simulations using KlyC code are comprehensively used for the first time to accurately conduct full-scale parameterization of EIK, it is found that the upper limit of terahertz klystron efficiency is no longer solely dominated via the beam perveance, but rather restricted by various factors, including effective impedance, ohmic loss, cavity arrangement, and so on. The physical mechanism involved is so complex that the preliminary parametric sortation is mandatory to achieve very high efficiency (HE). Particle-in-cell (PIC) simulation results verified our theoretical evaluations, demonstrating that the W-band EIK proposed and optimized in this article could deliver up to 44.5% electronic efficiency and 39.2% RF efficiency around 100 GHz, with operating beam voltage of 50 kV and beam current of 2 A. The output power and saturation gain could achieve 39.2 kW and 65.5 dB, respectively, in which no instability is observed. In addition, a novel beam optics system (BOS) based on hybrid permanent magnets is proposed. Such compact BOS is exclusively developed to deal with the challenge induced by severe radial beam expansion in this EIK, which is the side-effect of the high intensity of beam-wave interactions. This study on high-power (HP) HE compact W-band EIK reveals the true potential of such types of devices in the MMW/THz regime.
{"title":"Study on a High-Power W -Band Extended Interaction Klystron With Efficiency Toward 44%","authors":"Z. Zhang;J. C. Cai;P. C. Yin;Z. X. Su;X. K. Zhang;C. Zhang;L. Zeng;J. Xu;L. N. Yue;H. R. Yin;Y. Xu;G. Q. Zhao;W. X. Wang;Y. Y. Wei","doi":"10.1109/TED.2024.3499943","DOIUrl":"https://doi.org/10.1109/TED.2024.3499943","url":null,"abstract":"In order to overcome the low efficiency (usually less than 25%) of millimeter-wave and terahertz (MMW/THz) klystrons, an exploratory study is conducted to improve the efficiency in the design of W-band extended interaction klystrons (EIKs). In this article, fast large-signal simulations using KlyC code are comprehensively used for the first time to accurately conduct full-scale parameterization of EIK, it is found that the upper limit of terahertz klystron efficiency is no longer solely dominated via the beam perveance, but rather restricted by various factors, including effective impedance, ohmic loss, cavity arrangement, and so on. The physical mechanism involved is so complex that the preliminary parametric sortation is mandatory to achieve very high efficiency (HE). Particle-in-cell (PIC) simulation results verified our theoretical evaluations, demonstrating that the W-band EIK proposed and optimized in this article could deliver up to 44.5% electronic efficiency and 39.2% RF efficiency around 100 GHz, with operating beam voltage of 50 kV and beam current of 2 A. The output power and saturation gain could achieve 39.2 kW and 65.5 dB, respectively, in which no instability is observed. In addition, a novel beam optics system (BOS) based on hybrid permanent magnets is proposed. Such compact BOS is exclusively developed to deal with the challenge induced by severe radial beam expansion in this EIK, which is the side-effect of the high intensity of beam-wave interactions. This study on high-power (HP) HE compact W-band EIK reveals the true potential of such types of devices in the MMW/THz regime.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"424-431"},"PeriodicalIF":2.9,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-21DOI: 10.1109/TED.2024.3499949
Shi Zong;Lei Xu;Ruyu Liang;Zengcai Song;Junming Li;Zhihua Zhu;Shijun Luo
In this work, a low-temperature co-sputtering method was employed to fabricate high-performance amorphous InSnMgO (ITMO) thin film transistors (TFTs) with ultrathin channels. The effects of different Mg content on the electrical properties and bias stability of ITMO TFTs were studied by various characterization methods. As a result, when the sputtering power of MgO was set to 80 W, the field effect mobility ( $mu _{text {FE}}$ ) reached 52.5 cm2/V $cdot $ s, the low threshold voltage ( ${V}_{text {th}}$ ) of −0.28 V, and the subthreshold swing (SS) was as low as 0.239 V/decade. The super performance of the device is attributed to the reduction of oxygen vacancy concentration and the optimization of carrier concentration in the channel due to the doping of Mg. This study confirms the potential application of ITMO TFTs in the field of transparent flexible electronic devices and is expected to become a promising material for the next generation of high-resolution, low-power flat panel displays.
{"title":"Enhance Electrical Performance and Stability of InSnMgO Thin-Film Transistors by Optimizing Carrier Concentration via Mg Doping","authors":"Shi Zong;Lei Xu;Ruyu Liang;Zengcai Song;Junming Li;Zhihua Zhu;Shijun Luo","doi":"10.1109/TED.2024.3499949","DOIUrl":"https://doi.org/10.1109/TED.2024.3499949","url":null,"abstract":"In this work, a low-temperature co-sputtering method was employed to fabricate high-performance amorphous InSnMgO (ITMO) thin film transistors (TFTs) with ultrathin channels. The effects of different Mg content on the electrical properties and bias stability of ITMO TFTs were studied by various characterization methods. As a result, when the sputtering power of MgO was set to 80 W, the field effect mobility (\u0000<inline-formula> <tex-math>$mu _{text {FE}}$ </tex-math></inline-formula>\u0000) reached 52.5 cm2/V\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000s, the low threshold voltage (\u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000) of −0.28 V, and the subthreshold swing (SS) was as low as 0.239 V/decade. The super performance of the device is attributed to the reduction of oxygen vacancy concentration and the optimization of carrier concentration in the channel due to the doping of Mg. This study confirms the potential application of ITMO TFTs in the field of transparent flexible electronic devices and is expected to become a promising material for the next generation of high-resolution, low-power flat panel displays.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"277-281"},"PeriodicalIF":2.9,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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