Pub Date : 2025-08-05DOI: 10.1109/TED.2025.3593922
M. Rack;D. Lederer;J.-P. Raskin
This article delves into the detailed design and performance analysis of a mm-wave single-pole double-throw (SPDT) switch, fabricated in the GlobalFoundries 22-nm fully depleted silicon-on-insulator (FD-SOI) process on several types on silicon wafer, from standard-resistivity $10~Omega cdot $ cm ones to high-resistivity 620-$Omega cdot $ cm variants. Building upon the foundational results presented in Part I, this work investigates the specific impedance paths and parasitic effects introduced by the substrate in a full SPDT switch layout and highlights the radio frequency (RF) performance gains that are achievable by employing silicon substrates that have simultaneously high interface and bulk resistivity values. A detailed extraction of equivalent impedance paths is performed to quantify the contributions of both the bulk and interface resistivity, with a particular emphasis on the regions of the layout where these parasitics have the most significant effect on insertion loss (IL) and signal integrity. Electromagnetic (EM) simulations are used to model the switch layout with accuracy, enabling a thorough analysis of the coupling mechanisms. The impact of the optimized high-resistivity (HR) substrate and interface passivation techniques is explored further, showing their critical role in mitigating parasitic losses at mm-wave frequencies. This work provides valuable insights into substrate-induced performance degradation in high-frequency circuit modules and presents a comprehensive modeling approach to predict and mitigate these effects.
{"title":"High-Resistivity Substrates in 22-nm FD-SOI—Part II: Impact on mm-Wave SPDT Performance","authors":"M. Rack;D. Lederer;J.-P. Raskin","doi":"10.1109/TED.2025.3593922","DOIUrl":"https://doi.org/10.1109/TED.2025.3593922","url":null,"abstract":"This article delves into the detailed design and performance analysis of a mm-wave single-pole double-throw (SPDT) switch, fabricated in the GlobalFoundries 22-nm fully depleted silicon-on-insulator (FD-SOI) process on several types on silicon wafer, from standard-resistivity <inline-formula> <tex-math>$10~Omega cdot $ </tex-math></inline-formula>cm ones to high-resistivity 620-<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm variants. Building upon the foundational results presented in Part I, this work investigates the specific impedance paths and parasitic effects introduced by the substrate in a full SPDT switch layout and highlights the radio frequency (RF) performance gains that are achievable by employing silicon substrates that have simultaneously high interface and bulk resistivity values. A detailed extraction of equivalent impedance paths is performed to quantify the contributions of both the bulk and interface resistivity, with a particular emphasis on the regions of the layout where these parasitics have the most significant effect on insertion loss (IL) and signal integrity. Electromagnetic (EM) simulations are used to model the switch layout with accuracy, enabling a thorough analysis of the coupling mechanisms. The impact of the optimized high-resistivity (HR) substrate and interface passivation techniques is explored further, showing their critical role in mitigating parasitic losses at mm-wave frequencies. This work provides valuable insights into substrate-induced performance degradation in high-frequency circuit modules and presents a comprehensive modeling approach to predict and mitigate these effects.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5236-5242"},"PeriodicalIF":3.2,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article explores the impact of the substrate network on the high-frequency performance characteristics of silicon/silicon–germanium (Si/SiGe) heterojunction bipolar transistors (HBTs). The influence of the substrate network becomes particularly significant at frequencies above 100 GHz, necessitating advanced measurement and de-embedding techniques. In this study, we employ the advanced 16-term error calibration method to accurately extract the maximum oscillation frequency (${f}_{text {MAX}}text {)}$ up to 500 GHz. This approach allows us to observe second-order effects, such as the impact of substrate network, for the first time. Our findings reveal that the substrate network has significant implications for the optimization of high-frequency Si/SiGe HBTs, especially on ${f}_{text {MAX}}$ . The study provides insights into substrate-related parasitic effects and proposes strategies to mitigate these effects.
{"title":"Investigating Substrate Network Effects on Si/SiGe HBT Performance Up to 500 GHz","authors":"Philippine Billy;Nicolas Guitard;Thomas Zimmer;Alexis Gauthier;Pascal Chevalier;Sébastien Fregonese","doi":"10.1109/TED.2025.3593217","DOIUrl":"https://doi.org/10.1109/TED.2025.3593217","url":null,"abstract":"This article explores the impact of the substrate network on the high-frequency performance characteristics of silicon/silicon–germanium (Si/SiGe) heterojunction bipolar transistors (HBTs). The influence of the substrate network becomes particularly significant at frequencies above 100 GHz, necessitating advanced measurement and de-embedding techniques. In this study, we employ the advanced 16-term error calibration method to accurately extract the maximum oscillation frequency (<inline-formula> <tex-math>${f}_{text {MAX}}text {)}$ </tex-math></inline-formula> up to 500 GHz. This approach allows us to observe second-order effects, such as the impact of substrate network, for the first time. Our findings reveal that the substrate network has significant implications for the optimization of high-frequency Si/SiGe HBTs, especially on <inline-formula> <tex-math>${f}_{text {MAX}}$ </tex-math></inline-formula>. The study provides insights into substrate-related parasitic effects and proposes strategies to mitigate these effects.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4721-4727"},"PeriodicalIF":3.2,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-05DOI: 10.1109/TED.2025.3592634
Ying-Qi Liu;Bo-Wei Huang;Chun-Yi Cheng;Wei-Jen Chen;Min-Kuan Lin;Yi Huang;Ding-Wei Lin;C. W. Liu
A novel device integration scheme for dual-work-function-metal split-gate complementary FETs (CFETs) is demonstrated. Multiple p/n junctions are used to electrically isolate the vertically stacked transistors. The effective work function (EWF) of WNxCy is modulated by the N2/H2 flow ratio during the plasma-enhanced atomic layer deposition (PEALD) process. A ~10-nm-thick WNxCy layer enables ${V}_{text {TP}}$ (threshold voltage of pFETs) tunability up to 500 mV, while TiN is used as work function metal (WFM) for nFETs. The dual-WFM split-gate architecture achieves well-balanced threshold voltages, with a $vert {V}_{text {TP}}vert $ /$vert {V}_{text {TN}}vert $ ratio of 0.93. Furthermore, the CFET inverter with dual WFMs and split gate reaches a record-high voltage gain of 61 V/V among reported monolithic nanosheet CFETs.
{"title":"VₜTuning of Split-Gate GeSi Nanosheet CFETs With Dual Work Function Metals","authors":"Ying-Qi Liu;Bo-Wei Huang;Chun-Yi Cheng;Wei-Jen Chen;Min-Kuan Lin;Yi Huang;Ding-Wei Lin;C. W. Liu","doi":"10.1109/TED.2025.3592634","DOIUrl":"https://doi.org/10.1109/TED.2025.3592634","url":null,"abstract":"A novel device integration scheme for dual-work-function-metal split-gate complementary FETs (CFETs) is demonstrated. Multiple p/n junctions are used to electrically isolate the vertically stacked transistors. The effective work function (EWF) of WNxCy is modulated by the N2/H2 flow ratio during the plasma-enhanced atomic layer deposition (PEALD) process. A ~10-nm-thick WNxCy layer enables <inline-formula> <tex-math>${V}_{text {TP}}$ </tex-math></inline-formula> (threshold voltage of pFETs) tunability up to 500 mV, while TiN is used as work function metal (WFM) for nFETs. The dual-WFM split-gate architecture achieves well-balanced threshold voltages, with a <inline-formula> <tex-math>$vert {V}_{text {TP}}vert $ </tex-math></inline-formula>/<inline-formula> <tex-math>$vert {V}_{text {TN}}vert $ </tex-math></inline-formula> ratio of 0.93. Furthermore, the CFET inverter with dual WFMs and split gate reaches a record-high voltage gain of 61 V/V among reported monolithic nanosheet CFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4708-4713"},"PeriodicalIF":3.2,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-05DOI: 10.1109/TED.2025.3593465
Mohit Kumar Joshi;Vincent Da Costa;Muhammad Zubair;Ahsan Altaf;Rosa Letizia;Claudio Paoloni
Ka-band (26–40 GHz) is widely used for satellite links. In particular, the 26.5–29.5-GHz band is mostly used for uplink in low-Earth-orbit (LEO) constellations and is also part of the FR2 (24.25–52.6 GHz) for high-capacity terrestrial links. The addition of the 26.5–29.5-GHz band for downlink would increase the satellite throughput, but presently, solid-state power amplifier (SSPA) modules do not provide enough power and have too low efficiency. Ka-band traveling wave tubes (TWTs) are traditionally used in geostationary Earth orbit (GEO) satellites for their high transmission power and high efficiency. Compact and affordable Ka-band TWTs would be a promising solution to provide transmission power to enable downlink at the Ka-band. Meander lines (MLs) have been extensively investigated as slow wave structures (SWSs) for lightweight, small dimensions, and low voltage operation. In this article, an interaction circuit for compact and affordable Ka-band TWTs based on the ML (ML-TWT) is discussed. The first TWT with two ML sections interacting with an elliptical sheet beam with 4.56-kV beam voltage, in the 26.5–29.5-GHz frequency range, is proposed. More than 31-W output power with about 38-dB gain in the linear region is achieved. A single-section ML-SWS and a sever for the two-section ML-TWT are fabricated and measured. The compact dimensions and low voltage of the novel ML-TWT make it a competitive solution for medium transmission power in the future Ka-band high-capacity LEO satellite and terrestrial links for future 5G and 6G network integration.
{"title":"Ka-Band Meander-Line Slow Wave Structure Design for Traveling Wave Tube for High Data Rate Wireless Links","authors":"Mohit Kumar Joshi;Vincent Da Costa;Muhammad Zubair;Ahsan Altaf;Rosa Letizia;Claudio Paoloni","doi":"10.1109/TED.2025.3593465","DOIUrl":"https://doi.org/10.1109/TED.2025.3593465","url":null,"abstract":"Ka-band (26–40 GHz) is widely used for satellite links. In particular, the 26.5–29.5-GHz band is mostly used for uplink in low-Earth-orbit (LEO) constellations and is also part of the FR2 (24.25–52.6 GHz) for high-capacity terrestrial links. The addition of the 26.5–29.5-GHz band for downlink would increase the satellite throughput, but presently, solid-state power amplifier (SSPA) modules do not provide enough power and have too low efficiency. Ka-band traveling wave tubes (TWTs) are traditionally used in geostationary Earth orbit (GEO) satellites for their high transmission power and high efficiency. Compact and affordable Ka-band TWTs would be a promising solution to provide transmission power to enable downlink at the Ka-band. Meander lines (MLs) have been extensively investigated as slow wave structures (SWSs) for lightweight, small dimensions, and low voltage operation. In this article, an interaction circuit for compact and affordable Ka-band TWTs based on the ML (ML-TWT) is discussed. The first TWT with two ML sections interacting with an elliptical sheet beam with 4.56-kV beam voltage, in the 26.5–29.5-GHz frequency range, is proposed. More than 31-W output power with about 38-dB gain in the linear region is achieved. A single-section ML-SWS and a sever for the two-section ML-TWT are fabricated and measured. The compact dimensions and low voltage of the novel ML-TWT make it a competitive solution for medium transmission power in the future Ka-band high-capacity LEO satellite and terrestrial links for future 5G and 6G network integration.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5216-5222"},"PeriodicalIF":3.2,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-05DOI: 10.1109/TED.2025.3594268
M. Rack;D. Lederer;J.-P. Raskin
This article examines how the bulk and interface resistivity of silicon substrates influence the RF performance of devices fabricated in 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. To investigate this, coplanar waveguides (CPWs) were designed and manufactured using GlobalFoundries’ 22FDX (Registered trademark) process on a range of substrates, from standard 10-$Omega $ cm silicon wafers to high-resistivity (HR) 620-$Omega $ cm wafers. In addition, various silicon-interface conditions were explored, introducing process variations in interface resistivity alongside changes in bulk resistivity. To achieve high interfacial resistivity, a series of p-n junctions were implemented at the interface, and these are proven to drastically reduce RF losses. From the CPW line measurement data, interface and bulk resistivity values were extracted for all six considered substrate variations. The extraction of these properties enables modeling of the materials present in all substrate stacks and permits electromagnetic (EM) simulations of various RF layouts of various shapes, functions and characteristic dimensions, such as spiral inductors and mm-wave single-pole double-throw (SPDT) switches. Such simulations are shown to correlate well to the measured data using the calibrated material stack description. This work demonstrates the impact of the substrate’s bulk and interface properties on the losses and quality of these devices and highlights the necessity for an effective interface passivation technique and appropriate modeling.
{"title":"High-Resistivity Substrates in 22-nm FD-SOI—Part I: Wideband Modeling and Impact on RF Losses","authors":"M. Rack;D. Lederer;J.-P. Raskin","doi":"10.1109/TED.2025.3594268","DOIUrl":"https://doi.org/10.1109/TED.2025.3594268","url":null,"abstract":"This article examines how the bulk and interface resistivity of silicon substrates influence the RF performance of devices fabricated in 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. To investigate this, coplanar waveguides (CPWs) were designed and manufactured using GlobalFoundries’ 22FDX (Registered trademark) process on a range of substrates, from standard 10-<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>cm silicon wafers to high-resistivity (HR) 620-<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>cm wafers. In addition, various silicon-interface conditions were explored, introducing process variations in interface resistivity alongside changes in bulk resistivity. To achieve high interfacial resistivity, a series of p-n junctions were implemented at the interface, and these are proven to drastically reduce RF losses. From the CPW line measurement data, interface and bulk resistivity values were extracted for all six considered substrate variations. The extraction of these properties enables modeling of the materials present in all substrate stacks and permits electromagnetic (EM) simulations of various RF layouts of various shapes, functions and characteristic dimensions, such as spiral inductors and mm-wave single-pole double-throw (SPDT) switches. Such simulations are shown to correlate well to the measured data using the calibrated material stack description. This work demonstrates the impact of the substrate’s bulk and interface properties on the losses and quality of these devices and highlights the necessity for an effective interface passivation technique and appropriate modeling.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5229-5235"},"PeriodicalIF":3.2,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-04DOI: 10.1109/TED.2025.3592917
Yiping Zhang;Shunpeng Lu;Baiquan Liu;Huayu Gao;Yubu Zhou;Wenhui Fang;Zi-Hui Zhang;Swee Tiam Tan;Hilmi Volkan Demir;Xiao Wei Sun
Light-emitting diodes (LEDs) are essential for future energy-saving lighting and display technology owing to their high efficiency, long lifetime, and low cost. To further enhance the performance of GaN-based LEDs, electroluminescent (EL) cooling has been widely predicted to be useful over the past several decades; however, it has not been experimentally achieved. Herein, thermoelectric and phonon-pumped GaN-based LEDs have been demonstrated by both experimental measurements and theoretical modeling. It is surprisingly found that the effect of increasing temperature changes from negative to positive when the operating point is moved to the high-efficiency, midvoltage range. The power efficiency exhibits a maximum 2.24-fold improvement with increasing temperature (from room temperature to 473 K), and the peak efficiency at all elevated temperatures outperforms that at room temperature, where the Peltier effect changes from Peltier heat to Peltier cooling. Under lower biases, the phonon-assisted Peltier cooling provides additional energy for carriers to overcome the potential barrier and achieve recombination. The findings not only give an insightful understanding of EL cooling but also provide guidelines on thermal management and designing high-performance GaN-based LED devices and arrays (e.g., micro-LEDs), which can be further extended to other kinds of LEDs and optoelectronic devices.
{"title":"Observation of Peltier Cooling and Great Potential of Electroluminescent Cooling in GaN-Based Light-Emitting Diodes","authors":"Yiping Zhang;Shunpeng Lu;Baiquan Liu;Huayu Gao;Yubu Zhou;Wenhui Fang;Zi-Hui Zhang;Swee Tiam Tan;Hilmi Volkan Demir;Xiao Wei Sun","doi":"10.1109/TED.2025.3592917","DOIUrl":"https://doi.org/10.1109/TED.2025.3592917","url":null,"abstract":"Light-emitting diodes (LEDs) are essential for future energy-saving lighting and display technology owing to their high efficiency, long lifetime, and low cost. To further enhance the performance of GaN-based LEDs, electroluminescent (EL) cooling has been widely predicted to be useful over the past several decades; however, it has not been experimentally achieved. Herein, thermoelectric and phonon-pumped GaN-based LEDs have been demonstrated by both experimental measurements and theoretical modeling. It is surprisingly found that the effect of increasing temperature changes from negative to positive when the operating point is moved to the high-efficiency, midvoltage range. The power efficiency exhibits a maximum 2.24-fold improvement with increasing temperature (from room temperature to 473 K), and the peak efficiency at all elevated temperatures outperforms that at room temperature, where the Peltier effect changes from Peltier heat to Peltier cooling. Under lower biases, the phonon-assisted Peltier cooling provides additional energy for carriers to overcome the potential barrier and achieve recombination. The findings not only give an insightful understanding of EL cooling but also provide guidelines on thermal management and designing high-performance GaN-based LED devices and arrays (e.g., micro-LEDs), which can be further extended to other kinds of LEDs and optoelectronic devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5060-5066"},"PeriodicalIF":3.2,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work demonstrated a solar-blind ultraviolet (UV) photodetector (PD) based on a ferroelectric polarization-engineered BTO/AlXGa1-XN heterostructure. The key innovation lied in exploiting BTO’s switchable spontaneous polarization to actively modulate interfacial electrostatics, creating a polarization-coupled carrier transport channel that fundamentally overcame the inherent carrier transport limitations of AlGaN materials. This mechanism synergistically enhanced the built-in electric field and optimized band alignment, which facilitated photogenerated carrier transport. The resultant device achieved high responsivity and detectivity while maintaining intrinsic solar-blind selectivity, significantly surpassing conventional AlGaN-based detectors. Furthermore, we validate its practical utility through UV imaging and accurate optical communication signal decoding, establishing new possibilities for advanced optoelectronic systems.
{"title":"Solar-Blind UV PD Based on the BTO/AlXGa1-XN Heterostructure for Imaging and Optical Communication","authors":"Xu Qi;Leyang Qian;Xuekun Hong;Bingjie Ye;Huazhan Sun;Anqi Qiang;Yushen Liu;Irina Nikolaevna Parkhomenko;Fadei Fadeevich Komarov;Jun-Ge Liang;Xinyi Shan;Guofeng Yang","doi":"10.1109/TED.2025.3591742","DOIUrl":"https://doi.org/10.1109/TED.2025.3591742","url":null,"abstract":"This work demonstrated a solar-blind ultraviolet (UV) photodetector (PD) based on a ferroelectric polarization-engineered BTO/AlXGa1-XN heterostructure. The key innovation lied in exploiting BTO’s switchable spontaneous polarization to actively modulate interfacial electrostatics, creating a polarization-coupled carrier transport channel that fundamentally overcame the inherent carrier transport limitations of AlGaN materials. This mechanism synergistically enhanced the built-in electric field and optimized band alignment, which facilitated photogenerated carrier transport. The resultant device achieved high responsivity and detectivity while maintaining intrinsic solar-blind selectivity, significantly surpassing conventional AlGaN-based detectors. Furthermore, we validate its practical utility through UV imaging and accurate optical communication signal decoding, establishing new possibilities for advanced optoelectronic systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5054-5059"},"PeriodicalIF":3.2,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/TED.2025.3593216
Mojtaba Alaei;Herbert De Pauw;Elena Fabris;Stefaan Decoutere;Jan Doutreloigne;Johan Lauwaert;Benoit Bakeroot
Experimental data from gallium nitride (GaN)-on-Si p-GaN gate high-electron-mobility transistors (HEMTs) reveal a strong dependence of terminal capacitances-particularly $C_{mathrm{BS}}, C_{mathrm{BG}}$ , and $C_{mathrm{BD}}$ -on the drain-to-source voltage ($V_{mathrm{DS}}$ ), indicating significant coupling through the bulk contact. This behavior, linked to progressive depletion of the 2-D electron gas (2DEG) under field plates, is not adequately captured by existing compact models. This work presents a detailed analysis of the dynamics of $V_{text {DS }}$ -dependent depletion under field plates and develops an enhanced MIT Virtual Source GaN FET (MVSG) compact model that incorporates bulk-related capacitance contributions. The proposed model introduces a depletion-dependent modulation of channel and fringing capacitances and captures channel length modulation (CLM) effects due to progressive depletion of 2DEG with increasing $V_{text {DS }}$ . The extended model shows excellent agreement with the measured capacitance behavior and provides a deeper understanding of the substrate interaction mechanisms. This advancement supports the design of next-generation high-voltage GaN power ICs, such as integrated half-bridges and gate drivers, by enabling accurate prediction of terminal capacitances in simulations that include substrate effects.
{"title":"Modeling and Analysis of Terminal Capacitances in High-Power Devices: Application to p-GaN Gate HEMTs","authors":"Mojtaba Alaei;Herbert De Pauw;Elena Fabris;Stefaan Decoutere;Jan Doutreloigne;Johan Lauwaert;Benoit Bakeroot","doi":"10.1109/TED.2025.3593216","DOIUrl":"https://doi.org/10.1109/TED.2025.3593216","url":null,"abstract":"Experimental data from gallium nitride (GaN)-on-Si p-GaN gate high-electron-mobility transistors (HEMTs) reveal a strong dependence of terminal capacitances-particularly <inline-formula> <tex-math>$C_{mathrm{BS}}, C_{mathrm{BG}}$ </tex-math></inline-formula>, and <inline-formula> <tex-math>$C_{mathrm{BD}}$ </tex-math></inline-formula>-on the drain-to-source voltage (<inline-formula> <tex-math>$V_{mathrm{DS}}$ </tex-math></inline-formula>), indicating significant coupling through the bulk contact. This behavior, linked to progressive depletion of the 2-D electron gas (2DEG) under field plates, is not adequately captured by existing compact models. This work presents a detailed analysis of the dynamics of <inline-formula> <tex-math>$V_{text {DS }}$ </tex-math></inline-formula>-dependent depletion under field plates and develops an enhanced MIT Virtual Source GaN FET (MVSG) compact model that incorporates bulk-related capacitance contributions. The proposed model introduces a depletion-dependent modulation of channel and fringing capacitances and captures channel length modulation (CLM) effects due to progressive depletion of 2DEG with increasing <inline-formula> <tex-math>$V_{text {DS }}$ </tex-math></inline-formula>. The extended model shows excellent agreement with the measured capacitance behavior and provides a deeper understanding of the substrate interaction mechanisms. This advancement supports the design of next-generation high-voltage GaN power ICs, such as integrated half-bridges and gate drivers, by enabling accurate prediction of terminal capacitances in simulations that include substrate effects.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4817-4823"},"PeriodicalIF":3.2,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/TED.2025.3588834
Xi Jiang;Jing Chen;Chaofan Pan;Hao Niu;Song Yuan;Xiangdong Li;Zhaoheng Yan;Xiaowu Gong;Daming Wang;Jun Wang
This article investigates the failure mechanisms of the gallium nitride high electron mobility transistors (GaN HEMTs) under overcurrent stress. The overcurrent behavior of GaN hybrid drain-embedded gate injection transistor (HD-GIT) devices was evaluated under different stress conditions, and the primary failure modes were identified. The waveforms of the GaN devices during overcurrent events were analyzed in stages, and the physical mechanisms underlying each stage were analyzed. Numerical technology computer-aided design (TCAD) simulations were conducted to analyze the electric field distribution and the variations in electron mobility during overcurrent stress. Both thermal runaway and drain/substrate breakdown failures were investigated through simulation analysis. The results indicate that thermal runaway failure in GaN HEMTs occurs due to the accumulation of thermal stresses in the access region, which is triggered by the reduction in electron mobility and an increase in the electric field within the channel. The drain and substrate breakdown failure are mainly caused by the high vertical electric field between the drain and substrate due to hole injection from the drain p-GaN region. Furthermore, the failure mechanisms were validated through experimental tests.
{"title":"Experimental and Simulation Study on the Failure Mechanism of GaN HD-GIT Under Overcurrent Stress","authors":"Xi Jiang;Jing Chen;Chaofan Pan;Hao Niu;Song Yuan;Xiangdong Li;Zhaoheng Yan;Xiaowu Gong;Daming Wang;Jun Wang","doi":"10.1109/TED.2025.3588834","DOIUrl":"https://doi.org/10.1109/TED.2025.3588834","url":null,"abstract":"This article investigates the failure mechanisms of the gallium nitride high electron mobility transistors (GaN HEMTs) under overcurrent stress. The overcurrent behavior of GaN hybrid drain-embedded gate injection transistor (HD-GIT) devices was evaluated under different stress conditions, and the primary failure modes were identified. The waveforms of the GaN devices during overcurrent events were analyzed in stages, and the physical mechanisms underlying each stage were analyzed. Numerical technology computer-aided design (TCAD) simulations were conducted to analyze the electric field distribution and the variations in electron mobility during overcurrent stress. Both thermal runaway and drain/substrate breakdown failures were investigated through simulation analysis. The results indicate that thermal runaway failure in GaN HEMTs occurs due to the accumulation of thermal stresses in the access region, which is triggered by the reduction in electron mobility and an increase in the electric field within the channel. The drain and substrate breakdown failure are mainly caused by the high vertical electric field between the drain and substrate due to hole injection from the drain p-GaN region. Furthermore, the failure mechanisms were validated through experimental tests.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4770-4779"},"PeriodicalIF":3.2,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/TED.2025.3591574
Zihao Dai;Jianxun Wang;Yixin Wan;Xinjie Li;Hao Li;Chenrui Wei;Wei Jiang;Yong Luo
To enhance the output power and beam–wave interaction efficiency of sheet beam (SB) traveling wave tubes (SB-TWTs) operating in the subterahertz frequency range, this study proposes a novel groove-loaded folded waveguide (GLFW) slow wave structure (SWS) with a vertical beam tunnel. GLFW-SWS overcomes size limitations associated with operating frequency, thereby allowing for a broader lateral dimension of the beam tunnel. It effectively expands the width of the beam tunnel while minimizing reflection. Compared with the traditional folded waveguide (FW) SWS, the average interaction impedance in the interaction region is increased by 50%. In the subterahertz frequency range (218–220.5 GHz), the utilization of GLFW-SWS leads to a great improvement in the output power level of the TWT. Combined with a phase velocity tapering optimization method, at cathode voltages and current of 25 kV and 0.4 A (focused current density of 341 A/cm2), respectively, output power exceeding 1.01 kW can be achieved at 219.6 GHz. The interaction efficiency is over 10.1%. The transmission and dispersion characteristics are experimentally verified. This development offers a promising solution for subterahertz sources in next-generation communication.
为了提高工作在亚太赫兹频率范围内的片状束行波管（SB- twts）的输出功率和波束相互作用效率，本研究提出了一种具有垂直波束隧道的新型槽载折叠波导（GLFW）慢波结构（SWS）。GLFW-SWS克服了与工作频率相关的尺寸限制，从而允许更宽的波束隧道横向尺寸。它有效地扩大了光束隧道的宽度，同时最大限度地减少了反射。与传统的折叠波导（FW） SWS相比，其相互作用区域的平均相互作用阻抗提高了50%。在次太赫兹频率范围内（218-220.5 GHz），利用GLFW-SWS可以大大提高行波管的输出功率水平。结合相速度渐变优化方法，在阴极电压为25 kV、电流为0.4 a（聚焦电流密度为341 a /cm2）时，219.6 GHz的输出功率可超过1.01 kW。相互作用效率大于10.1%。实验验证了其传输和色散特性。这一发展为下一代通信中的次太赫兹源提供了一个有前途的解决方案。
{"title":"A Groove-Loaded Folded Waveguide Slow Wave Structure With Vertical Beam Tunnel for Power Enhancement in Sheet Beam Sub-THz TWTs","authors":"Zihao Dai;Jianxun Wang;Yixin Wan;Xinjie Li;Hao Li;Chenrui Wei;Wei Jiang;Yong Luo","doi":"10.1109/TED.2025.3591574","DOIUrl":"https://doi.org/10.1109/TED.2025.3591574","url":null,"abstract":"To enhance the output power and beam–wave interaction efficiency of sheet beam (SB) traveling wave tubes (SB-TWTs) operating in the subterahertz frequency range, this study proposes a novel groove-loaded folded waveguide (GLFW) slow wave structure (SWS) with a vertical beam tunnel. GLFW-SWS overcomes size limitations associated with operating frequency, thereby allowing for a broader lateral dimension of the beam tunnel. It effectively expands the width of the beam tunnel while minimizing reflection. Compared with the traditional folded waveguide (FW) SWS, the average interaction impedance in the interaction region is increased by 50%. In the subterahertz frequency range (218–220.5 GHz), the utilization of GLFW-SWS leads to a great improvement in the output power level of the TWT. Combined with a phase velocity tapering optimization method, at cathode voltages and current of 25 kV and 0.4 A (focused current density of 341 A/cm2), respectively, output power exceeding 1.01 kW can be achieved at 219.6 GHz. The interaction efficiency is over 10.1%. The transmission and dispersion characteristics are experimentally verified. This development offers a promising solution for subterahertz sources in next-generation communication.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5201-5208"},"PeriodicalIF":3.2,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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