Pub Date : 2025-01-24DOI: 10.1109/TED.2025.3530056
{"title":"Exploration of the exciting world of multifunctional oxide-based electronic devices: from material to system-level applications","authors":"","doi":"10.1109/TED.2025.3530056","DOIUrl":"https://doi.org/10.1109/TED.2025.3530056","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 2","pages":"943-944"},"PeriodicalIF":2.9,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10852533","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143373126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-24DOI: 10.1109/TED.2025.3529405
Chao-Yang Ke;Ming-Dou Ker
A power-rail electrostatic discharge (ESD) clamp circuit for monolithic GaN-based integrated circuits (ICs) with ultralow leakage current and dynamic timing-voltage detection function was proposed, which has been successfully verified in a 0.5-$mu $ m GaN-on-Si process. The standby leakage current is only 0.8 nA. With the voltage detection, the proposed ESD clamp circuit can only be triggered by ESD events, and cannot be falsely triggered during fast power-on conditions. The experimental results demonstrate that the human-body-model (HBM) ESD robustness of the proposed design can be achieved over 6 kV. The triggered voltage of the ESD clamp circuit is flexible by adjusting the number of diode-connected high electron mobility transistors (HEMTs), so it can be utilized in different voltage ratings of ${V}_{textit {CC}}$ .
{"title":"Design of GaN-on-Silicon Power-Rail ESD Clamp Circuit With Ultralow Leakage Current and Dynamic Timing-Voltage Detection Function","authors":"Chao-Yang Ke;Ming-Dou Ker","doi":"10.1109/TED.2025.3529405","DOIUrl":"https://doi.org/10.1109/TED.2025.3529405","url":null,"abstract":"A power-rail electrostatic discharge (ESD) clamp circuit for monolithic GaN-based integrated circuits (ICs) with ultralow leakage current and dynamic timing-voltage detection function was proposed, which has been successfully verified in a 0.5-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> m GaN-on-Si process. The standby leakage current is only 0.8 nA. With the voltage detection, the proposed ESD clamp circuit can only be triggered by ESD events, and cannot be falsely triggered during fast power-on conditions. The experimental results demonstrate that the human-body-model (HBM) ESD robustness of the proposed design can be achieved over 6 kV. The triggered voltage of the ESD clamp circuit is flexible by adjusting the number of diode-connected high electron mobility transistors (HEMTs), so it can be utilized in different voltage ratings of <inline-formula> <tex-math>${V}_{textit {CC}}$ </tex-math></inline-formula>.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1066-1074"},"PeriodicalIF":2.9,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-24DOI: 10.1109/TED.2025.3525821
{"title":"IEEE Transactions on Electron Devices Information for Authors","authors":"","doi":"10.1109/TED.2025.3525821","DOIUrl":"https://doi.org/10.1109/TED.2025.3525821","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 2","pages":"C3-C3"},"PeriodicalIF":2.9,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10852535","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143373116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-24DOI: 10.1109/TED.2025.3529407
Sanket Mitra;Chandrima Mondal;Abhijit Biswas
In this work, we present a design, model, and analysis for a multilayered transition metal dichalcogenide (TMD)-based negative capacitance (NC) FET that achieves a subthreshold swing (SS) well below the thermodynamic limit, a maximum drain-induced barrier rise (DIBR) of 5 mV/V, and a threshold voltage (${V} _{text {th}}$ ) roll-up confined within 0.8% at a 10-nm channel length, using hafnium zirconium oxide (Hf0.5Zr0.5O2) as the ferroelectric material. Various parameters are considered, including ferroelectric layer thickness (${t} _{text {FE}}$ ), coercive electric field (${E} _{c}$ ), remanent polarization (${P} _{r}$ ), number of molybdenum disulfide (MoS2) layers (N), equivalent front and buried oxide thicknesses (EOT$_{mathbf {f}}$ , EOTb), channel length (L), and drain-source bias (${V} _{text {DS}}$ ). A surface-potential-based model, accounting for interfacial traps, is employed to compute performance parameters such as ${V}_{text {th}}$ , SS, and DIBR. The model is validated against simulation results and existing data. The capacitance matching is performed to ensure hysteresis-free and stable NC operation. Conditions for the ferroelectric parameters ($alpha $ ) and ${t}_{text {FE}}$ are derived to mitigate short-channel effects (SCEs). Optimization is carried out to achieve subthermodynamic SS while maintaining 5 mV/V DIBR and a ${V}_{text {th}}$ roll-up below 0.8%, with values recorded for various combinations of N, EOTf, EOTb, and ${V}_{text {DS}}$ . Unlike direct bandgap monolayer MoS2, multilayer MoS2, an indirect bandgap semiconductor, is preferred due to its lower interface-trapped charge density and augmented performance. The feasibility of the recorded $alpha ~{t}_{text {FE}}$ values is verified against experimental results, and an empirical model is proposed to guide the selection of ferroelectric materials for specific ${t}_{text {FE}}$ .
{"title":"Design of MoS2 NCFET Featuring Subthermodynamic Limit SS, No More Than 5 mV/V DIBR, and 0.8% Threshold Voltage Variation at 10-nm Channel Length: Modeling and Analysis","authors":"Sanket Mitra;Chandrima Mondal;Abhijit Biswas","doi":"10.1109/TED.2025.3529407","DOIUrl":"https://doi.org/10.1109/TED.2025.3529407","url":null,"abstract":"In this work, we present a design, model, and analysis for a multilayered transition metal dichalcogenide (TMD)-based negative capacitance (NC) FET that achieves a subthreshold swing (SS) well below the thermodynamic limit, a maximum drain-induced barrier rise (DIBR) of 5 mV/V, and a threshold voltage (<inline-formula> <tex-math>${V} _{text {th}}$ </tex-math></inline-formula>) roll-up confined within 0.8% at a 10-nm channel length, using hafnium zirconium oxide (Hf0.5Zr0.5O2) as the ferroelectric material. Various parameters are considered, including ferroelectric layer thickness (<inline-formula> <tex-math>${t} _{text {FE}}$ </tex-math></inline-formula>), coercive electric field (<inline-formula> <tex-math>${E} _{c}$ </tex-math></inline-formula>), remanent polarization (<inline-formula> <tex-math>${P} _{r}$ </tex-math></inline-formula>), number of molybdenum disulfide (MoS2) layers (N), equivalent front and buried oxide thicknesses (EOT<inline-formula> <tex-math>$_{mathbf {f}}$ </tex-math></inline-formula>, EOTb), channel length (L), and drain-source bias (<inline-formula> <tex-math>${V} _{text {DS}}$ </tex-math></inline-formula>). A surface-potential-based model, accounting for interfacial traps, is employed to compute performance parameters such as <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>, SS, and DIBR. The model is validated against simulation results and existing data. The capacitance matching is performed to ensure hysteresis-free and stable NC operation. Conditions for the ferroelectric parameters (<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>) and <inline-formula> <tex-math>${t}_{text {FE}}$ </tex-math></inline-formula> are derived to mitigate short-channel effects (SCEs). Optimization is carried out to achieve subthermodynamic SS while maintaining 5 mV/V DIBR and a <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> roll-up below 0.8%, with values recorded for various combinations of N, EOTf, EOTb, and <inline-formula> <tex-math>${V}_{text {DS}}$ </tex-math></inline-formula>. Unlike direct bandgap monolayer MoS2, multilayer MoS2, an indirect bandgap semiconductor, is preferred due to its lower interface-trapped charge density and augmented performance. The feasibility of the recorded <inline-formula> <tex-math>$alpha ~{t}_{text {FE}}$ </tex-math></inline-formula> values is verified against experimental results, and an empirical model is proposed to guide the selection of ferroelectric materials for specific <inline-formula> <tex-math>${t}_{text {FE}}$ </tex-math></inline-formula>.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1476-1482"},"PeriodicalIF":2.9,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143580923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-24DOI: 10.1109/TED.2025.3530000
{"title":"Wide Band Gap Semiconductors for Automotive Applications","authors":"","doi":"10.1109/TED.2025.3530000","DOIUrl":"https://doi.org/10.1109/TED.2025.3530000","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 2","pages":"946-947"},"PeriodicalIF":2.9,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10852531","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143373136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-24DOI: 10.1109/TED.2025.3529810
I. A. Savichev;I. G. Margolin;R. I. Romanov;A. A. Chouprik
The development of low-power and high-density ferroelectric memories requires scaling the thickness of the functional layer. However, the thickness could have a significant impact on the performance of memory devices. This work examines the effect of ferroelectric layer thickness on resistive switching and depolarization phenomena in a metal-Hf0.5Zr0.5O2-Si (MFS) structure, which is the functional structure of both ferroelectric field-effect transistors (FeFETs) and ferroelectric tunnel junctions (FTJs). The MFS structures show one stable and another unstable polarization state, with the instability caused by the strong electric field produced by charged donor surface states at the Si interface and poor screening of this polarization. The rate of the unstable state depolarization slows down with increasing thickness from 5 to 10 nm, which is due to the decrease in the depolarization field at the same potential difference in the structure. The resistive effect increases with increasing thickness up to ${R}_{text {OFF}}$ /${R}_{text {ON}}=24$ , which is related to the reduction of undesired conductivity along the grain boundaries of the polycrystalline Hf0.5Zr0.5O2 film. The temporal dynamics of the depolarization of the unstable polarization state and the resulting gradual switching off of the low-resistance state are close to the characteristic times of the weight change of biological synapses, and therefore, such ferroelectric memristors are suitable for emulating their behavior. The results may be useful for the development of building blocks for neuromorphic computing as well as a new generation of FeFET and FTJ-based memories.
{"title":"Role of Ferroelectric Layer Thickness in Resistive Switching and Depolarization Effects in Hf₀.₅Zr₀.₅O₂-Based Structures","authors":"I. A. Savichev;I. G. Margolin;R. I. Romanov;A. A. Chouprik","doi":"10.1109/TED.2025.3529810","DOIUrl":"https://doi.org/10.1109/TED.2025.3529810","url":null,"abstract":"The development of low-power and high-density ferroelectric memories requires scaling the thickness of the functional layer. However, the thickness could have a significant impact on the performance of memory devices. This work examines the effect of ferroelectric layer thickness on resistive switching and depolarization phenomena in a metal-Hf0.5Zr0.5O2-Si (MFS) structure, which is the functional structure of both ferroelectric field-effect transistors (FeFETs) and ferroelectric tunnel junctions (FTJs). The MFS structures show one stable and another unstable polarization state, with the instability caused by the strong electric field produced by charged donor surface states at the Si interface and poor screening of this polarization. The rate of the unstable state depolarization slows down with increasing thickness from 5 to 10 nm, which is due to the decrease in the depolarization field at the same potential difference in the structure. The resistive effect increases with increasing thickness up to <inline-formula> <tex-math>${R}_{text {OFF}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${R}_{text {ON}}=24$ </tex-math></inline-formula>, which is related to the reduction of undesired conductivity along the grain boundaries of the polycrystalline Hf0.5Zr0.5O2 film. The temporal dynamics of the depolarization of the unstable polarization state and the resulting gradual switching off of the low-resistance state are close to the characteristic times of the weight change of biological synapses, and therefore, such ferroelectric memristors are suitable for emulating their behavior. The results may be useful for the development of building blocks for neuromorphic computing as well as a new generation of FeFET and FTJ-based memories.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1104-1111"},"PeriodicalIF":2.9,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-24DOI: 10.1109/TED.2025.3525819
{"title":"IEEE ELECTRON DEVICES SOCIETY","authors":"","doi":"10.1109/TED.2025.3525819","DOIUrl":"https://doi.org/10.1109/TED.2025.3525819","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 2","pages":"C2-C2"},"PeriodicalIF":2.9,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10852534","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143184138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-24DOI: 10.1109/TED.2025.3530057
{"title":"Announcing an IEEE/Optica Publishing Group Journal of Lightwave Technology Special Issue on: OFS-29","authors":"","doi":"10.1109/TED.2025.3530057","DOIUrl":"https://doi.org/10.1109/TED.2025.3530057","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 2","pages":"945-945"},"PeriodicalIF":2.9,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10852530","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143373138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the demand for wearable integrated circuits in the field of flexible electronic, ambipolar organic field-effect transistors (OFETs) acting as both n-type and p-type performances are attracting more and more attention. In this article, a flexible inverter comprised of two identical ambipolar transistors was fabricated on the flexible muscovite substrate. The entire fabrication process for ambipolar transistors remains below 300°C, ensuring compatibility with backend-of-the-line (BEOL). The ambipolar transistor exhibits typical V-shape transfer curve with distinct branches for hole and electron transport, along with a comprehensive ambipolar region. The software ABAQUS was used to analyze the distribution of stress for the ambipolar transistor. Meanwhile, the ambipolar inverter comprised of the transistors can work for both positive and negative supply voltages (${V} _{text {DD}}$ ) depending on input voltage (${V} _{text {IN}}$ ). Furthermore, the inverter is highly flexible, which can work stably under different bending states. The proposed flexible inverter provides a possibility of application for flexible wearable integrated circuits.
{"title":"Flexible Inverter Based on Ambipolar OFETs Compatible With Finite Element Analysis","authors":"Xuemeng Hu;Jialin Meng;Hao Zhu;Tianyu Wang;Qingqing Sun;David Wei Zhang;Lin Chen","doi":"10.1109/TED.2025.3526561","DOIUrl":"https://doi.org/10.1109/TED.2025.3526561","url":null,"abstract":"With the demand for wearable integrated circuits in the field of flexible electronic, ambipolar organic field-effect transistors (OFETs) acting as both n-type and p-type performances are attracting more and more attention. In this article, a flexible inverter comprised of two identical ambipolar transistors was fabricated on the flexible muscovite substrate. The entire fabrication process for ambipolar transistors remains below 300°C, ensuring compatibility with backend-of-the-line (BEOL). The ambipolar transistor exhibits typical V-shape transfer curve with distinct branches for hole and electron transport, along with a comprehensive ambipolar region. The software ABAQUS was used to analyze the distribution of stress for the ambipolar transistor. Meanwhile, the ambipolar inverter comprised of the transistors can work for both positive and negative supply voltages (<inline-formula> <tex-math>${V} _{text {DD}}$ </tex-math></inline-formula>) depending on input voltage (<inline-formula> <tex-math>${V} _{text {IN}}$ </tex-math></inline-formula>). Furthermore, the inverter is highly flexible, which can work stably under different bending states. The proposed flexible inverter provides a possibility of application for flexible wearable integrated circuits.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1174-1179"},"PeriodicalIF":2.9,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
GaN-based Micro-LED technology has been intensively applied in high-resolution display and visible light communication (VLC) applications, benefiting from its enhancement of integration density. However, parasitic issues in the heterogeneous integration of GaN-based Micro-LED and its Si-based CMOS driver are one of the main factors limiting the switching speed in display applications and modulation bandwidth in VLC technology at present. This work reports a novel monolithically integrated device of GaN-based light-emitting diode (LED) and high-electron-mobility transistor (HEMT), which is essentially a light-emitting HEMT (LE-HEMT) based on a p-GaN HEMT epitaxy, with p-GaN being retained under the drain electrode and an InGaN quantum well layer inserted between the AlGaN barrier and the intrinsic GaN layer. The influence of gate-source voltage (${V} _{text {GS}}$ ) and applied drain voltage (${V} _{text {DD}}$ ) on the controllability of LE-HEMT is investigated. It exhibits output current up to 303 mA/mm at ${V} _{text {DD}} =10$ V and ${V} _{text {GS}} =2$ V. The luminance and light output power (LOP) reach 2680 cd/m2 and 0.16 W/cm2, respectively, being superior to that of LED-HEMT integrated devices based on HEMT-like epitaxial structures from the literature. Besides, it exhibits good switching performances with a turn-on delay of 288 ns and a turn-off delay of $7.2~mu $ s. This work offers a novel approach to the monolithic integration of light source and its driving transistor based on an HEMT-like epitaxial structure and simplified fabrication processes, providing a pathway for high-resolution display and high-speed VLC applications.
{"title":"Proposal and Realization of Light-Emitting HEMT With InGaN Quantum Well Inserted","authors":"Kailin Ren;Jijun Zhu;Haoyu Wang;Yangyang Hu;Kai Cheng;Peng Xiang;Luqiao Yin;Aiying Guo;Jianhua Zhang","doi":"10.1109/TED.2025.3529811","DOIUrl":"https://doi.org/10.1109/TED.2025.3529811","url":null,"abstract":"GaN-based Micro-LED technology has been intensively applied in high-resolution display and visible light communication (VLC) applications, benefiting from its enhancement of integration density. However, parasitic issues in the heterogeneous integration of GaN-based Micro-LED and its Si-based CMOS driver are one of the main factors limiting the switching speed in display applications and modulation bandwidth in VLC technology at present. This work reports a novel monolithically integrated device of GaN-based light-emitting diode (LED) and high-electron-mobility transistor (HEMT), which is essentially a light-emitting HEMT (LE-HEMT) based on a p-GaN HEMT epitaxy, with p-GaN being retained under the drain electrode and an InGaN quantum well layer inserted between the AlGaN barrier and the intrinsic GaN layer. The influence of gate-source voltage (<inline-formula> <tex-math>${V} _{text {GS}}$ </tex-math></inline-formula>) and applied drain voltage (<inline-formula> <tex-math>${V} _{text {DD}}$ </tex-math></inline-formula>) on the controllability of LE-HEMT is investigated. It exhibits output current up to 303 mA/mm at <inline-formula> <tex-math>${V} _{text {DD}} =10$ </tex-math></inline-formula> V and <inline-formula> <tex-math>${V} _{text {GS}} =2$ </tex-math></inline-formula> V. The luminance and light output power (LOP) reach 2680 cd/m2 and 0.16 W/cm2, respectively, being superior to that of LED-HEMT integrated devices based on HEMT-like epitaxial structures from the literature. Besides, it exhibits good switching performances with a turn-on delay of 288 ns and a turn-off delay of <inline-formula> <tex-math>$7.2~mu $ </tex-math></inline-formula>s. This work offers a novel approach to the monolithic integration of light source and its driving transistor based on an HEMT-like epitaxial structure and simplified fabrication processes, providing a pathway for high-resolution display and high-speed VLC applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1206-1210"},"PeriodicalIF":2.9,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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