Pub Date : 2024-08-15DOI: 10.1109/TED.2024.3438686
Zhen-Jin Wang;Xin-Liang Ye;Chun-Liang Lin;Wei-Chen Tu;Chih-Chiang Yang;Yan-Kuin Su
The micro light-emitting diodes ( $mu $ LEDs) offer advantages that make it an attractive option for various applications, such as displays, lighting, AR/VR, and consumer electronics. The light output power (LOP) and external quantum efficiency (EQE) of $mu $ LEDs are the crucial parameters that impact the performance and suitability of these devices. Ongoing studies are focused on addressing the issue of $mu $ LEDs. In this study, we propose several treatment strategies to modify the sidewall of $mu $ LEDs and improve the performance of devices. The results show that the $mu $ LEDs treated with citric acid (CA) and ammonium sulfide [(NH $_{{4}}text {)}_{{2}}$ Sx] for 1 h have the best improvement in LOP by 93.3%, and EQE increases by 91.3%. In addition, the reliability of $mu $ LEDs with different sidewall treatments was studied under long-term aging and high-temperature and high-humidity conditions. The treatment method for $mu $ LEDs has made significant contributions to the performance of devices, bringing about advancements in various key areas.
微型发光二极管（$mu $ LEDs）的优势使其成为显示器、照明、AR/VR 和消费类电子产品等各种应用中极具吸引力的选择。LED 的光输出功率（LOP）和外部量子效率（EQE）是影响这些设备性能和适用性的关键参数。目前的研究主要集中在解决 $mu $ LED 的问题上。在这项研究中，我们提出了几种处理策略，以改变 $mu $ LED 的侧壁，提高器件的性能。结果表明，用柠檬酸（CA）和硫化铵[(NH $_{{4}}text {)}_{{2}}$ Sx]处理 1 h 的 $mu $ LED 的 LOP 提高了 93.3%，EQE 提高了 91.3%。此外，还研究了不同侧壁处理的 $mu $ LED 在长期老化和高温高湿条件下的可靠性。发光二极管的处理方法对器件的性能做出了重大贡献，在多个关键领域取得了进展。
{"title":"Increasing Efficiency and Extending Lifetime of Red Micro Light-Emitting Diodes Through Sidewall Treatment for Improved Reliability","authors":"Zhen-Jin Wang;Xin-Liang Ye;Chun-Liang Lin;Wei-Chen Tu;Chih-Chiang Yang;Yan-Kuin Su","doi":"10.1109/TED.2024.3438686","DOIUrl":"https://doi.org/10.1109/TED.2024.3438686","url":null,"abstract":"The micro light-emitting diodes (\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000LEDs) offer advantages that make it an attractive option for various applications, such as displays, lighting, AR/VR, and consumer electronics. The light output power (LOP) and external quantum efficiency (EQE) of \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000LEDs are the crucial parameters that impact the performance and suitability of these devices. Ongoing studies are focused on addressing the issue of \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000LEDs. In this study, we propose several treatment strategies to modify the sidewall of \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000LEDs and improve the performance of devices. The results show that the \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000LEDs treated with citric acid (CA) and ammonium sulfide [(NH\u0000<inline-formula> <tex-math>$_{{4}}text {)}_{{2}}$ </tex-math></inline-formula>\u0000Sx] for 1 h have the best improvement in LOP by 93.3%, and EQE increases by 91.3%. In addition, the reliability of \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000LEDs with different sidewall treatments was studied under long-term aging and high-temperature and high-humidity conditions. The treatment method for \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000LEDs has made significant contributions to the performance of devices, bringing about advancements in various key areas.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142084503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The alternating current (ac)-driven GaN-based single contact light-emitting diode (SC-LED) has garnered significant attention due to its unique driving technique and potential applications, especially in areas where direct current-driven (dc-driven) LEDs face limitations. Our previous research emphasizes the importance of reducing the operating voltage of SC-LED. In this study, we have developed and manufactured a novel SC-LED featuring a tunnel junction (TJ) structure, which exhibits a lower breakdown voltage ( ${V} _{text {breakdown}}$ ) compared to conventional LEDs with an ITO contact layer. The simulation and experimental data illustrate a significant performance gap between TJ SC-LED and ITO SC-LED. The working voltage of TJ SC-LED is 34 V, which is 29% lower than that of ITO SC-LED. Specifically, under ac power at 80 V, TJ SC-LED exhibits a current of 0.94 mA and a WPE of 3.22%, both higher than the 0.77 mA and 3.02% values recorded for the ITO SC-LED. This comparison underscores the superior performance of TJ SC-LED over ITO SC-LED. These findings enhance our understanding of SC-LEDs and pave the way for the advancement of new driving techniques in nano-sized displays.
交流电（ac）驱动的氮化镓基单触点发光二极管（SC-LED）因其独特的驱动技术和潜在应用而备受关注，尤其是在直流电驱动（dc-driven）发光二极管面临限制的领域。我们之前的研究强调了降低 SC-LED 工作电压的重要性。在本研究中，我们开发并制造了一种具有隧道结（TJ）结构的新型 SC-LED，与带有 ITO 接触层的传统 LED 相比，它具有更低的击穿电压（${V} _{text {breakdown}}$ ）。仿真和实验数据表明，TJ SC-LED 与 ITO SC-LED 之间存在明显的性能差距。TJ SC-LED 的工作电压为 34 V，比 ITO SC-LED 低 29%。具体来说，在 80 V 交流电源下，TJ SC-LED 的电流为 0.94 mA，WPE 为 3.22%，均高于 ITO SC-LED 的 0.77 mA 和 3.02%。这一对比强调了 TJ SC-LED 优于 ITO SC-LED 的性能。这些发现加深了我们对 SC-LED 的理解，并为纳米尺寸显示器中新驱动技术的发展铺平了道路。
{"title":"Enhanced Performance of GaN-Based Single Contact Micro-LED Driven by AC Power Utilizing the Tunnel Junction","authors":"Dongqi Zhang;Tao Tao;Ting Zhi;Zhe Zhuang;Feifan Xu;Yimeng Sang;Junchi Yu;Yu Yan;Kangkai Tian;Zi-Hui Zhang;Jiachen Zhang;Bin Liu","doi":"10.1109/TED.2024.3435629","DOIUrl":"https://doi.org/10.1109/TED.2024.3435629","url":null,"abstract":"The alternating current (ac)-driven GaN-based single contact light-emitting diode (SC-LED) has garnered significant attention due to its unique driving technique and potential applications, especially in areas where direct current-driven (dc-driven) LEDs face limitations. Our previous research emphasizes the importance of reducing the operating voltage of SC-LED. In this study, we have developed and manufactured a novel SC-LED featuring a tunnel junction (TJ) structure, which exhibits a lower breakdown voltage (\u0000<inline-formula> <tex-math>${V} _{text {breakdown}}$ </tex-math></inline-formula>\u0000) compared to conventional LEDs with an ITO contact layer. The simulation and experimental data illustrate a significant performance gap between TJ SC-LED and ITO SC-LED. The working voltage of TJ SC-LED is 34 V, which is 29% lower than that of ITO SC-LED. Specifically, under ac power at 80 V, TJ SC-LED exhibits a current of 0.94 mA and a WPE of 3.22%, both higher than the 0.77 mA and 3.02% values recorded for the ITO SC-LED. This comparison underscores the superior performance of TJ SC-LED over ITO SC-LED. These findings enhance our understanding of SC-LEDs and pave the way for the advancement of new driving techniques in nano-sized displays.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142050477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This research presents a new method for manufacturing field emission devices (FEDs) using a standard 0.35- $mu $ m CMOS MEMS fabrication process, allowing the devices to function in normal air conditions. To enable nanoscale electrode gaps and atmospheric pressure operation, the FED’s layout is strategically modified to function as a diode, deliberately bypassing certain design rules for low-voltage capability. The SEM images suggest that the actual gap distance separating the electrodes is typically smaller than the initially intended dimensions. Measurements reveal an inverse relationship between the diode-like FEDs’ threshold voltages and the designed electrode spacing. These diode-like FEDs exhibit gentle rectification behavior, especially those with lower threshold voltages. This approach drastically simplifies FED fabrication, demonstrating the feasibility of integrating FEDs with CMOS technology. While the current 0.35- $mu $ m CMOS MEMS process employs aluminum metal stacks, this material choice may compromise reliability, especially when exposed to high-frequency alternating voltages.
{"title":"Diode-Like Field Emission Devices Fabricated by Standard 0.35-μm CMOS MEMS Process","authors":"Wen-Teng Chang;An-De Xu;Shao-Ping Huang;Sin-Rong Liu;Ting-Yi Wu","doi":"10.1109/TED.2024.3436032","DOIUrl":"https://doi.org/10.1109/TED.2024.3436032","url":null,"abstract":"This research presents a new method for manufacturing field emission devices (FEDs) using a standard 0.35-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS MEMS fabrication process, allowing the devices to function in normal air conditions. To enable nanoscale electrode gaps and atmospheric pressure operation, the FED’s layout is strategically modified to function as a diode, deliberately bypassing certain design rules for low-voltage capability. The SEM images suggest that the actual gap distance separating the electrodes is typically smaller than the initially intended dimensions. Measurements reveal an inverse relationship between the diode-like FEDs’ threshold voltages and the designed electrode spacing. These diode-like FEDs exhibit gentle rectification behavior, especially those with lower threshold voltages. This approach drastically simplifies FED fabrication, demonstrating the feasibility of integrating FEDs with CMOS technology. While the current 0.35-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS MEMS process employs aluminum metal stacks, this material choice may compromise reliability, especially when exposed to high-frequency alternating voltages.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142045106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
HfOx-based ferroelectric random access memories (FeRAMs) have been proposed as a promising candidate to further dynamic random access memory (DRAM) scaling. This article presents a bitcell design space exploration of HfZrOx-based FeRAM based on a 2T1C testbench representative of a 64-kb 1T1C subarray at 40-nm CMOS technology. We first explore the impact of ferroelectric capacitor (FeCAP) sizing on the read sensing margin (SM) and speed with eight different blocks in the subarray, supported by a hardware-calibrated FeCAP compact model. We identify the capacitance ratio ( ${C} _{text {R}}$ ) between the bitline parasitic capacitance ( ${C} _{text {BL}}$ ) and the FeCAP capacitance ( ${C} _{text {FE}}$ ) as the critical design parameter for bitcell SM optimization, with a maximum ${C} _{text {R}}$ of 41 permitted for the given FeCAP technology. Furthermore, we investigate the impact of FeCAP sizing on ferro-grain granularity (FGG)-induced variability. Our findings clarify that SM variability worsens with increasing FeCAP size but does not significantly affect the readability overall. Additionally, we examine the consequences of FeCAP sizing on disturbance effects during write operations, concluding that larger FeCAPs help mitigate write disturbances by reducing voltage transfer to half-selected (HS) cells.
{"title":"Design Space Exploration of FeRAM Bit Cell for DRAM Application","authors":"Hyungrock Oh;Yang Xiang;Fernando Garcia Redondo;Mohit Kumar Gupta;Manu Perumkunnil;Marie Garcia Bardon;Amit Dhiman;Sathisha Nanjunde Gowda;Amey Walke;Andrea Fantini;Farrukh Yasin;Gouri Sankar Kar;Geert Hellings;Wim Dehaene","doi":"10.1109/TED.2024.3435630","DOIUrl":"https://doi.org/10.1109/TED.2024.3435630","url":null,"abstract":"HfOx-based ferroelectric random access memories (FeRAMs) have been proposed as a promising candidate to further dynamic random access memory (DRAM) scaling. This article presents a bitcell design space exploration of HfZrOx-based FeRAM based on a 2T1C testbench representative of a 64-kb 1T1C subarray at 40-nm CMOS technology. We first explore the impact of ferroelectric capacitor (FeCAP) sizing on the read sensing margin (SM) and speed with eight different blocks in the subarray, supported by a hardware-calibrated FeCAP compact model. We identify the capacitance ratio (\u0000<inline-formula> <tex-math>${C} _{text {R}}$ </tex-math></inline-formula>\u0000) between the bitline parasitic capacitance (\u0000<inline-formula> <tex-math>${C} _{text {BL}}$ </tex-math></inline-formula>\u0000) and the FeCAP capacitance (\u0000<inline-formula> <tex-math>${C} _{text {FE}}$ </tex-math></inline-formula>\u0000) as the critical design parameter for bitcell SM optimization, with a maximum \u0000<inline-formula> <tex-math>${C} _{text {R}}$ </tex-math></inline-formula>\u0000 of 41 permitted for the given FeCAP technology. Furthermore, we investigate the impact of FeCAP sizing on ferro-grain granularity (FGG)-induced variability. Our findings clarify that SM variability worsens with increasing FeCAP size but does not significantly affect the readability overall. Additionally, we examine the consequences of FeCAP sizing on disturbance effects during write operations, concluding that larger FeCAPs help mitigate write disturbances by reducing voltage transfer to half-selected (HS) cells.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142084490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-12DOI: 10.1109/TED.2024.3433833
Cheng-Kuei Lee;Hsun-Lin Chang;Kun-Mung Chen;Guo-Wei Huang;Chien-Nan Kuo;Pei-Wen Li;Horng-Chih Lin
We report the implementation of both n- and p-channel polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with features of T-shaped gate (T-gate) of n+ poly-Si in combination with lightly doped drain (LDD) structure. The inclusion of the T-gate and LDD structures improves both the on-state current ( ${I}_{text {on}}$ ) and off-state leakage ( ${I}_{text {off}}$ ) of n-channel TFTs significantly in comparison to the conventional TFTs. For p-channel poly-Si TFTs, the LDD structure mitigates ${I}_{text {off}}$ but leads to an ${I}_{text {on}}$ degradation due to a potential barrier at the source junction underneath the T-gate’s wing. An additional boron channel doping not only improves ${I}_{text {on}}$ but also adjusts the threshold voltage of p-channel TFTs. Based on our proposed poly-Si TFTs, the fabricated T-gate devices demonstrate full-swing switching of CMOS inverters.
我们报告了 n+ 多晶硅 T 型栅极（T-gate）与轻掺杂漏极（LDD）结构相结合的 n 沟道和 p 沟道多晶硅薄膜晶体管（TFT）的实现情况。与传统 TFT 相比，加入 T 形栅极和 LDD 结构后，n 沟道 TFT 的导通电流（${I}_{text{on}}$）和关断漏电流（${I}_{text{off}}$）都得到了显著改善。对于 p 沟道多晶硅 TFT 而言，LDD 结构可以减少 ${I}_{text {off}}$，但由于 T 栅极翼下的源结处存在势垒，会导致 ${I}_{text {on}}$下降。额外的硼沟道掺杂不仅能提高{I}_{text {on}$，还能调整 p 沟道 TFT 的阈值电压。基于我们提出的多晶硅 TFT，制造出的 T 栅极器件实现了 CMOS 逆变器的全摆动开关。
{"title":"Polycrystalline-Silicon CMOS Thin-Film Transistors With T-Shaped Gate and Lightly Doped Drain","authors":"Cheng-Kuei Lee;Hsun-Lin Chang;Kun-Mung Chen;Guo-Wei Huang;Chien-Nan Kuo;Pei-Wen Li;Horng-Chih Lin","doi":"10.1109/TED.2024.3433833","DOIUrl":"https://doi.org/10.1109/TED.2024.3433833","url":null,"abstract":"We report the implementation of both n- and p-channel polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with features of T-shaped gate (T-gate) of n+ poly-Si in combination with lightly doped drain (LDD) structure. The inclusion of the T-gate and LDD structures improves both the on-state current (\u0000<inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>\u0000) and off-state leakage (\u0000<inline-formula> <tex-math>${I}_{text {off}}$ </tex-math></inline-formula>\u0000) of n-channel TFTs significantly in comparison to the conventional TFTs. For p-channel poly-Si TFTs, the LDD structure mitigates \u0000<inline-formula> <tex-math>${I}_{text {off}}$ </tex-math></inline-formula>\u0000 but leads to an \u0000<inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>\u0000 degradation due to a potential barrier at the source junction underneath the T-gate’s wing. An additional boron channel doping not only improves \u0000<inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>\u0000 but also adjusts the threshold voltage of p-channel TFTs. Based on our proposed poly-Si TFTs, the fabricated T-gate devices demonstrate full-swing switching of CMOS inverters.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142084507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-09DOI: 10.1109/TED.2024.3430244
Sumit Choudhary;Daniel Schwarz;Hannes S. Funk;Satinder K. Sharma;Jörg Schulze
For junctionless FETs (JLFETs), an optimal ohmic contact is needed to achieve maximum drive current. The scaling of the source/drain (S/D) contact area impacts the contact resistivity ( $rho _{c}$ ) of FETs, which limits their on current and switching speed. Minimizing the S/D series resistance along with ohmic contacts is the critical factor in JLFET design due to moderate doping levels at S/D. The Ni and Ge contacts optimized at a low temperature of $350~^{circ }$ C by forming gas annealing (FGA) process and the computed contact resistance ( ${R}_{c}$ ), sheet resistance ( ${R}_{text {sh}}$ ), and contact resistivity ( $rho _{c}$ ) for Ni/p-GeSn contacts are $2.04times 10^{-{3}}~Omega cdot text {cm}$ , $63.96~Omega $ /□, and $6.18times 10^{-{8}}~Omega cdot text {cm}^{{2}}$ , respectively. The impact of capping metal resistance ( ${R}_{m}$ ) is analytically examined for Ni/p-GeSn contacts using the modified circular transmission line model (cTLM). Furthermore, to study the metal cap resistance ( ${R}_{m}$ ) effect pragmatically, the optimized GeSn channel FinFET with width/length (W/L) 20/90 nm is analyzed by incorporating an extra metal cap at contacts and its electrical characteristics were compared with the control sample. The result demonstrate that the effect of metal resistance is very significant in low sheet resistance ( ${R}_{text {sh}}$ ) materials, where ${R}_{text {sh}}$ is close to ${R}_{m}$ .
{"title":"Low-Temperature Processed Ni/GeSn Optimal Contacts for Junctionless GeSn-on-Si FinFETs","authors":"Sumit Choudhary;Daniel Schwarz;Hannes S. Funk;Satinder K. Sharma;Jörg Schulze","doi":"10.1109/TED.2024.3430244","DOIUrl":"10.1109/TED.2024.3430244","url":null,"abstract":"For junctionless FETs (JLFETs), an optimal ohmic contact is needed to achieve maximum drive current. The scaling of the source/drain (S/D) contact area impacts the contact resistivity (\u0000<inline-formula> <tex-math>$rho _{c}$ </tex-math></inline-formula>\u0000) of FETs, which limits their\u0000<sc>on</small>\u0000 current and switching speed. Minimizing the S/D series resistance along with ohmic contacts is the critical factor in JLFET design due to moderate doping levels at S/D. The Ni and Ge contacts optimized at a low temperature of \u0000<inline-formula> <tex-math>$350~^{circ }$ </tex-math></inline-formula>\u0000C by forming gas annealing (FGA) process and the computed contact resistance (\u0000<inline-formula> <tex-math>${R}_{c}$ </tex-math></inline-formula>\u0000), sheet resistance (\u0000<inline-formula> <tex-math>${R}_{text {sh}}$ </tex-math></inline-formula>\u0000), and contact resistivity (\u0000<inline-formula> <tex-math>$rho _{c}$ </tex-math></inline-formula>\u0000) for Ni/p-GeSn contacts are \u0000<inline-formula> <tex-math>$2.04times 10^{-{3}}~Omega cdot text {cm}$ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$63.96~Omega $ </tex-math></inline-formula>\u0000/□, and \u0000<inline-formula> <tex-math>$6.18times 10^{-{8}}~Omega cdot text {cm}^{{2}}$ </tex-math></inline-formula>\u0000, respectively. The impact of capping metal resistance (\u0000<inline-formula> <tex-math>${R}_{m}$ </tex-math></inline-formula>\u0000) is analytically examined for Ni/p-GeSn contacts using the modified circular transmission line model (cTLM). Furthermore, to study the metal cap resistance (\u0000<inline-formula> <tex-math>${R}_{m}$ </tex-math></inline-formula>\u0000) effect pragmatically, the optimized GeSn channel FinFET with width/length (W/L) 20/90 nm is analyzed by incorporating an extra metal cap at contacts and its electrical characteristics were compared with the control sample. The result demonstrate that the effect of metal resistance is very significant in low sheet resistance (\u0000<inline-formula> <tex-math>${R}_{text {sh}}$ </tex-math></inline-formula>\u0000) materials, where \u0000<inline-formula> <tex-math>${R}_{text {sh}}$ </tex-math></inline-formula>\u0000 is close to \u0000<inline-formula> <tex-math>${R}_{m}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-09DOI: 10.1109/ted.2024.3438114
Sergio García-Sánchez, Ignacio Íñiguez-de-la-Torre, Susana Pérez, Tomás González, Javier Mateos
{"title":"Monte Carlo Study of Gunn Oscillations in Geometrically Shaped Planar Gunn Diodes Based on Doped GaN: Influence of Geometry, Intervalley Energy, and Temperature","authors":"Sergio García-Sánchez, Ignacio Íñiguez-de-la-Torre, Susana Pérez, Tomás González, Javier Mateos","doi":"10.1109/ted.2024.3438114","DOIUrl":"https://doi.org/10.1109/ted.2024.3438114","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":3.1,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-09DOI: 10.1109/TED.2024.3435175
Izhar;Merrilyn M. A. Fiagbenu;Xingyu Du;Pariasadat Musavigharavi;Yang Deng;Akhil Gunda;Jeff Leathersich;Craig Moe;Abhay Kochhar;Eric A. Stach;Ramakrishna Vetury;Roy H. Olsson
This article presents 19-GHz bulk acoustic wave (BAW) resonators realized in a periodically poled piezoelectric film (P3F) microfabricated in a commercial XBAW process. The polarization of the three layers comprising the P3F film are realized via a combination of as-grown (two-layer) and electrically poled (one-layer) aluminum scandium nitride (AlScN). To improve the series ( ${Q}_{s}$ ) and maximum ( ${Q}_{max }$ ) quality factors, the device is constructed by connecting two-BAW resonators in series, which lowers the effect of the via resistance when compared with a traditional single BAW. Resonators achieved ${Q}_{max }$ of 531 (with ${Q}_{s}$ of 348 and ${Q}_{p}$ of 264) and ${text {FoM}}_{{os}}$ (defined as ${text {FoM}}_{{os}} = {{f}_{{s},{p}} {Q}}_{{s},{p}} times {{10}}^{-{9}}$ , where ${Q}_{{s},{p}}$ is the quality factor at series ( ${f}_{s}$ ) or parallel ( ${f}_{p}$ ) resonance frequency) of 6542 at 18.8-GHz frequency, which is higher than most of the state-of-the-art piezoelectric BAW resonators operating at similar and higher frequencies. The experimental results indicate that the P3F BAW resonators are promising for applications in emerging RF communication systems.
{"title":"A High Quality Factor, 19-GHz Periodically Poled AlScN BAW Resonator Fabricated in a Commercial XBAW Process","authors":"Izhar;Merrilyn M. A. Fiagbenu;Xingyu Du;Pariasadat Musavigharavi;Yang Deng;Akhil Gunda;Jeff Leathersich;Craig Moe;Abhay Kochhar;Eric A. Stach;Ramakrishna Vetury;Roy H. Olsson","doi":"10.1109/TED.2024.3435175","DOIUrl":"https://doi.org/10.1109/TED.2024.3435175","url":null,"abstract":"This article presents 19-GHz bulk acoustic wave (BAW) resonators realized in a periodically poled piezoelectric film (P3F) microfabricated in a commercial XBAW process. The polarization of the three layers comprising the P3F film are realized via a combination of as-grown (two-layer) and electrically poled (one-layer) aluminum scandium nitride (AlScN). To improve the series (\u0000<inline-formula> <tex-math>${Q}_{s}$ </tex-math></inline-formula>\u0000) and maximum (\u0000<inline-formula> <tex-math>${Q}_{max }$ </tex-math></inline-formula>\u0000) quality factors, the device is constructed by connecting two-BAW resonators in series, which lowers the effect of the via resistance when compared with a traditional single BAW. Resonators achieved \u0000<inline-formula> <tex-math>${Q}_{max }$ </tex-math></inline-formula>\u0000 of 531 (with \u0000<inline-formula> <tex-math>${Q}_{s}$ </tex-math></inline-formula>\u0000 of 348 and \u0000<inline-formula> <tex-math>${Q}_{p}$ </tex-math></inline-formula>\u0000 of 264) and \u0000<inline-formula> <tex-math>${text {FoM}}_{{os}}$ </tex-math></inline-formula>\u0000 (defined as \u0000<inline-formula> <tex-math>${text {FoM}}_{{os}} = {{f}_{{s},{p}} {Q}}_{{s},{p}} times {{10}}^{-{9}}$ </tex-math></inline-formula>\u0000, where \u0000<inline-formula> <tex-math>${Q}_{{s},{p}}$ </tex-math></inline-formula>\u0000 is the quality factor at series (\u0000<inline-formula> <tex-math>${f}_{s}$ </tex-math></inline-formula>\u0000) or parallel (\u0000<inline-formula> <tex-math>${f}_{p}$ </tex-math></inline-formula>\u0000) resonance frequency) of 6542 at 18.8-GHz frequency, which is higher than most of the state-of-the-art piezoelectric BAW resonators operating at similar and higher frequencies. The experimental results indicate that the P3F BAW resonators are promising for applications in emerging RF communication systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142050458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article deals with the stochastic resonance (SR) phenomenon experimentally observed in HfO2-based memristors. The SR impact on the binary spike time-dependent plasticity (STDP) protocol at the device level was investigated. We demonstrate that the two extreme conductance states of the device that represent the synaptic weights in neuromorphic systems can be better distinguished with the incorporation of Gaussian noise into the bias signal. This technique allows setting the memristor conductance which is directly related to the overlap between the pre- and postsynaptic pulses. The study is reproduced in the LTSPICE simulator using the dynamic memdiode model (DMM) for memristors.
{"title":"Stochastic Resonance in HfO₂-Based Memristors: Impact of External Noise on the Binary STDP Protocol","authors":"E. Salvador;R. Rodriguez;E. Miranda;J. Martin-Martinez;A. Rubio;V. Ntinas;G. Ch. Sirakoulis;A. Crespo-Yepes;M. Nafria","doi":"10.1109/TED.2024.3435173","DOIUrl":"10.1109/TED.2024.3435173","url":null,"abstract":"This article deals with the stochastic resonance (SR) phenomenon experimentally observed in HfO2-based memristors. The SR impact on the binary spike time-dependent plasticity (STDP) protocol at the device level was investigated. We demonstrate that the two extreme conductance states of the device that represent the synaptic weights in neuromorphic systems can be better distinguished with the incorporation of Gaussian noise into the bias signal. This technique allows setting the memristor conductance which is directly related to the overlap between the pre- and postsynaptic pulses. The study is reproduced in the LTSPICE simulator using the dynamic memdiode model (DMM) for memristors.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10632173","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-08DOI: 10.1109/TED.2024.3433310
Ya-Xun Lin;Der-Sheng Chao;Jenq-Horng Liang;Yao-Luen Shen;Chih-Fang Huang;Steve Hall;Ivona Z. Mitrovic
On-state stress induced device degradation of gallium nitride quasivertical Schottky barrier diode (SBD) with SiO2 passivation layer was investigated in this article. The devices were stressed at room temperature by biasing them separately at three distinct voltages for 500 s. The longer-term degradation was seen to be dominated predominantly by electron trapping in the oxide passivation layer. Less-severe degradation was observed in passivated devices in comparison with control devices without SiO2 passivation. The control devices were found to exhibit degradation due to the influence of bulk traps near to the metal/GaN interface. Moreover, the anode was held at zero voltage for 500 s to analyse the electron de-trapping mechanism during the recovery phase of SBDs. Current-voltage characteristics of the SBDs were measured to monitor the evolution of forward voltage and barrier height through periodic interruption under stress and recovery. A power-law model and universal recovery function were utilized to evaluate the parameter shifts with respect to time for each phase, respectively. The results demonstrate that border and bulk oxide traps associated with the passivation layer lead to the trapping and de-trapping of electrons. Furthermore, long-time constant bulk oxide traps are thought to be the contributing factor in the partial recovery, indicating that few electrons emit from these traps in the short-term recovery phase.
{"title":"Reliability of Quasi-vertical GaN on Silicon Schottky Barrier Diodes With SiO₂ Passivation Layer Under On-State Stress Bias","authors":"Ya-Xun Lin;Der-Sheng Chao;Jenq-Horng Liang;Yao-Luen Shen;Chih-Fang Huang;Steve Hall;Ivona Z. Mitrovic","doi":"10.1109/TED.2024.3433310","DOIUrl":"10.1109/TED.2024.3433310","url":null,"abstract":"On-state stress induced device degradation of gallium nitride quasivertical Schottky barrier diode (SBD) with SiO2 passivation layer was investigated in this article. The devices were stressed at room temperature by biasing them separately at three distinct voltages for 500 s. The longer-term degradation was seen to be dominated predominantly by electron trapping in the oxide passivation layer. Less-severe degradation was observed in passivated devices in comparison with control devices without SiO2 passivation. The control devices were found to exhibit degradation due to the influence of bulk traps near to the metal/GaN interface. Moreover, the anode was held at zero voltage for 500 s to analyse the electron de-trapping mechanism during the recovery phase of SBDs. Current-voltage characteristics of the SBDs were measured to monitor the evolution of forward voltage and barrier height through periodic interruption under stress and recovery. A power-law model and universal recovery function were utilized to evaluate the parameter shifts with respect to time for each phase, respectively. The results demonstrate that border and bulk oxide traps associated with the passivation layer lead to the trapping and de-trapping of electrons. Furthermore, long-time constant bulk oxide traps are thought to be the contributing factor in the partial recovery, indicating that few electrons emit from these traps in the short-term recovery phase.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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