Pub Date : 2025-07-30DOI: 10.1109/TED.2025.3592909
Chan Hee Suk;Jae Hyeon Park;Hyung Soon Kim;Keon-Ho Yoo;Tae Whan Kim
Recent indirect time-of-flight (iToF) sensors utilize backside structure technology (BST) to improve quantum efficiency by increasing the absorption of infrared light. However, this technology causes electrons to be generated far from the pixel center, leading to degraded demodulation contrast (DC) due to inefficient charge transfer. This study presents the first in-depth analysis of how the spatial distribution of electron generation affects DC in iToF sensors using TCAD simulations, analyzing both electron transfer ratios and optical generation profiles. We introduce the concept of transfer contrast (TrC), defined as the electron transfer ratio to the memory nodes (MNs), and examine it in conjunction with the probability of optical generation to quantify localized charge transfer inefficiencies. To address the performance degradation, we propose an extended photodiode scheme with vertical and lateral expansion. This design accelerates electrons generated even at the edges of the pixel by introducing additional electric fields across the pixel region, ensuring efficient charge transport to the MN within the pulse time. The proposed scheme enhances DC by 12% and reduces parasitic light sensitivity (PLS) by 18%, with minimal fabrication complexity. This approach is compatible with various pixel sizes and offers improved depth accuracy for infrared imaging applications.
{"title":"Extended Photodiode Scheme for Enhancement of Demodulation Contrast in Indirect Time-of-Flight Sensors","authors":"Chan Hee Suk;Jae Hyeon Park;Hyung Soon Kim;Keon-Ho Yoo;Tae Whan Kim","doi":"10.1109/TED.2025.3592909","DOIUrl":"https://doi.org/10.1109/TED.2025.3592909","url":null,"abstract":"Recent indirect time-of-flight (iToF) sensors utilize backside structure technology (BST) to improve quantum efficiency by increasing the absorption of infrared light. However, this technology causes electrons to be generated far from the pixel center, leading to degraded demodulation contrast (DC) due to inefficient charge transfer. This study presents the first in-depth analysis of how the spatial distribution of electron generation affects DC in iToF sensors using TCAD simulations, analyzing both electron transfer ratios and optical generation profiles. We introduce the concept of transfer contrast (TrC), defined as the electron transfer ratio to the memory nodes (MNs), and examine it in conjunction with the probability of optical generation to quantify localized charge transfer inefficiencies. To address the performance degradation, we propose an extended photodiode scheme with vertical and lateral expansion. This design accelerates electrons generated even at the edges of the pixel by introducing additional electric fields across the pixel region, ensuring efficient charge transport to the MN within the pulse time. The proposed scheme enhances DC by 12% and reduces parasitic light sensitivity (PLS) by 18%, with minimal fabrication complexity. This approach is compatible with various pixel sizes and offers improved depth accuracy for infrared imaging applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5067-5072"},"PeriodicalIF":3.2,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TED.2025.3590686
Jiangwei Cui;Qiwen Zheng;Yaqing Chi;Bin Liang;Xiaolong Li;Yang Guo;Qi Guo;Yudong Li
In this article, the interaction of total ionizing dose (TID) effect and hot carrier injection (HCI) degradation in bulk I/O-FIN field-effect transistors (FinFETs) is investigated. The results for stress post radiation (SPR) show that the HCI degradation of irradiated devices is greater than that of unirradiated, and the irradiated devices undergo rapid recovery by HCI stress for a very short time. With the increase of stress time, the influence of TID on HCI decreases and the off-state leakage current after irradiation does not recover to the initial value of the device. The electrons injection into the shallow trench isolation (STI) during HCI is suggested as the reason for parameters recovery after irradiation. While the experiment results of radiation post stress (RPS) show that there is no obvious influence of HCI on TID, since there is no electrons injection into STI region during HCI before TID. The irradiation experiment under HCI bias shows that the combination of these two effects causes the change of device characteristics. The mechanism of interaction between TID and HCI is revealed.
{"title":"Interaction of Total Ionizing Dose Effect and Hot Carrier Degradation in Bulk I/O-FinFETs","authors":"Jiangwei Cui;Qiwen Zheng;Yaqing Chi;Bin Liang;Xiaolong Li;Yang Guo;Qi Guo;Yudong Li","doi":"10.1109/TED.2025.3590686","DOIUrl":"https://doi.org/10.1109/TED.2025.3590686","url":null,"abstract":"In this article, the interaction of total ionizing dose (TID) effect and hot carrier injection (HCI) degradation in bulk I/O-<sc>FIN</small> field-effect transistors (FinFETs) is investigated. The results for stress post radiation (SPR) show that the HCI degradation of irradiated devices is greater than that of unirradiated, and the irradiated devices undergo rapid recovery by HCI stress for a very short time. With the increase of stress time, the influence of TID on HCI decreases and the <sc>off</small>-state leakage current after irradiation does not recover to the initial value of the device. The electrons injection into the shallow trench isolation (STI) during HCI is suggested as the reason for parameters recovery after irradiation. While the experiment results of radiation post stress (RPS) show that there is no obvious influence of HCI on TID, since there is no electrons injection into STI region during HCI before TID. The irradiation experiment under HCI bias shows that the combination of these two effects causes the change of device characteristics. The mechanism of interaction between TID and HCI is revealed.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4662-4668"},"PeriodicalIF":3.2,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TED.2025.3592176
Mohammad Sajid Nazir;Mir Mohammad Shayoub;Nivedhita Venkatesan;Patrick Fay;Yogesh Singh Chauhan
This article presents an approach for modeling polarization-graded gallium nitride (GaN) high-electron-mobility transistors (HEMTs). Unlike conventional GaN HEMTs, where a 2-D electron gas (2DEG) forms at the barrier–channel interface, graded structures feature a 3-D electron distribution. TCAD simulations are used to extract carrier density and energy band diagrams, which form the basis for model development. The derivation uses refined approximations for the Fermi–Dirac integral solution, ensuring differentiability while accurately correlating carrier density with the applied gate bias through the use of potential balance. A surface-potential-based approach is subsequently used to model terminal currents and charges. Validation of the model is done through comparison with on-wafer measurements and published data, including dc transfer and output characteristics and measured S-parameters over the frequency range of 10 MHz–110 GHz. Furthermore, model accuracy in representing linearity is verified by comparing to large signal and intermodulation measurements at 10 GHz.
{"title":"A Compact Model for Polarization-Graded HEMTs Demonstrating Enhanced Linearity","authors":"Mohammad Sajid Nazir;Mir Mohammad Shayoub;Nivedhita Venkatesan;Patrick Fay;Yogesh Singh Chauhan","doi":"10.1109/TED.2025.3592176","DOIUrl":"https://doi.org/10.1109/TED.2025.3592176","url":null,"abstract":"This article presents an approach for modeling polarization-graded gallium nitride (GaN) high-electron-mobility transistors (HEMTs). Unlike conventional GaN HEMTs, where a 2-D electron gas (2DEG) forms at the barrier–channel interface, graded structures feature a 3-D electron distribution. TCAD simulations are used to extract carrier density and energy band diagrams, which form the basis for model development. The derivation uses refined approximations for the Fermi–Dirac integral solution, ensuring differentiability while accurately correlating carrier density with the applied gate bias through the use of potential balance. A surface-potential-based approach is subsequently used to model terminal currents and charges. Validation of the model is done through comparison with on-wafer measurements and published data, including dc transfer and output characteristics and measured S-parameters over the frequency range of 10 MHz–110 GHz. Furthermore, model accuracy in representing linearity is verified by comparing to large signal and intermodulation measurements at 10 GHz.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4795-4801"},"PeriodicalIF":3.2,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TED.2025.3589196
Hyeon Seo Yun;Seul Ki Hong;Seung Jae Baik;Jaeduk Lee;Jong Kyung Park
This article presents a machine learning approach using CatBoost regression to model Z-interference (Z-INF) effects in scaled 3-D nand flash memory. As vertical integration of word-lines (WLs) increases bit density, pitch scaling intensifies cell-to-cell interference, widening threshold voltage (${V}_{text {th}}text {)}$ distributions, and reducing sensing margins. Conventional TCAD simulations and exponential function fitting can handle two-parameter relationships but cannot adequately model multiple variables affecting Z-INF. Our proposed three-parameter model incorporates both initial and final states of attack cells with victim cell characteristics, while maintaining extensibility for additional factors at smaller cell dimensions. Experimental results confirm that the model accurately predicts ${V}_{text {th}}$ distribution changes across various WL geometries with improved computational efficiency. Analysis shows Z-INF increases 4–5 times when oxide/nitride (ON) pitch decreases from 50 to 40 nm, with critical degradation below 45 nm. The model successfully accounts for process variations and identifies scaling thresholds, providing insights for reliability improvement and error correction in advanced 3-D nand architectures.
{"title":"CatBoost-Based Z-Interference Modeling for Accurate Prediction of Threshold Voltage Distribution in Scaled 3-D NAND Flash","authors":"Hyeon Seo Yun;Seul Ki Hong;Seung Jae Baik;Jaeduk Lee;Jong Kyung Park","doi":"10.1109/TED.2025.3589196","DOIUrl":"https://doi.org/10.1109/TED.2025.3589196","url":null,"abstract":"This article presents a machine learning approach using CatBoost regression to model Z-interference (Z-INF) effects in scaled 3-D <sc>nand</small> flash memory. As vertical integration of word-lines (WLs) increases bit density, pitch scaling intensifies cell-to-cell interference, widening threshold voltage (<inline-formula> <tex-math>${V}_{text {th}}text {)}$ </tex-math></inline-formula> distributions, and reducing sensing margins. Conventional TCAD simulations and exponential function fitting can handle two-parameter relationships but cannot adequately model multiple variables affecting Z-INF. Our proposed three-parameter model incorporates both initial and final states of attack cells with victim cell characteristics, while maintaining extensibility for additional factors at smaller cell dimensions. Experimental results confirm that the model accurately predicts <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> distribution changes across various WL geometries with improved computational efficiency. Analysis shows Z-INF increases 4–5 times when oxide/nitride (ON) pitch decreases from 50 to 40 nm, with critical degradation below 45 nm. The model successfully accounts for process variations and identifies scaling thresholds, providing insights for reliability improvement and error correction in advanced 3-D <sc>nand</small> architectures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4851-4855"},"PeriodicalIF":3.2,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TED.2025.3588149
Haimeng Huang;Xiao Wang;Haoyue Zhang;Zhentao Xiao;Juncheng Xiong;Hongqiang Yang
Unified temperature-dependent models are developed to optimize ${R} {_{text {sp}}}$ for the insulating pillar superjunction (IP-SJ) MOSFETs. The insulating pillar (i-pillar) could be intrinsic silicon in the compensated pillar SJ (CP-SJ) structure, oxide in the oxide pillar SJ (OP-SJ) structure, or even air in the air pillar SJ (AP-SJ) structure. These three typical structures are investigated and compared. Extensive investigations reveal that CP-SJ exhibits no improvement ${R} {_{text {sp}}}$ compared with the conventional SJ (C-SJ) structure. The AP-SJ (with the lowest relative dielectric constant of unity) possesses the best ${R} {_{text {sp}}}$ , especially with high BV and narrow half cell width b, and large drain-to-source voltage (${V} {_{text {DS}}}$ ), due to better suppression of JFET effect. For BV ${=}1250$ V and ${b}{=}0.6~{mu }$ m, theoretical optimization predicts a largest reduction up to 20.5% in ${R} {_{text {sp}}}$ with ${V} {_{text {DS}} =}5$ V for the AP-SJ at room temperature. The effects of temperature (T) on the optimization results and the temperature-dependent application are also investigated.
{"title":"Optimization of Specific On-Resistance for Superjunction With Insulating Pillar Including Temperature Dependence","authors":"Haimeng Huang;Xiao Wang;Haoyue Zhang;Zhentao Xiao;Juncheng Xiong;Hongqiang Yang","doi":"10.1109/TED.2025.3588149","DOIUrl":"https://doi.org/10.1109/TED.2025.3588149","url":null,"abstract":"Unified temperature-dependent models are developed to optimize <inline-formula> <tex-math>${R} {_{text {sp}}}$ </tex-math></inline-formula> for the insulating pillar superjunction (IP-SJ) MOSFETs. The insulating pillar (i-pillar) could be intrinsic silicon in the compensated pillar SJ (CP-SJ) structure, oxide in the oxide pillar SJ (OP-SJ) structure, or even air in the air pillar SJ (AP-SJ) structure. These three typical structures are investigated and compared. Extensive investigations reveal that CP-SJ exhibits no improvement <inline-formula> <tex-math>${R} {_{text {sp}}}$ </tex-math></inline-formula> compared with the conventional SJ (C-SJ) structure. The AP-SJ (with the lowest relative dielectric constant of unity) possesses the best <inline-formula> <tex-math>${R} {_{text {sp}}}$ </tex-math></inline-formula>, especially with high BV and narrow half cell width b, and large drain-to-source voltage (<inline-formula> <tex-math>${V} {_{text {DS}}}$ </tex-math></inline-formula>), due to better suppression of JFET effect. For BV <inline-formula> <tex-math>${=}1250$ </tex-math></inline-formula> V and <inline-formula> <tex-math>${b}{=}0.6~{mu }$ </tex-math></inline-formula>m, theoretical optimization predicts a largest reduction up to 20.5% in <inline-formula> <tex-math>${R} {_{text {sp}}}$ </tex-math></inline-formula> with <inline-formula> <tex-math>${V} {_{text {DS}} =}5$ </tex-math></inline-formula> V for the AP-SJ at room temperature. The effects of temperature (T) on the optimization results and the temperature-dependent application are also investigated.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5097-5103"},"PeriodicalIF":3.2,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TED.2025.3592173
Puhao Chai;Jun Zhu;Jiale Chen;Zihao Wang
The rapid development of modern electronic technology has created an urgent demand for high-density nonvolatile memory. To address this challenge, we propose a method that leverages the Maxwell–Wagner interface polarization effect to enhance the performance of charge trapping memory (CTM). By employing Al2O3 /LaTiO3 stacked structures with differing dielectric constants as charge trapping layers (CTLs), we create abundant trapping sites and significantly boost the charge trapping capability. The memory properties were systematically investigated and compared with different interface devices. Our device shows excellent memory performance with a 20.06 V memory window and a $4.9times 10^{{13}}$ /cm2 charge trapping density at ±12 V sweep voltage, 91.2% charge retention after ten years, and stable frequency performance. These superior memory properties arise from the trapped charges that accumulate at heterogeneous interfaces to balance the electric field. Furthermore, additional thinner interfacial structures lead to a decline in memory performance due to atomic thermal diffusion. This study offers a promising approach for high-density nonvolatile memories.
{"title":"High-Performance Charge Trapping Memories Achieved by Heterogeneous Interface Polarization","authors":"Puhao Chai;Jun Zhu;Jiale Chen;Zihao Wang","doi":"10.1109/TED.2025.3592173","DOIUrl":"https://doi.org/10.1109/TED.2025.3592173","url":null,"abstract":"The rapid development of modern electronic technology has created an urgent demand for high-density nonvolatile memory. To address this challenge, we propose a method that leverages the Maxwell–Wagner interface polarization effect to enhance the performance of charge trapping memory (CTM). By employing Al2O3 /LaTiO3 stacked structures with differing dielectric constants as charge trapping layers (CTLs), we create abundant trapping sites and significantly boost the charge trapping capability. The memory properties were systematically investigated and compared with different interface devices. Our device shows excellent memory performance with a 20.06 V memory window and a <inline-formula> <tex-math>$4.9times 10^{{13}}$ </tex-math></inline-formula>/cm2 charge trapping density at ±12 V sweep voltage, 91.2% charge retention after ten years, and stable frequency performance. These superior memory properties arise from the trapped charges that accumulate at heterogeneous interfaces to balance the electric field. Furthermore, additional thinner interfacial structures lead to a decline in memory performance due to atomic thermal diffusion. This study offers a promising approach for high-density nonvolatile memories.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4910-4915"},"PeriodicalIF":3.2,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TED.2025.3591582
Yuan-Ming Liu;Jih-Chao Chiu;Yu-Shan Wu;Yu-Chen Fan;Rong-Wei Ma;Hidenari Fujiwara;Kuan-Wei Lu;C. W. Liu
The amorphous InGaZnO (a-IGZO) gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) are demonstrated. All process temperatures are below $300~^{circ }$ C, showing back-end-of-line (BEOL) compatibility. The channel release (CR) is achieved by reactive-ion etching (RIE) with extremely high etching selectivity of the SiN sacrificial layer (SL) over the a-IGZO channel. A novel composite field oxide (FOX) is exploited to form an etching stop layer and to avoid gate leakage. The gate stacks are deposited all-at-once using plasma-enhanced atomic layer deposition (PEALD) following the CR to achieve the GAA structure, which is confirmed by the energy-dispersive X-ray spectroscopy (EDS) mapping. The device with a gate length of 52 nm shows ${I}_{text {off}} lt 10^{-{7}} ~mu $ A/$mu $ m (below detection limit), high ${I}_{text {on}}$ /${I}_{text {off}} gt 1.3times 10^{{8}}$ , positive threshold voltage (${V}_{T}$ ) of 3.5 V, and a clear saturation region in the output characteristic. Moreover, a subthreshold swing (SS) as low as 67 mV/dec is achieved a transition with the gate length of 150 nm.
{"title":"Amorphous IGZO GAA Nanosheet FETs Using Typical Channel Release","authors":"Yuan-Ming Liu;Jih-Chao Chiu;Yu-Shan Wu;Yu-Chen Fan;Rong-Wei Ma;Hidenari Fujiwara;Kuan-Wei Lu;C. W. Liu","doi":"10.1109/TED.2025.3591582","DOIUrl":"https://doi.org/10.1109/TED.2025.3591582","url":null,"abstract":"The amorphous InGaZnO (a-IGZO) gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) are demonstrated. All process temperatures are below <inline-formula> <tex-math>$300~^{circ }$ </tex-math></inline-formula>C, showing back-end-of-line (BEOL) compatibility. The channel release (CR) is achieved by reactive-ion etching (RIE) with extremely high etching selectivity of the SiN sacrificial layer (SL) over the a-IGZO channel. A novel composite field oxide (FOX) is exploited to form an etching stop layer and to avoid gate leakage. The gate stacks are deposited all-at-once using plasma-enhanced atomic layer deposition (PEALD) following the CR to achieve the GAA structure, which is confirmed by the energy-dispersive X-ray spectroscopy (EDS) mapping. The device with a gate length of 52 nm shows <inline-formula> <tex-math>${I}_{text {off}} lt 10^{-{7}} ~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m (below detection limit), high <inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {off}} gt 1.3times 10^{{8}}$ </tex-math></inline-formula>, positive threshold voltage (<inline-formula> <tex-math>${V}_{T}$ </tex-math></inline-formula>) of 3.5 V, and a clear saturation region in the output characteristic. Moreover, a subthreshold swing (SS) as low as 67 mV/dec is achieved a transition with the gate length of 150 nm.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4998-5003"},"PeriodicalIF":3.2,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TED.2025.3591573
Mukul Kumar;Chao-Hsin Wu
This study introduces a novel approach to enhance the current sensing capabilities of triple quantum-well heterojunction bipolar transistors (TQW-HBTs) through a cascaded Darlington transistor pair configuration. The circuit, comprising two intricately designed TQW-HBTs, is thoroughly investigated for its temperature-dependent collector current behavior across substrate temperatures ranging from $25~^{circ }$ C to $85~^{circ }$ C. The Darlington configuration significantly amplifies the low sensing current of the TQW-HBT, achieving a current gain of 1.59 at $25~^{circ }$ C and 1.83 at $85~^{circ }$ C under a common bias of ${V}_{text {CE}}$ of 3.6 V and ${I}_{text {B}}$ of 1 mA. The TQW-HBT exhibits an increase in current gain from 0.37 to 0.94 as the temperature rises from $25~^{circ }$ C to $85~^{circ }$ C, while the Darlington transistor achieves a larger increase in current gain from 0.59 to 1.71 under the same conditions. At $25~^{circ }$ C, the current sensitivity of the TQW-HBT is measured at $5.74~mu $ A/°C, while the Darlington transistor demonstrates a higher sensitivity of $10.15~mu $ A/°C. As the temperature reaches $85~^{circ }$ C, these sensitivities further increase to $12.86~mu $ A/°C for the TQW-HBT and $27~mu $ A/°C for the Darlington transistor. Additionally, the circuit allows for the current-to-voltage conversion, achieving a maximum voltage sensitivity of 16.07 mV/°C at $85~^{circ }$ C, with ${V}_{text {DD}}$ of 4 V and ${I}_{B}$ of 1 mA. These results highlight the superior performance of the TQW-HBT cascaded Darlington transistor over conventional bipolar-based temperature sensors, positioning it as a promising candidate for the next-generation ultrahigh-sensitivity thermal sensor technologies.
{"title":"Ultrahigh Thermal Sensitivity Using a Darlington-Cascaded Triple-Quantum-Well Heterojunction Bipolar Light-Emitting Transistors","authors":"Mukul Kumar;Chao-Hsin Wu","doi":"10.1109/TED.2025.3591573","DOIUrl":"https://doi.org/10.1109/TED.2025.3591573","url":null,"abstract":"This study introduces a novel approach to enhance the current sensing capabilities of triple quantum-well heterojunction bipolar transistors (TQW-HBTs) through a cascaded Darlington transistor pair configuration. The circuit, comprising two intricately designed TQW-HBTs, is thoroughly investigated for its temperature-dependent collector current behavior across substrate temperatures ranging from <inline-formula> <tex-math>$25~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C. The Darlington configuration significantly amplifies the low sensing current of the TQW-HBT, achieving a current gain of 1.59 at <inline-formula> <tex-math>$25~^{circ }$ </tex-math></inline-formula>C and 1.83 at <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C under a common bias of <inline-formula> <tex-math>${V}_{text {CE}}$ </tex-math></inline-formula> of 3.6 V and <inline-formula> <tex-math>${I}_{text {B}}$ </tex-math></inline-formula> of 1 mA. The TQW-HBT exhibits an increase in current gain from 0.37 to 0.94 as the temperature rises from <inline-formula> <tex-math>$25~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C, while the Darlington transistor achieves a larger increase in current gain from 0.59 to 1.71 under the same conditions. At <inline-formula> <tex-math>$25~^{circ }$ </tex-math></inline-formula>C, the current sensitivity of the TQW-HBT is measured at <inline-formula> <tex-math>$5.74~mu $ </tex-math></inline-formula>A/°C, while the Darlington transistor demonstrates a higher sensitivity of <inline-formula> <tex-math>$10.15~mu $ </tex-math></inline-formula>A/°C. As the temperature reaches <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C, these sensitivities further increase to <inline-formula> <tex-math>$12.86~mu $ </tex-math></inline-formula>A/°C for the TQW-HBT and <inline-formula> <tex-math>$27~mu $ </tex-math></inline-formula>A/°C for the Darlington transistor. Additionally, the circuit allows for the current-to-voltage conversion, achieving a maximum voltage sensitivity of 16.07 mV/°C at <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C, with <inline-formula> <tex-math>${V}_{text {DD}}$ </tex-math></inline-formula> of 4 V and <inline-formula> <tex-math>${I}_{B}$ </tex-math></inline-formula> of 1 mA. These results highlight the superior performance of the TQW-HBT cascaded Darlington transistor over conventional bipolar-based temperature sensors, positioning it as a promising candidate for the next-generation ultrahigh-sensitivity thermal sensor technologies.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5146-5153"},"PeriodicalIF":3.2,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TED.2025.3588521
Yonggui Zhai;Rui Wang;Hongguang Wang;Meng Cao;Shu Lin;Na Zhang;Yun Li;Wanzhao Cui;Yongdong Li
This study proposes a method for suppressing the multipactor effect in high-power microwave devices for spacecraft applications by integrating dielectric materials. Electromagnetic fields are numerically analyzed using the CST Microwave Studio, while multipactor thresholds are accurately predicted via an in-house developed 3-D particle-in-cell (PIC) simulation code. A systematic investigation is conducted to examine how the geometric parameters and material properties of dielectric influence multipactor. Simulation results show that when the dielectric width matches that of a parallel-plate or rectangular waveguide, increasing both the thickness and relative permittivity enhances the amplitude of the radio frequency (RF) electric field, accompanied by a decrease in the multipactor threshold. Conversely, when the dielectric width is smaller than the waveguide, the RF electric field amplitude decreases, leading to an increase in the multipactor threshold. Notably, partially filled dielectric can reduce the RF electric field amplitude by up to 90%, and improve the threshold by as much as 40 times compared to unfilled dielectric. These findings provide critical design insights for high-power microwave components in space applications.
{"title":"Suppressing the Multipactor in Microwave Devices by Introducing the Dielectric Material","authors":"Yonggui Zhai;Rui Wang;Hongguang Wang;Meng Cao;Shu Lin;Na Zhang;Yun Li;Wanzhao Cui;Yongdong Li","doi":"10.1109/TED.2025.3588521","DOIUrl":"https://doi.org/10.1109/TED.2025.3588521","url":null,"abstract":"This study proposes a method for suppressing the multipactor effect in high-power microwave devices for spacecraft applications by integrating dielectric materials. Electromagnetic fields are numerically analyzed using the CST Microwave Studio, while multipactor thresholds are accurately predicted via an in-house developed 3-D particle-in-cell (PIC) simulation code. A systematic investigation is conducted to examine how the geometric parameters and material properties of dielectric influence multipactor. Simulation results show that when the dielectric width matches that of a parallel-plate or rectangular waveguide, increasing both the thickness and relative permittivity enhances the amplitude of the radio frequency (RF) electric field, accompanied by a decrease in the multipactor threshold. Conversely, when the dielectric width is smaller than the waveguide, the RF electric field amplitude decreases, leading to an increase in the multipactor threshold. Notably, partially filled dielectric can reduce the RF electric field amplitude by up to 90%, and improve the threshold by as much as 40 times compared to unfilled dielectric. These findings provide critical design insights for high-power microwave components in space applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5195-5200"},"PeriodicalIF":3.2,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-28DOI: 10.1109/TED.2025.3589197
Xian Wu;Sen Gao;Lei Xiao;Jing Wang
The subthreshold swing (SS) of conventional field-effect transistors (FETs) is fundamentally limited to 60 mV/dec at room temperature, which significantly constrains the sensitivity of biosensors in detecting weak biological signals effectively. To address this bottleneck, we present a comprehensive, physics-based, and circuit-compatible analytical model for a 2-D material negative capacitance FET (NCFET) biosensor. The model features a top-gate architecture incorporating a HfZrO (HZO) ferroelectric layer for the first time, designed to be fully compatible with standard semiconductor fabrication processes. It provides a robust theoretical framework for accurately predicting the performance of NCFET biosensors (NC-BioFET) and addresses the limitations of traditional FETs. Using an n-WSe2 NCFET biosensor as an example, we validate the model through extensive simulations, achieving an SS as low as 30 mV/dec and demonstrating excellent pH sensing performance. In a model-constructed aqueous environment, the sensor exhibits an impressive pH detection sensitivity of 1799/pH, significantly outperforming the 461/pH sensitivity observed in its conventional FET biosensor. Furthermore, to validate the accuracy of the model, we fabricated WSe2 NCFET biosensors and tested their response across a range of pH. The model shows excellent agreement with experimental results in terms of drain current, SS, and voltage/current sensitivity. This work establishes a robust theoretical and experimental foundation for the design and optimization of high-performance and low-power biosensors. It also bridges the gap between NCFET technology and biosensing applications, paving the way for next-generation biosensors with ultrahigh sensitivity and superior signal detection capabilities.
{"title":"Analytical Modeling of Negative Capacitance Field-Effect Transistor for Highly Sensitive Biosensor Applications","authors":"Xian Wu;Sen Gao;Lei Xiao;Jing Wang","doi":"10.1109/TED.2025.3589197","DOIUrl":"https://doi.org/10.1109/TED.2025.3589197","url":null,"abstract":"The subthreshold swing (SS) of conventional field-effect transistors (FETs) is fundamentally limited to 60 mV/dec at room temperature, which significantly constrains the sensitivity of biosensors in detecting weak biological signals effectively. To address this bottleneck, we present a comprehensive, physics-based, and circuit-compatible analytical model for a 2-D material negative capacitance FET (NCFET) biosensor. The model features a top-gate architecture incorporating a HfZrO (HZO) ferroelectric layer for the first time, designed to be fully compatible with standard semiconductor fabrication processes. It provides a robust theoretical framework for accurately predicting the performance of NCFET biosensors (NC-BioFET) and addresses the limitations of traditional FETs. Using an n-WSe2 NCFET biosensor as an example, we validate the model through extensive simulations, achieving an SS as low as 30 mV/dec and demonstrating excellent pH sensing performance. In a model-constructed aqueous environment, the sensor exhibits an impressive pH detection sensitivity of 1799/pH, significantly outperforming the 461/pH sensitivity observed in its conventional FET biosensor. Furthermore, to validate the accuracy of the model, we fabricated WSe2 NCFET biosensors and tested their response across a range of pH. The model shows excellent agreement with experimental results in terms of drain current, SS, and voltage/current sensitivity. This work establishes a robust theoretical and experimental foundation for the design and optimization of high-performance and low-power biosensors. It also bridges the gap between NCFET technology and biosensing applications, paving the way for next-generation biosensors with ultrahigh sensitivity and superior signal detection capabilities.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5154-5162"},"PeriodicalIF":3.2,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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