In this brief, a $2{^{text {nd}}}$ -order $g_{mathrm { m}} - C$ lowpass filter with a practical input linear range of $400~{mathrm { mV}}_{mathrm { P}}$ dedicated to ECG signal acquisition is proposed. This filter employs a degenerative source-coupled-pair circuit as a $g_{mathrm { m}}$ cell. It enhances the linear input range by a factor of $times 4$ compared with the source follower filter. Additionally, to mitigate the effect of current source mismatch, a dynamic element matching technique is applied. By doing so, HD2 is suppressed more than 1.5 dB over the entire passband frequency. This proposed filter is implemented in a $0.18~mu $ m CMOS process. It offers a 250-Hz bandwidth with input-referred noise and a dynamic range of $82.1~mu {mathrm { V}}_{mathrm {mathrm {rms}}}$ and 67.34 dB, respectively. The power consumption of 38.4 nW is achieved with a 1.2 V supply. Compared with other recent nano-power filters, the proposed filter provides the highest linear input range with competitive Figure-of-Merit to the top-tier designs. It is therefore beneficial to the practical implementation of a low-power ECG acquisition system.
{"title":"A 38.4 nW, 1.2 V, 250-Hz, 2nd-Order gm – C LPF With Degenerative SCP Transconductors Achieving 800-mVPP Input Range and 82.1- μVrms IRN for ECG Acquisition","authors":"Surachoke Thanapitak;Prajuab Pawarangkoon;Wanlop Surakampontorn;Rafidah Ahmad;Ruhaifi Abdullah Zawawi;Asrulnizam Abd. Manaf;Suriya Adirek;Chaiyan Chanapromma","doi":"10.1109/TCSII.2024.3451494","DOIUrl":"10.1109/TCSII.2024.3451494","url":null,"abstract":"In this brief, a \u0000<inline-formula> <tex-math>$2{^{text {nd}}}$ </tex-math></inline-formula>\u0000-order \u0000<inline-formula> <tex-math>$g_{mathrm { m}} - C$ </tex-math></inline-formula>\u0000 lowpass filter with a practical input linear range of \u0000<inline-formula> <tex-math>$400~{mathrm { mV}}_{mathrm { P}}$ </tex-math></inline-formula>\u0000 dedicated to ECG signal acquisition is proposed. This filter employs a degenerative source-coupled-pair circuit as a \u0000<inline-formula> <tex-math>$g_{mathrm { m}}$ </tex-math></inline-formula>\u0000 cell. It enhances the linear input range by a factor of \u0000<inline-formula> <tex-math>$times 4$ </tex-math></inline-formula>\u0000 compared with the source follower filter. Additionally, to mitigate the effect of current source mismatch, a dynamic element matching technique is applied. By doing so, HD2 is suppressed more than 1.5 dB over the entire passband frequency. This proposed filter is implemented in a \u0000<inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>\u0000m CMOS process. It offers a 250-Hz bandwidth with input-referred noise and a dynamic range of \u0000<inline-formula> <tex-math>$82.1~mu {mathrm { V}}_{mathrm {mathrm {rms}}}$ </tex-math></inline-formula>\u0000 and 67.34 dB, respectively. The power consumption of 38.4 nW is achieved with a 1.2 V supply. Compared with other recent nano-power filters, the proposed filter provides the highest linear input range with competitive Figure-of-Merit to the top-tier designs. It is therefore beneficial to the practical implementation of a low-power ECG acquisition system.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"3-7"},"PeriodicalIF":4.0,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-29DOI: 10.1109/TCSII.2024.3452056
Lingling Wu;Wenying Hou;Xinrong Yang;Haitao Li
This brief addresses the conservation of total-activity-degree for mix-valued logical networks (MVLNs) via the algebraic state space representation method. With the aid of total-activity-degree vector, a criterion is proposed for verifying the conservation of total-activity-degree for MVLNs. Besides, the effect of deterministic function perturbations on the conservation of total-activity-degree for MVLNs is explored, and the corresponding criterion is established for the robust conservation of total-activity-degree.
{"title":"Conservation of Total-Activity-Degree for Mix-Valued Logical Networks","authors":"Lingling Wu;Wenying Hou;Xinrong Yang;Haitao Li","doi":"10.1109/TCSII.2024.3452056","DOIUrl":"10.1109/TCSII.2024.3452056","url":null,"abstract":"This brief addresses the conservation of total-activity-degree for mix-valued logical networks (MVLNs) via the algebraic state space representation method. With the aid of total-activity-degree vector, a criterion is proposed for verifying the conservation of total-activity-degree for MVLNs. Besides, the effect of deterministic function perturbations on the conservation of total-activity-degree for MVLNs is explored, and the corresponding criterion is established for the robust conservation of total-activity-degree.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"188-192"},"PeriodicalIF":4.0,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief is concerned with the stability analysis of amplidyne electrical systems (AESs) equipped with a delayed PI controller. Firstly, the model of AESs with time-varying delays and a PI controller is established. Secondly, a less conservative stability criterion of AESs related time delay is obtained by utilizing an advanced matrix-injection method. Finally, the effectiveness of the proposed criterion is verified by a case study.
{"title":"Stability Analysis of Amplidyne Electrical Systems With Time-Varying Delay via a Matrix-Injection Method","authors":"Hong-Jian Huang;Chuan-Ke Zhang;Li Jin;Hong-Zhang Wang;Zhe-Li Yuan","doi":"10.1109/TCSII.2024.3451555","DOIUrl":"10.1109/TCSII.2024.3451555","url":null,"abstract":"This brief is concerned with the stability analysis of amplidyne electrical systems (AESs) equipped with a delayed PI controller. Firstly, the model of AESs with time-varying delays and a PI controller is established. Secondly, a less conservative stability criterion of AESs related time delay is obtained by utilizing an advanced matrix-injection method. Finally, the effectiveness of the proposed criterion is verified by a case study.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"183-187"},"PeriodicalIF":4.0,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-29DOI: 10.1109/TCSII.2024.3451971
Yushu Yang;Zihang Wang;Jianfei Wang;Jia Hou;Yang Su;Chen Yang
Lattice-based cryptography has experienced significant advancements in recent years due to its versatility and simplicity. The ring learning with errors (RLWE) problem is widely adopted in lattice-based cryptography. However, the polynomial multiplication is the performance bottleneck of RLWE-based cryptography, which requires further examination. In this brief, a lightweight and efficient encryption/decryption coprocessor for RLWE-based cryptography is proposed. The time complexity of the Schoolbook polynomial multiplication (SPM) is reduced from ${n}^{2}$ to $ {n}^{ {2}} {/8}$ by enhancing multiplication parallelism. Moreover, an optimized structure for the Compressed cumulative distribution table (CDT) Gaussian sampler is proposed, resulting in 22.2% reduction in storage resource. The proposed SPM structure demonstrates a $2.3times $ performance speedup and $2.7times $ hardware efficiency for the encryption core, compared with state-of-the-art SPM accelerators. Additionally, it achieves a $2.4times $ performance speedup and $3.2times $ improvements on hardware efficiency for the decryption core.
{"title":"A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography","authors":"Yushu Yang;Zihang Wang;Jianfei Wang;Jia Hou;Yang Su;Chen Yang","doi":"10.1109/TCSII.2024.3451971","DOIUrl":"10.1109/TCSII.2024.3451971","url":null,"abstract":"Lattice-based cryptography has experienced significant advancements in recent years due to its versatility and simplicity. The ring learning with errors (RLWE) problem is widely adopted in lattice-based cryptography. However, the polynomial multiplication is the performance bottleneck of RLWE-based cryptography, which requires further examination. In this brief, a lightweight and efficient encryption/decryption coprocessor for RLWE-based cryptography is proposed. The time complexity of the Schoolbook polynomial multiplication (SPM) is reduced from \u0000<inline-formula> <tex-math>${n}^{2}$ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$ {n}^{ {2}} {/8}$ </tex-math></inline-formula>\u0000 by enhancing multiplication parallelism. Moreover, an optimized structure for the Compressed cumulative distribution table (CDT) Gaussian sampler is proposed, resulting in 22.2% reduction in storage resource. The proposed SPM structure demonstrates a \u0000<inline-formula> <tex-math>$2.3times $ </tex-math></inline-formula>\u0000 performance speedup and \u0000<inline-formula> <tex-math>$2.7times $ </tex-math></inline-formula>\u0000 hardware efficiency for the encryption core, compared with state-of-the-art SPM accelerators. Additionally, it achieves a \u0000<inline-formula> <tex-math>$2.4times $ </tex-math></inline-formula>\u0000 performance speedup and \u0000<inline-formula> <tex-math>$3.2times $ </tex-math></inline-formula>\u0000 improvements on hardware efficiency for the decryption core.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5004-5008"},"PeriodicalIF":4.0,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a discrete multi-tone (DMT) wireline transceiver (TRX) datapath and introduces the RFSoC-based real-time hardware platform to quickly sweep the optimum bit and power loading profile constrained by the peak-to-average-power ratio (PAPR). The datapath is implemented based on 32-parallel multi-path delay feedback (MDF) fast Fourier transform (FFT)/inverse FFT (IFFT) processors to save resources, integrating with the sign-sign least mean square (SS-LMS) engine. The loading is computed for the channel signal-to-noise ratio (SNR) and PAPR. The platform consists of 2.048 GS/s data converters, the DMT datapath implemented on programmable logic (PL) running at 64 MHz, and the channel board. This system enables a quick bit-error-rate (BER) test at an order of 1.0E-9, accelerating the finding of optimal loading with realistic hardware effects and random clipping events. Experimental results show that the data rate could reach a maximum of 6.82 Gb/s at a BER of 5.7E-4 and a minimum BER of 3.7E-7 for a target data rate of 4.81 Gb/s with a channel exhibiting 16.3 dB insertion loss (IL) at Nyquist.
{"title":"A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC","authors":"Jaewon Lee;Seoyoung Jang;Donggeon Kim;Yujin Choi;Jong-Hyeok Yoon;Matthias Braendli;Thomas Morf;Marcel Kossel;Pier-Andrea Francese;Gain Kim","doi":"10.1109/TCSII.2024.3450695","DOIUrl":"10.1109/TCSII.2024.3450695","url":null,"abstract":"This brief presents a discrete multi-tone (DMT) wireline transceiver (TRX) datapath and introduces the RFSoC-based real-time hardware platform to quickly sweep the optimum bit and power loading profile constrained by the peak-to-average-power ratio (PAPR). The datapath is implemented based on 32-parallel multi-path delay feedback (MDF) fast Fourier transform (FFT)/inverse FFT (IFFT) processors to save resources, integrating with the sign-sign least mean square (SS-LMS) engine. The loading is computed for the channel signal-to-noise ratio (SNR) and PAPR. The platform consists of 2.048 GS/s data converters, the DMT datapath implemented on programmable logic (PL) running at 64 MHz, and the channel board. This system enables a quick bit-error-rate (BER) test at an order of 1.0E-9, accelerating the finding of optimal loading with realistic hardware effects and random clipping events. Experimental results show that the data rate could reach a maximum of 6.82 Gb/s at a BER of 5.7E-4 and a minimum BER of 3.7E-7 for a target data rate of 4.81 Gb/s with a channel exhibiting 16.3 dB insertion loss (IL) at Nyquist.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4889-4893"},"PeriodicalIF":4.0,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-26DOI: 10.1109/TCSII.2024.3449631
Hao Guo;Kaizhe Guo;Zhicheng Lin;Kam Man Shum;Chi Hou Chan
This brief presents a high gain frequency multiplier chain in 65-nm CMOS technology. The frequency doubler transistor interconnection layout is carefully designed to minimize the parasitic effect and enhance performance. The gate bias voltage is discussed and optimized to improve the doubler conversion gain. A shorting stub for the second harmonic at the gate terminal is added to enhance both the conversion gain and saturated output power. A two-stage neutralized power amplifier is designed to provide sufficient power to drive the frequency doubler. Measurement results show the chip achieves a peak conversion gain of 13.2 dB at 208 GHz with −17.6 dBm input power. The saturation output power is 0.3 dBm, while the chip still maintains an 11 dB conversion gain at 212 GHz. The 3-dB output power bandwidth is 13.2% from 190 to 217 GHz. With 100 mW DC power consumption, the peak power-added efficiency is 0.99%.
{"title":"A 190-217-GHz Frequency Multiplier Chain With 13.2 dB Conversion Gain in 65-nm CMOS","authors":"Hao Guo;Kaizhe Guo;Zhicheng Lin;Kam Man Shum;Chi Hou Chan","doi":"10.1109/TCSII.2024.3449631","DOIUrl":"10.1109/TCSII.2024.3449631","url":null,"abstract":"This brief presents a high gain frequency multiplier chain in 65-nm CMOS technology. The frequency doubler transistor interconnection layout is carefully designed to minimize the parasitic effect and enhance performance. The gate bias voltage is discussed and optimized to improve the doubler conversion gain. A shorting stub for the second harmonic at the gate terminal is added to enhance both the conversion gain and saturated output power. A two-stage neutralized power amplifier is designed to provide sufficient power to drive the frequency doubler. Measurement results show the chip achieves a peak conversion gain of 13.2 dB at 208 GHz with −17.6 dBm input power. The saturation output power is 0.3 dBm, while the chip still maintains an 11 dB conversion gain at 212 GHz. The 3-dB output power bandwidth is 13.2% from 190 to 217 GHz. With 100 mW DC power consumption, the peak power-added efficiency is 0.99%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4859-4863"},"PeriodicalIF":4.0,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Precise illumination control of matrix light-emitting diode (LED) headlamps is crucial for both energy efficiency in electric vehicles and driver safety. Enhancing energy efficiency extends the range of electric vehicles, while ensuring reliable illumination improves driver safety in autonomous vehicles. This brief discusses the control of illumination for eight serially connected LEDs using 8-bit pulse-width modulation (PWM) combined with a gate driver. A bypass gate driver, employing a cascode current mirror structure, manages the current through each LED, minimizing variations in analog string voltage. The proposed method supports 256 levels of illumination adjustment, making it suitable for adaptive front-lighting systems (AFLS). Implemented with TSMC’s 180-nm high-voltage CMOS technology, with a maximum power supply of 70V and a chip size of 5 mm2, the system ensures precise LED control and effectively prevents overcurrent.
矩阵式发光二极管（LED）前大灯的精确照明控制对于电动汽车的能效和驾驶员的安全至关重要。提高能效可延长电动汽车的续航里程，而确保可靠的照明可提高自动驾驶汽车的驾驶安全性。本简介讨论了使用 8 位脉宽调制 (PWM) 结合栅极驱动器控制八个串联 LED 的照明。旁路栅极驱动器采用级联电流镜结构，管理通过每个 LED 的电流，最大限度地减少模拟串电压的变化。所提出的方法支持 256 级照明调节，因此适用于自适应前照明系统 (AFLS)。该系统采用台积电 180 纳米高压 CMOS 技术，最大供电电压为 70V，芯片尺寸为 5 平方毫米，可确保精确的 LED 控制，并有效防止过流。
{"title":"Precise Individual Illumination Control of Matrix LED With Bypass Gate Driver and 8-Bit PWM","authors":"Jonghyuk Chae;Jaehun Jeong;Byeongha Park;Seungju Lee;Jongmin Park;Jinwook Burm","doi":"10.1109/TCSII.2024.3448489","DOIUrl":"10.1109/TCSII.2024.3448489","url":null,"abstract":"Precise illumination control of matrix light-emitting diode (LED) headlamps is crucial for both energy efficiency in electric vehicles and driver safety. Enhancing energy efficiency extends the range of electric vehicles, while ensuring reliable illumination improves driver safety in autonomous vehicles. This brief discusses the control of illumination for eight serially connected LEDs using 8-bit pulse-width modulation (PWM) combined with a gate driver. A bypass gate driver, employing a cascode current mirror structure, manages the current through each LED, minimizing variations in analog string voltage. The proposed method supports 256 levels of illumination adjustment, making it suitable for adaptive front-lighting systems (AFLS). Implemented with TSMC’s 180-nm high-voltage CMOS technology, with a maximum power supply of 70V and a chip size of 5 mm2, the system ensures precise LED control and effectively prevents overcurrent.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4653-4657"},"PeriodicalIF":4.0,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a 5.4-to-7.4 GHz injection-locked frequency tripler (ILFT) with enhanced $3^{rd}$ harmonic injection using collector-to-base transformer-coupled input buffer. Regenerative feedback in the input buffer using a collector-to-base coupled transformer provides up to 2x improvement in the locking range of the ILFT compared to a conventional ILFT. Fabricated in $0.13~mu $ m BiCMOS technology, the tripler exhibits a jitter tracking bandwidth, $omega _{JTB}$ of 20 MHz. Due to its optimal jitter tracking bandwidth, the tripler filters the input noise beyond the $omega _{JTB}$ and effectively suppresses the free-running oscillator’s phase noise below $omega _{JTB}$ . We achieve an output rms jitter of 33.6 fs for an input rms jitter of 68 fs over a bandwidth of [1k-100MHz]. The ILFT demonstrates a good sub-harmonic rejection ratio, SHRR of 51 dB and 48 dB for fundamental and second harmonic, respectively.
{"title":"A 5.4-7.4 GHz Ultra-Low Jitter Injection-Locked Frequency Tripler With 3rd Harmonic Current Boosting Input Buffer","authors":"Sonam Sadhukhan;Arpan Thakkar;Pranav Kumar;Saurabh Saxena","doi":"10.1109/TCSII.2024.3446728","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3446728","url":null,"abstract":"We present a 5.4-to-7.4 GHz injection-locked frequency tripler (ILFT) with enhanced \u0000<inline-formula> <tex-math>$3^{rd}$ </tex-math></inline-formula>\u0000 harmonic injection using collector-to-base transformer-coupled input buffer. Regenerative feedback in the input buffer using a collector-to-base coupled transformer provides up to 2x improvement in the locking range of the ILFT compared to a conventional ILFT. Fabricated in \u0000<inline-formula> <tex-math>$0.13~mu $ </tex-math></inline-formula>\u0000 m BiCMOS technology, the tripler exhibits a jitter tracking bandwidth, \u0000<inline-formula> <tex-math>$omega _{JTB}$ </tex-math></inline-formula>\u0000 of 20 MHz. Due to its optimal jitter tracking bandwidth, the tripler filters the input noise beyond the \u0000<inline-formula> <tex-math>$omega _{JTB}$ </tex-math></inline-formula>\u0000 and effectively suppresses the free-running oscillator’s phase noise below \u0000<inline-formula> <tex-math>$omega _{JTB}$ </tex-math></inline-formula>\u0000. We achieve an output rms jitter of 33.6 fs for an input rms jitter of 68 fs over a bandwidth of [1k-100MHz]. The ILFT demonstrates a good sub-harmonic rejection ratio, SHRR of 51 dB and 48 dB for fundamental and second harmonic, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4693-4697"},"PeriodicalIF":4.0,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-20DOI: 10.1109/TCSII.2024.3446534
Sang-Hun Lee;Won-Young Lee
This brief presents a 0.6 V 4-MS/s 2-bit conversion/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator which is employed to suppress the input referred noise. The VCO-based comparison requires many oscillation cycles to amplify phase differences between VCOs if the input voltage difference is small. In this design, therefore, a 2-bit conversion/cycle scheme is adopted to optimize the ADC sampling rate and an asynchronous timing controller is applied to optimize the conversion time. The proposed SAR ADC is fabricated in 65-nm CMOS technology. At the 0.6 V supply voltage and the 4-MS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.42 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.58/−0.79 LSB and +0.52/−0.75 LSB, respectively. The figure of merits (FoM) is 6.59 fJ/conversion-step with the power consumption of $15.93~mu $ W.
{"title":"A 0.6-V 4-MS/s Asynchronous SAR ADC With 2-Bit Conversion/Cycle Time-Domain Comparator","authors":"Sang-Hun Lee;Won-Young Lee","doi":"10.1109/TCSII.2024.3446534","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3446534","url":null,"abstract":"This brief presents a 0.6 V 4-MS/s 2-bit conversion/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator which is employed to suppress the input referred noise. The VCO-based comparison requires many oscillation cycles to amplify phase differences between VCOs if the input voltage difference is small. In this design, therefore, a 2-bit conversion/cycle scheme is adopted to optimize the ADC sampling rate and an asynchronous timing controller is applied to optimize the conversion time. The proposed SAR ADC is fabricated in 65-nm CMOS technology. At the 0.6 V supply voltage and the 4-MS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.42 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.58/−0.79 LSB and +0.52/−0.75 LSB, respectively. The figure of merits (FoM) is 6.59 fJ/conversion-step with the power consumption of \u0000<inline-formula> <tex-math>$15.93~mu $ </tex-math></inline-formula>\u0000 W.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4648-4652"},"PeriodicalIF":4.0,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief proposes an efficient structure for electroencephalogram (EEG) signal recording. A single-sample strategy is proposed to mitigate metastability issues in Voltage-Controlled Oscillator (VCO) Analog Front Ends (AFEs), offering timing margins of 14 phase cycles and simplifying the result arbitration logic to 1-bit multiplexing. Additionally, an analysis of existing EEG sub-band filter designs is presented, followed by an efficient band multiplexing serial multiplier structure that capitalizes on timing slacks. This design features a reduction in both the number of multipliers and the complexity of the multiplexing network. The proposed design was implemented using 40nm CMOS technology. The VCO-AFE demonstrates stable, error-free recordings with an input-referred noise (IRN) of $0.66boldsymbol {mu }$ V $boldsymbol {_{rms}}$ within 0.5–60Hz, according to the measurement results. The proposed sub-band filter exhibits substantial savings of 11% and 51% in area and power, respectively, compared to prior work when scaled to the same technology node.
{"title":"Efficient Metastability Mitigation and Sub-Band Filtering in VCO-Based EEG Recording","authors":"Zijian Tang;Chao Sun;Yuan Ma;Minqian Zheng;Chao Zhang;Zhixiong Ma;Tongfei Wang;Milin Zhang","doi":"10.1109/TCSII.2024.3446187","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3446187","url":null,"abstract":"This brief proposes an efficient structure for electroencephalogram (EEG) signal recording. A single-sample strategy is proposed to mitigate metastability issues in Voltage-Controlled Oscillator (VCO) Analog Front Ends (AFEs), offering timing margins of 14 phase cycles and simplifying the result arbitration logic to 1-bit multiplexing. Additionally, an analysis of existing EEG sub-band filter designs is presented, followed by an efficient band multiplexing serial multiplier structure that capitalizes on timing slacks. This design features a reduction in both the number of multipliers and the complexity of the multiplexing network. The proposed design was implemented using 40nm CMOS technology. The VCO-AFE demonstrates stable, error-free recordings with an input-referred noise (IRN) of \u0000<inline-formula> <tex-math>$0.66boldsymbol {mu }$ </tex-math></inline-formula>\u0000V\u0000<inline-formula> <tex-math>$boldsymbol {_{rms}}$ </tex-math></inline-formula>\u0000 within 0.5–60Hz, according to the measurement results. The proposed sub-band filter exhibits substantial savings of 11% and 51% in area and power, respectively, compared to prior work when scaled to the same technology node.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4999-5003"},"PeriodicalIF":4.0,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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