Pub Date : 2024-08-29DOI: 10.1109/tcsii.2024.3452056
Lingling Wu, Wenying Hou, Xinrong Yang, Haitao Li
{"title":"Conservation of Total-Activity-Degree for Mix-Valued Logical Networks","authors":"Lingling Wu, Wenying Hou, Xinrong Yang, Haitao Li","doi":"10.1109/tcsii.2024.3452056","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3452056","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"77 1","pages":""},"PeriodicalIF":4.4,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-29DOI: 10.1109/tcsii.2024.3451555
Hong-Jian Huang, Chuan-Ke Zhang, Li Jin, Hong-Zhang Wang, Zhe-Li Yuan
{"title":"Stability Analysis of Amplidyne Electrical Systems With Time-Varying Delay via a Matrix-Injection Method","authors":"Hong-Jian Huang, Chuan-Ke Zhang, Li Jin, Hong-Zhang Wang, Zhe-Li Yuan","doi":"10.1109/tcsii.2024.3451555","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3451555","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"10 1","pages":""},"PeriodicalIF":4.4,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-29DOI: 10.1109/tcsii.2024.3451971
Yushu Yang, Zihang Wang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang
{"title":"A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography","authors":"Yushu Yang, Zihang Wang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang","doi":"10.1109/tcsii.2024.3451971","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3451971","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"59 1","pages":""},"PeriodicalIF":4.4,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-26DOI: 10.1109/tcsii.2024.3449631
Hao Guo, Kaizhe Guo, Zhicheng Lin, Kam Man Shum, Chi Hou Chan
{"title":"A 190-217-GHz Frequency Multiplier Chain With 13.2 dB Conversion Gain in 65-nm CMOS","authors":"Hao Guo, Kaizhe Guo, Zhicheng Lin, Kam Man Shum, Chi Hou Chan","doi":"10.1109/tcsii.2024.3449631","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3449631","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"75 1","pages":""},"PeriodicalIF":4.4,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Precise illumination control of matrix light-emitting diode (LED) headlamps is crucial for both energy efficiency in electric vehicles and driver safety. Enhancing energy efficiency extends the range of electric vehicles, while ensuring reliable illumination improves driver safety in autonomous vehicles. This brief discusses the control of illumination for eight serially connected LEDs using 8-bit pulse-width modulation (PWM) combined with a gate driver. A bypass gate driver, employing a cascode current mirror structure, manages the current through each LED, minimizing variations in analog string voltage. The proposed method supports 256 levels of illumination adjustment, making it suitable for adaptive front-lighting systems (AFLS). Implemented with TSMC’s 180-nm high-voltage CMOS technology, with a maximum power supply of 70V and a chip size of 5 mm2, the system ensures precise LED control and effectively prevents overcurrent.
矩阵式发光二极管（LED）前大灯的精确照明控制对于电动汽车的能效和驾驶员的安全至关重要。提高能效可延长电动汽车的续航里程，而确保可靠的照明可提高自动驾驶汽车的驾驶安全性。本简介讨论了使用 8 位脉宽调制 (PWM) 结合栅极驱动器控制八个串联 LED 的照明。旁路栅极驱动器采用级联电流镜结构，管理通过每个 LED 的电流，最大限度地减少模拟串电压的变化。所提出的方法支持 256 级照明调节，因此适用于自适应前照明系统 (AFLS)。该系统采用台积电 180 纳米高压 CMOS 技术，最大供电电压为 70V，芯片尺寸为 5 平方毫米，可确保精确的 LED 控制，并有效防止过流。
{"title":"Precise Individual Illumination Control of Matrix LED With Bypass Gate Driver and 8-Bit PWM","authors":"Jonghyuk Chae;Jaehun Jeong;Byeongha Park;Seungju Lee;Jongmin Park;Jinwook Burm","doi":"10.1109/TCSII.2024.3448489","DOIUrl":"10.1109/TCSII.2024.3448489","url":null,"abstract":"Precise illumination control of matrix light-emitting diode (LED) headlamps is crucial for both energy efficiency in electric vehicles and driver safety. Enhancing energy efficiency extends the range of electric vehicles, while ensuring reliable illumination improves driver safety in autonomous vehicles. This brief discusses the control of illumination for eight serially connected LEDs using 8-bit pulse-width modulation (PWM) combined with a gate driver. A bypass gate driver, employing a cascode current mirror structure, manages the current through each LED, minimizing variations in analog string voltage. The proposed method supports 256 levels of illumination adjustment, making it suitable for adaptive front-lighting systems (AFLS). Implemented with TSMC’s 180-nm high-voltage CMOS technology, with a maximum power supply of 70V and a chip size of 5 mm2, the system ensures precise LED control and effectively prevents overcurrent.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4653-4657"},"PeriodicalIF":4.0,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a 5.4-to-7.4 GHz injection-locked frequency tripler (ILFT) with enhanced $3^{rd}$ harmonic injection using collector-to-base transformer-coupled input buffer. Regenerative feedback in the input buffer using a collector-to-base coupled transformer provides up to 2x improvement in the locking range of the ILFT compared to a conventional ILFT. Fabricated in $0.13~mu $ m BiCMOS technology, the tripler exhibits a jitter tracking bandwidth, $omega _{JTB}$ of 20 MHz. Due to its optimal jitter tracking bandwidth, the tripler filters the input noise beyond the $omega _{JTB}$ and effectively suppresses the free-running oscillator’s phase noise below $omega _{JTB}$ . We achieve an output rms jitter of 33.6 fs for an input rms jitter of 68 fs over a bandwidth of [1k-100MHz]. The ILFT demonstrates a good sub-harmonic rejection ratio, SHRR of 51 dB and 48 dB for fundamental and second harmonic, respectively.
{"title":"A 5.4-7.4 GHz Ultra-Low Jitter Injection-Locked Frequency Tripler With 3rd Harmonic Current Boosting Input Buffer","authors":"Sonam Sadhukhan;Arpan Thakkar;Pranav Kumar;Saurabh Saxena","doi":"10.1109/TCSII.2024.3446728","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3446728","url":null,"abstract":"We present a 5.4-to-7.4 GHz injection-locked frequency tripler (ILFT) with enhanced \u0000<inline-formula> <tex-math>$3^{rd}$ </tex-math></inline-formula>\u0000 harmonic injection using collector-to-base transformer-coupled input buffer. Regenerative feedback in the input buffer using a collector-to-base coupled transformer provides up to 2x improvement in the locking range of the ILFT compared to a conventional ILFT. Fabricated in \u0000<inline-formula> <tex-math>$0.13~mu $ </tex-math></inline-formula>\u0000 m BiCMOS technology, the tripler exhibits a jitter tracking bandwidth, \u0000<inline-formula> <tex-math>$omega _{JTB}$ </tex-math></inline-formula>\u0000 of 20 MHz. Due to its optimal jitter tracking bandwidth, the tripler filters the input noise beyond the \u0000<inline-formula> <tex-math>$omega _{JTB}$ </tex-math></inline-formula>\u0000 and effectively suppresses the free-running oscillator’s phase noise below \u0000<inline-formula> <tex-math>$omega _{JTB}$ </tex-math></inline-formula>\u0000. We achieve an output rms jitter of 33.6 fs for an input rms jitter of 68 fs over a bandwidth of [1k-100MHz]. The ILFT demonstrates a good sub-harmonic rejection ratio, SHRR of 51 dB and 48 dB for fundamental and second harmonic, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4693-4697"},"PeriodicalIF":4.0,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-20DOI: 10.1109/TCSII.2024.3446534
Sang-Hun Lee;Won-Young Lee
This brief presents a 0.6 V 4-MS/s 2-bit conversion/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator which is employed to suppress the input referred noise. The VCO-based comparison requires many oscillation cycles to amplify phase differences between VCOs if the input voltage difference is small. In this design, therefore, a 2-bit conversion/cycle scheme is adopted to optimize the ADC sampling rate and an asynchronous timing controller is applied to optimize the conversion time. The proposed SAR ADC is fabricated in 65-nm CMOS technology. At the 0.6 V supply voltage and the 4-MS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.42 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.58/−0.79 LSB and +0.52/−0.75 LSB, respectively. The figure of merits (FoM) is 6.59 fJ/conversion-step with the power consumption of $15.93~mu $ W.
{"title":"A 0.6-V 4-MS/s Asynchronous SAR ADC With 2-Bit Conversion/Cycle Time-Domain Comparator","authors":"Sang-Hun Lee;Won-Young Lee","doi":"10.1109/TCSII.2024.3446534","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3446534","url":null,"abstract":"This brief presents a 0.6 V 4-MS/s 2-bit conversion/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator which is employed to suppress the input referred noise. The VCO-based comparison requires many oscillation cycles to amplify phase differences between VCOs if the input voltage difference is small. In this design, therefore, a 2-bit conversion/cycle scheme is adopted to optimize the ADC sampling rate and an asynchronous timing controller is applied to optimize the conversion time. The proposed SAR ADC is fabricated in 65-nm CMOS technology. At the 0.6 V supply voltage and the 4-MS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.42 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.58/−0.79 LSB and +0.52/−0.75 LSB, respectively. The figure of merits (FoM) is 6.59 fJ/conversion-step with the power consumption of \u0000<inline-formula> <tex-math>$15.93~mu $ </tex-math></inline-formula>\u0000 W.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4648-4652"},"PeriodicalIF":4.0,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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