Pub Date : 2025-10-30DOI: 10.1109/TCSII.2025.3627209
Kang Liu;Baohong Li;Qin Jiang;Yingmin Zhang;Tianqi Liu
This brief proposes a fault ride-through (FRT) strategy for hybrid cascaded high-voltage direct current (HVDC) systems using a controllable line-commutated converter (CLCC). Unlike conventional LCCs prone to commutation failures during AC faults, the CLCC provides forced commutation and ensures stable operation. When combined with series-connected modular multilevel converters (MMCs), it also limits transient overcurrents and overvoltages in vulnerable submodules. Modeling and control principles are outlined, and simulations under various fault conditions confirm that the CLCC both eliminates commutation failures and reduces MMC stress, enabling reliable FRT. These results highlight the CLCC’s potential to improve the resilience and engineering feasibility of future hybrid HVDC systems.
{"title":"Fault Ride-Through Strategy for Hybrid Cascaded HVdc Systems Based on Controllable LCC","authors":"Kang Liu;Baohong Li;Qin Jiang;Yingmin Zhang;Tianqi Liu","doi":"10.1109/TCSII.2025.3627209","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3627209","url":null,"abstract":"This brief proposes a fault ride-through (FRT) strategy for hybrid cascaded high-voltage direct current (HVDC) systems using a controllable line-commutated converter (CLCC). Unlike conventional LCCs prone to commutation failures during AC faults, the CLCC provides forced commutation and ensures stable operation. When combined with series-connected modular multilevel converters (MMCs), it also limits transient overcurrents and overvoltages in vulnerable submodules. Modeling and control principles are outlined, and simulations under various fault conditions confirm that the CLCC both eliminates commutation failures and reduces MMC stress, enabling reliable FRT. These results highlight the CLCC’s potential to improve the resilience and engineering feasibility of future hybrid HVDC systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"88-92"},"PeriodicalIF":4.9,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-14DOI: 10.1109/TCSII.2025.3621345
Philippe Bich;Luciano Prono;Chiara Boretti;Fabio Pareschi;Riccardo Rovatti;Gianluca Setti
Dynamic Vision Sensors (DVS) offer a unique advantage in capturing changes in luminance asynchronously, providing high temporal resolution and efficiency, making them particularly suitable for applications like egocentric vision and autonomous driving. However, adapting the sparse and asynchronous nature of DVS data for traditional non-recurrent deep learning models, such as convolutional neural networks (CNNs) and transformer-based architectures, poses challenges. In fact, classical methods, such as time surfaces and voxel grids, convert event-based data into a form suitable for frame-based Deep Neural Networks (DNNs). While effective, these methods often sacrifice the fine-grained temporal details intrinsic to DVS data, especially when requiring high throughput predictions. This can diminish the advantages of DVS in capturing fast-moving or transient phenomena. We aim to contribute addressing this issue and propose a dynamic pre-processing pipeline called Memory of Events through Spatial Attention (MESA), that enhances the currently used event-based data representations. This is obtained by storing events in a memory tensor with pixel-wise adaptive forgetting factors generated in real time through a spatial-attention module. Tested on multiple computer vision tasks, this method enhances the performance of state-of-the-art non-recurrent DNNs with minimal computational cost. In particular, by using MESA, the accuracy on CIFAR10-DVS with MobileViT-v2s improves by more than 15% and with DETR-ResNet50, the mAP on the PEDRo object detection dataset is three times higher than the baseline achieved with time surfaces alone. Furthermore, when estimating pupil position on the 3ET+ dataset using MobileNet-v3s, MESA reduces the Euclidean distance error by 36% compared to using time surfaces alone.
{"title":"MESA: A Dynamical Attention-Based Pre-Processing Pipeline for High-Throughput Event-Based Computer Vision Tasks","authors":"Philippe Bich;Luciano Prono;Chiara Boretti;Fabio Pareschi;Riccardo Rovatti;Gianluca Setti","doi":"10.1109/TCSII.2025.3621345","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3621345","url":null,"abstract":"Dynamic Vision Sensors (DVS) offer a unique advantage in capturing changes in luminance asynchronously, providing high temporal resolution and efficiency, making them particularly suitable for applications like egocentric vision and autonomous driving. However, adapting the sparse and asynchronous nature of DVS data for traditional non-recurrent deep learning models, such as convolutional neural networks (CNNs) and transformer-based architectures, poses challenges. In fact, classical methods, such as time surfaces and voxel grids, convert event-based data into a form suitable for frame-based Deep Neural Networks (DNNs). While effective, these methods often sacrifice the fine-grained temporal details intrinsic to DVS data, especially when requiring high throughput predictions. This can diminish the advantages of DVS in capturing fast-moving or transient phenomena. We aim to contribute addressing this issue and propose a dynamic pre-processing pipeline called <italic>Memory of Events through Spatial Attention</i> (MESA), that enhances the currently used event-based data representations. This is obtained by storing events in a memory tensor with pixel-wise adaptive forgetting factors generated in real time through a spatial-attention module. Tested on multiple computer vision tasks, this method enhances the performance of state-of-the-art non-recurrent DNNs with minimal computational cost. In particular, by using MESA, the accuracy on CIFAR10-DVS with MobileViT-v2s improves by more than 15% and with DETR-ResNet50, the mAP on the PEDRo object detection dataset is three times higher than the baseline achieved with time surfaces alone. Furthermore, when estimating pupil position on the 3ET+ dataset using MobileNet-v3s, MESA reduces the Euclidean distance error by 36% compared to using time surfaces alone.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 12","pages":"2057-2061"},"PeriodicalIF":4.9,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145595118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Backscatter (BackCom) communication using a cavity poses a significant challenge due to the bandpass filtering behavior of the cavity, which restricts the range of separation between uplink and downlink frequencies, potentially leading to self-jamming issues, requiring a high-sensitivity transceiver and a high quality-factor narrow-band filter. This brief proposes a new method for BackCom using a multimode rectangular cavity with dimensions of $49.6~text{cm} times 49.6~text{cm} times 30.4$ cm, which resonates at 427.5 MHz in TE011 mode and 570 MHz in TM110 mode. A double-sided square loop coil, sized $1.2~text{mm} times 1.2$ mm on an FR4 substrate, serves as the miniaturized device (MD) antenna for freely moving small animal implants. The MD integrates an on-chip circuit implemented in a $0.35~mu $ m CMOS technology, featuring a 5-stage differential rectifier with a power management unit and a low-power on-chip frequency generator. The frequency generator eliminates a power-hungry synthesizer by deriving the 142.5 MHz modulation signal from the 570 MHz downlink via frequency division. The multimode cavity as a reader receives an uplink signal of -20 dBm at 427.5 MHz in TE011 mode, with a downlink input power of 24 dBm at 570 MHz in TM110 mode applied to the cavity. This approach shows a sufficient separation of 142.5 MHz between the uplink and downlink modes, which eliminates self-jamming, relaxes filter requirements, and enables using the full cavity bandwidth for potentially higher data rates.
{"title":"Multimode Cavity Enabling Backscatter Communication for mm-Sized Implants in Freely Moving Animals","authors":"Natachai Terawatsakul;Alireza Saberkari;Atila Alvandpour","doi":"10.1109/TCSII.2025.3618660","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3618660","url":null,"abstract":"Backscatter (BackCom) communication using a cavity poses a significant challenge due to the bandpass filtering behavior of the cavity, which restricts the range of separation between uplink and downlink frequencies, potentially leading to self-jamming issues, requiring a high-sensitivity transceiver and a high quality-factor narrow-band filter. This brief proposes a new method for BackCom using a multimode rectangular cavity with dimensions of <inline-formula> <tex-math>$49.6~text{cm} times 49.6~text{cm} times 30.4$ </tex-math></inline-formula> cm, which resonates at 427.5 MHz in TE<sub>011</sub> mode and 570 MHz in TM<sub>110</sub> mode. A double-sided square loop coil, sized <inline-formula> <tex-math>$1.2~text{mm} times 1.2$ </tex-math></inline-formula> mm on an FR4 substrate, serves as the miniaturized device (MD) antenna for freely moving small animal implants. The MD integrates an on-chip circuit implemented in a <inline-formula> <tex-math>$0.35~mu $ </tex-math></inline-formula>m CMOS technology, featuring a 5-stage differential rectifier with a power management unit and a low-power on-chip frequency generator. The frequency generator eliminates a power-hungry synthesizer by deriving the 142.5 MHz modulation signal from the 570 MHz downlink via frequency division. The multimode cavity as a reader receives an uplink signal of -20 dBm at 427.5 MHz in TE<sub>011</sub> mode, with a downlink input power of 24 dBm at 570 MHz in TM<sub>110</sub> mode applied to the cavity. This approach shows a sufficient separation of 142.5 MHz between the uplink and downlink modes, which eliminates self-jamming, relaxes filter requirements, and enables using the full cavity bandwidth for potentially higher data rates.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1730-1734"},"PeriodicalIF":4.9,"publicationDate":"2025-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A closed-loop pole analysis (CLPA) method is presented for Miller-compensated multistage amplifiers. CLPA broadens design-oriented analysis by adopting an impedance-based point of view, directly relating T/(1+T) to closed-loop response, along with clear circuit design specifications ($text {g}_{text {m2}}$ , $text {R}_{text {o2}}$ , $text {C}_{text {p2}}$ and $text {g}_{text {m3}}$ ), offering intuitive and quantitative design insights. Specifically, CLPA modeling the inner Miller loop as a second-order RLC cell allows natural frequency and damping to be extracted from output impedance breakpoints. Leveraging this connection, a resonance control scalable single-Miller capacitor compensation (RCSMC) topology is developed. Measurement results in 28 nm CMOS show that a three-stage RCSMC amplifier achieves 124 dB DC gain, a 1.16 MHz gain-bandwidth product, and an FOM1 of 39,456 MHz$cdot $ pF/($mu $ W$cdot $ mm2) with a 200 pF load, while simulations of a four-stage RCSMC amplifier reach 120 dB gain and an FOM1 of 1,137,800 MHz$cdot $ pF/($mu $ W$cdot $ mm2) for a 64 nF load, demonstrating performance and scalability.
{"title":"Closed-Loop Pole Analysis via Output Impedance in Miller-Compensated Amplifiers","authors":"Haochang Zhi;Shaojie Xu;Jintao Li;Tong Zhou;Yun Li;Weiwei Shan;Wanyuan Qu","doi":"10.1109/TCSII.2025.3618605","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3618605","url":null,"abstract":"A closed-loop pole analysis (CLPA) method is presented for Miller-compensated multistage amplifiers. CLPA broadens design-oriented analysis by adopting an impedance-based point of view, directly relating T/(1+T) to closed-loop response, along with clear circuit design specifications (<inline-formula> <tex-math>$text {g}_{text {m2}}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$text {R}_{text {o2}}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$text {C}_{text {p2}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$text {g}_{text {m3}}$ </tex-math></inline-formula>), offering intuitive and quantitative design insights. Specifically, CLPA modeling the inner Miller loop as a second-order RLC cell allows natural frequency and damping to be extracted from output impedance breakpoints. Leveraging this connection, a resonance control scalable single-Miller capacitor compensation (RCSMC) topology is developed. Measurement results in 28 nm CMOS show that a three-stage RCSMC amplifier achieves 124 dB DC gain, a 1.16 MHz gain-bandwidth product, and an FOM<sub>1</sub> of 39,456 MHz<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>pF/(<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>mm<sup>2</sup>) with a 200 pF load, while simulations of a four-stage RCSMC amplifier reach 120 dB gain and an FOM<sub>1</sub> of 1,137,800 MHz<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>pF/(<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>mm<sup>2</sup>) for a 64 nF load, demonstrating performance and scalability.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1715-1719"},"PeriodicalIF":4.9,"publicationDate":"2025-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Boolean Satisfiability (SAT) based verification and Content Addressable Memory (CAM) based lookup operations contribute to the efficiency of network packet transmission. Although related In Memory Accelerators (IMAs) provide substantial computational acceleration, current implementations still face limitations: IMAs based on incomplete SAT-solving methods are unsuitable for verification tasks; IMAs that integrate verification and lookup functionality are rare. To overcome these limitations, we propose an IMA based on Static Random-Access Memory (SRAM) that integrates both complete SAT-solving capabilities and high-throughput lookup operations. In this work, clause satisfiability determination and backtracking operations are implemented for complete SAT solving. Meanwhile, the RWL-split 11T SRAM array with 144Kb capacity increased the throughput of CAM based lookup operations. The prototype has been fabricated using a 65nm process. The power consumption of approximately 19.3mW under a supply voltage of 1.1V and a working frequency of 100MHz. The experimental results are demonstrated. For solving SAT problems, this work achieves 100% solvability in the SATLIB benchmark. For lookup operations, it consumes 0.13 fJ/search/bit and 0.26 fJ/search/bit for binary and ternary CAM operations, respectively.
{"title":"A SRAM-Based In-Memory Accelerator Featuring Complete SAT Solving and CAM Operations for Efficient Network Transmission","authors":"Jinrong Zhou;Renlong Li;Yifeng Zhou;Qiaoyi Fu;Zhuojun Chen","doi":"10.1109/TCSII.2025.3616326","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3616326","url":null,"abstract":"Boolean Satisfiability (SAT) based verification and Content Addressable Memory (CAM) based lookup operations contribute to the efficiency of network packet transmission. Although related In Memory Accelerators (IMAs) provide substantial computational acceleration, current implementations still face limitations: IMAs based on incomplete SAT-solving methods are unsuitable for verification tasks; IMAs that integrate verification and lookup functionality are rare. To overcome these limitations, we propose an IMA based on Static Random-Access Memory (SRAM) that integrates both complete SAT-solving capabilities and high-throughput lookup operations. In this work, clause satisfiability determination and backtracking operations are implemented for complete SAT solving. Meanwhile, the RWL-split 11T SRAM array with 144Kb capacity increased the throughput of CAM based lookup operations. The prototype has been fabricated using a 65nm process. The power consumption of approximately 19.3mW under a supply voltage of 1.1V and a working frequency of 100MHz. The experimental results are demonstrated. For solving SAT problems, this work achieves 100% solvability in the SATLIB benchmark. For lookup operations, it consumes 0.13 fJ/search/bit and 0.26 fJ/search/bit for binary and ternary CAM operations, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1785-1789"},"PeriodicalIF":4.9,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-01DOI: 10.1109/TCSII.2025.3615935
Reza Badiei;Somayeh Timarchi;Alireza Zakaleh
The primary goals of neuromorphic engineering are to study, simulate, model, and implement neural behavior of the human brain. In this work, we propose a modified version of the original FitzHugh-Nagumo (FHN) neuron model in which the nonlinear term is replaced with a power-of-two-based approximation. The modification eliminates the need for multipliers, reducing hardware resource utilization while maintaining high fidelity in reproducing the dynamic behaviors of the original model. To validate the proposed model, we conduct dynamic behavior analysis, error evaluation, and network behavior simulation, demonstrating that it accurately reproduces the key characteristics of the FHN model with minimal error. An efficient digital hardware solution for implementing neurons optimized for large-scale Spiking Neural Networks (SNNs), leveraging resource-sharing techniques and pipelining strategies, is presented. The design is described using the VHSIC Hardware Description Language (VHDL), simulated and synthesized in Vivado, and implemented on a Xilinx Zynq Field-Programmable Gate Array (FPGA). Experimental results demonstrate that the proposed model achieves a normalized RMSE of 0.36, while utilizing only 0.38% of the available resources, including 0.27% of slice LUTs and 0.16% of registers. Additionally, it operates at a frequency of 255 MHz while consuming only 29 mW of power. Moreover, the FPGA implementation of our proposed model requires fewer resources and lower power consumption compared to previous works, while maintaining a comparable error rate.
{"title":"Low-Power Resource-Efficient FPGA Implementation of Modified FitzHugh–Nagumo Neuron for Spiking Neural Networks","authors":"Reza Badiei;Somayeh Timarchi;Alireza Zakaleh","doi":"10.1109/TCSII.2025.3615935","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3615935","url":null,"abstract":"The primary goals of neuromorphic engineering are to study, simulate, model, and implement neural behavior of the human brain. In this work, we propose a modified version of the original FitzHugh-Nagumo (FHN) neuron model in which the nonlinear term is replaced with a power-of-two-based approximation. The modification eliminates the need for multipliers, reducing hardware resource utilization while maintaining high fidelity in reproducing the dynamic behaviors of the original model. To validate the proposed model, we conduct dynamic behavior analysis, error evaluation, and network behavior simulation, demonstrating that it accurately reproduces the key characteristics of the FHN model with minimal error. An efficient digital hardware solution for implementing neurons optimized for large-scale Spiking Neural Networks (SNNs), leveraging resource-sharing techniques and pipelining strategies, is presented. The design is described using the VHSIC Hardware Description Language (VHDL), simulated and synthesized in Vivado, and implemented on a Xilinx Zynq Field-Programmable Gate Array (FPGA). Experimental results demonstrate that the proposed model achieves a normalized RMSE of 0.36, while utilizing only 0.38% of the available resources, including 0.27% of slice LUTs and 0.16% of registers. Additionally, it operates at a frequency of 255 MHz while consuming only 29 mW of power. Moreover, the FPGA implementation of our proposed model requires fewer resources and lower power consumption compared to previous works, while maintaining a comparable error rate.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1780-1784"},"PeriodicalIF":4.9,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-29DOI: 10.1109/TCSII.2025.3615635
Xianrui Dou;Huaguo Liang;Zhengfeng Huang;Yingchun Lu;Yue Wang;Tian Chen;Jun Liu
In the manufacturing process of integrated chips, numerous defects may occur in through-silicon vias (TSVs), which can affect the integrity of signals passing through the TSVs. Therefore, it is crucial to detect these defects in the early stages of production. Existing testing methods suffer from issues such as large testing areas and time overhead, as well as low testing accuracy. In this brief, an nMOS is selected as the gating device to reduce the area overhead of shared testing. A voltage comparator is employed to amplify the voltage difference between the TSV under test and a reference capacitor, enabling the detection of resistive open defects with $R_{text {open}} geq 39~{mathrm {Omega }}$ , leakage defects with $R_{text {leak}} leq 5~{mathrm {M}} {mathrm {Omega }}$ . Compared with other methods, this approach offers the advantages of high detection accuracy for resistive open defects and minimal testing area and time overhead.
{"title":"Prebond Test of TSV Based on Voltage Skew Amplification","authors":"Xianrui Dou;Huaguo Liang;Zhengfeng Huang;Yingchun Lu;Yue Wang;Tian Chen;Jun Liu","doi":"10.1109/TCSII.2025.3615635","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3615635","url":null,"abstract":"In the manufacturing process of integrated chips, numerous defects may occur in through-silicon vias (TSVs), which can affect the integrity of signals passing through the TSVs. Therefore, it is crucial to detect these defects in the early stages of production. Existing testing methods suffer from issues such as large testing areas and time overhead, as well as low testing accuracy. In this brief, an nMOS is selected as the gating device to reduce the area overhead of shared testing. A voltage comparator is employed to amplify the voltage difference between the TSV under test and a reference capacitor, enabling the detection of resistive open defects with <inline-formula> <tex-math>$R_{text {open}} geq 39~{mathrm {Omega }}$ </tex-math></inline-formula>, leakage defects with <inline-formula> <tex-math>$R_{text {leak}} leq 5~{mathrm {M}} {mathrm {Omega }}$ </tex-math></inline-formula>. Compared with other methods, this approach offers the advantages of high detection accuracy for resistive open defects and minimal testing area and time overhead.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1770-1774"},"PeriodicalIF":4.9,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-29DOI: 10.1109/TCSII.2025.3615850
Ruoyu Wu;Peng Liu
Ising machines, which leverage natural computing, exhibit exceptionally fast annealing and low energy consumption, positioning them as promising solutions for combinatorial optimization problems. In particular, CMOS-compatible Ising machines offer significant advantages due to their cost-effective fabrication and scalability. This brief proposes a novel CMOS-compatible continuous-time Ising machine that performs natural iteration and optimization based on physical properties through direct current comparison. The architecture and circuit design enable rapid updates of Ising nodes via interactions within a resistive array, providing real-time feedback to other nodes and facilitating efficient annealing. Simulations under 65 nm process demonstrate that, for a 100-node fully connected Max-Cut problem, our design requires only 20 ns of annealing time and 0.23 nJ of energy, while achieving an average accuracy of 96%. Compared to a state-of-the-art approach, our design reduces time to solution and energy consumption by $9times $ and $51times $ , respectively.
{"title":"Enhancing Efficiency in Continuous-Time Ising Machine Through Direct Current Comparison","authors":"Ruoyu Wu;Peng Liu","doi":"10.1109/TCSII.2025.3615850","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3615850","url":null,"abstract":"Ising machines, which leverage natural computing, exhibit exceptionally fast annealing and low energy consumption, positioning them as promising solutions for combinatorial optimization problems. In particular, CMOS-compatible Ising machines offer significant advantages due to their cost-effective fabrication and scalability. This brief proposes a novel CMOS-compatible continuous-time Ising machine that performs natural iteration and optimization based on physical properties through direct current comparison. The architecture and circuit design enable rapid updates of Ising nodes via interactions within a resistive array, providing real-time feedback to other nodes and facilitating efficient annealing. Simulations under 65 nm process demonstrate that, for a 100-node fully connected Max-Cut problem, our design requires only 20 ns of annealing time and 0.23 nJ of energy, while achieving an average accuracy of 96%. Compared to a state-of-the-art approach, our design reduces time to solution and energy consumption by <inline-formula> <tex-math>$9times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$51times $ </tex-math></inline-formula>, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1790-1794"},"PeriodicalIF":4.9,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-29DOI: 10.1109/TCSII.2025.3615737
L. Hemanth Krishna;B. Srinivasu;K. Sridharan
Arithmetic units in multivalued logic have been extensively researched in the last decade in the context of emerging nanodevices. While considerable work has been done on adder and multiplier designs, the focus has been on handling unsigned numbers. In this brief, we first present an algorithm for multiplication of a pair of signed ternary numbers represented in three’s complement format. The algorithm leads to partial product digits which are all positive. Using a special class of operators in ternary logic, we then present a hardware-efficient realization of the algorithm that leads to low multiplexer count. The special operators also contribute to power reduction. Technology assessment using Carbon Nanotube FET (CNTFET) reveals that the proposed multiplier achieves substantial reduction in power-delay product (PDP) over the best existing design. In particular, the savings in PDP for $6times 6$ and $36times 36$ multipliers are 32% and 38% respectively.
{"title":"Low Complexity Three’s Complement Parallel Multiplier Using Special Operators of Ternary Logic","authors":"L. Hemanth Krishna;B. Srinivasu;K. Sridharan","doi":"10.1109/TCSII.2025.3615737","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3615737","url":null,"abstract":"Arithmetic units in multivalued logic have been extensively researched in the last decade in the context of emerging nanodevices. While considerable work has been done on adder and multiplier designs, the focus has been on handling unsigned numbers. In this brief, we first present an algorithm for multiplication of a pair of <italic>signed ternary numbers represented in three’s complement format</i>. The algorithm leads to partial product digits which are all positive. Using a special class of operators in ternary logic, we then present a hardware-efficient realization of the algorithm that leads to low multiplexer count. The special operators also contribute to power reduction. Technology assessment using Carbon Nanotube FET (CNTFET) reveals that the proposed multiplier achieves substantial reduction in power-delay product (PDP) over the best existing design. In particular, the savings in PDP for <inline-formula> <tex-math>$6times 6$ </tex-math></inline-formula> and <inline-formula> <tex-math>$36times 36$ </tex-math></inline-formula> multipliers are 32% and 38% respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1775-1779"},"PeriodicalIF":4.9,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-26DOI: 10.1109/TCSII.2025.3614711
Yalin Zhang;Zhongxin Liu;Zengqiang Chen
Secondary control and the State-of-Charge (SoC) balance control are important control objectives for battery energy storage systems (BESSs). In this brief, a communication weight allocation method based on the centrality of eigenvectors is designed for a connected and directed graph, which results in the adjacency matrix having a given leading eigenvector. Subsequently, a distributed secondary voltage controller and an SoC balance controller are designed for droop-controlled BESSs to achieve voltage leader-following multiconsensus and SoC balance, respectively. It is worth mentioning that under the designed voltage secondary control scheme, only a single leader is needed to achieve voltage multiconsensus control. In addition, the capacity information/droop coefficient does not need to be transmitted in the communication network to achieve power sharing according to capacity and SoC balance. For SoC balance control, the control gain is also well analyzed to ensure stability. The relevant simulations verify the effectiveness of the designed scheme.
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