An area-efficient CMOS cross-coupled LC-VCO, operating from 5.74 GHz to 8.02 GHz and featuring a tail noise filter with two tail inductors integrated inside the main inductor, is presented for the first time. The tail noise filter comprised two nested intertwined tail inductors (NITIs) and a tail capacitor bank, effectively suppressing phase noise (PN) while generating negligible magnetic couplings between the main inductor and the NITIs. The proposed architecture enables area-efficient CMOS cross-coupled design, even with the two NITIs, but has no performance degradation, i.e., it eliminates the additional area for the tail noise filter. Implemented in 28-nm CMOS process, it consumed 11 mA current from 0.73 V power supply. The LC-VCO achieved PN of −116.38 dBc/Hz at 1 MHz offset frequency for an output frequency of 5.747 GHz. 37% and 27% reductions in silicon area were achieved, over the conventional LC-VCO and an LC-VCO using intertwined tail inductors (ITIs), respectively, without compromising on performance. The proposed design has the smallest area among state-of-the-art LC-VCOs that include a tail noise filter along with competitive PN and frequency tuning range (FTR).
{"title":"An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors","authors":"Hyogyoung An;Hyeonjun Nam;Sungjin Kim;Younghyun Lim;Heein Yoon","doi":"10.1109/TCSII.2024.3485921","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485921","url":null,"abstract":"An area-efficient CMOS cross-coupled LC-VCO, operating from 5.74 GHz to 8.02 GHz and featuring a tail noise filter with two tail inductors integrated inside the main inductor, is presented for the first time. The tail noise filter comprised two nested intertwined tail inductors (NITIs) and a tail capacitor bank, effectively suppressing phase noise (PN) while generating negligible magnetic couplings between the main inductor and the NITIs. The proposed architecture enables area-efficient CMOS cross-coupled design, even with the two NITIs, but has no performance degradation, i.e., it eliminates the additional area for the tail noise filter. Implemented in 28-nm CMOS process, it consumed 11 mA current from 0.73 V power supply. The LC-VCO achieved PN of −116.38 dBc/Hz at 1 MHz offset frequency for an output frequency of 5.747 GHz. 37% and 27% reductions in silicon area were achieved, over the conventional LC-VCO and an LC-VCO using intertwined tail inductors (ITIs), respectively, without compromising on performance. The proposed design has the smallest area among state-of-the-art LC-VCOs that include a tail noise filter along with competitive PN and frequency tuning range (FTR).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"143-147"},"PeriodicalIF":4.0,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-24DOI: 10.1109/TCSII.2024.3485649
Hongjie Zeng;Zemeng Huang;Tao Tan;Yubing Li;Xiuping Li
This brief presents a wideband low noise amplifier (LNA) at K-band. A parasitic-aware analysis focused on gain is proposed in the transformer feedback $g_{mathrm {m}}$ -boost common-gate (CG) stage. This analysis models parasitic components as grounded equivalents, decoupling the amplifier into active circuitry and passive components. It addresses the design challenges of wideband amplifiers with complex capacitive networks, offering a more accurate representation of the amplifier’s characteristics and providing valuable guidance for parasitic-sensitive designs. The designed amplifier consists of a gm-boost transformer feedback CG stage followed by a capacitor-neutralized common source (CS) stage. An adapted interstage matching network is developed to compensate for the unbalanced transimpedance, which contributes to a flat overall wideband gain with a low noise figure (NF). The input and output of the LNA are well-matched and the LNA achieves a maximum gain of 14.6 dB, 3-dB bandwidth of 9.5 GHz (19-28.5 GHz), a minimum NF of 2.3 dB, and an input 1-dB compression point (IP1dB) exceeding -10.3 dBm across 19-28.5 GHz. The proposed LNA is implemented in a 110-nm CMOS process, occupying a compact chip area of 0.258 mm2 and consuming 25.6 mW at a supply voltage of 1.2 V. To the best of our knowledge, this brief represents the first comprehensive, parasitic-aware gain analysis of the transformer feedback $g_{mathrm {m}}$ -boost CG stage.
{"title":"Parasitic-Aware Analysis and Design of a Wideband gm-Boost Low Noise Amplifier at K-Band","authors":"Hongjie Zeng;Zemeng Huang;Tao Tan;Yubing Li;Xiuping Li","doi":"10.1109/TCSII.2024.3485649","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485649","url":null,"abstract":"This brief presents a wideband low noise amplifier (LNA) at K-band. A parasitic-aware analysis focused on gain is proposed in the transformer feedback \u0000<inline-formula> <tex-math>$g_{mathrm {m}}$ </tex-math></inline-formula>\u0000-boost common-gate (CG) stage. This analysis models parasitic components as grounded equivalents, decoupling the amplifier into active circuitry and passive components. It addresses the design challenges of wideband amplifiers with complex capacitive networks, offering a more accurate representation of the amplifier’s characteristics and providing valuable guidance for parasitic-sensitive designs. The designed amplifier consists of a gm-boost transformer feedback CG stage followed by a capacitor-neutralized common source (CS) stage. An adapted interstage matching network is developed to compensate for the unbalanced transimpedance, which contributes to a flat overall wideband gain with a low noise figure (NF). The input and output of the LNA are well-matched and the LNA achieves a maximum gain of 14.6 dB, 3-dB bandwidth of 9.5 GHz (19-28.5 GHz), a minimum NF of 2.3 dB, and an input 1-dB compression point (IP1dB) exceeding -10.3 dBm across 19-28.5 GHz. The proposed LNA is implemented in a 110-nm CMOS process, occupying a compact chip area of 0.258 mm2 and consuming 25.6 mW at a supply voltage of 1.2 V. To the best of our knowledge, this brief represents the first comprehensive, parasitic-aware gain analysis of the transformer feedback \u0000<inline-formula> <tex-math>$g_{mathrm {m}}$ </tex-math></inline-formula>\u0000-boost CG stage.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"138-142"},"PeriodicalIF":4.0,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-23DOI: 10.1109/TCSII.2024.3485011
Yu-Chi Yen;Shen-Iuan Liu
A sub-sampling phase-locked loop (SSPLL) with foreground open-loop gain calibration is presented. By digitally adjusting the transconductance cell, the open-loop gain of the SSPLL is calibrated. This SSPLL is fabricated in 40 nm CMOS technology. Its active area is $0.167~{mathrm { mm}}^{2}$ and the power consumption is 14.08mW at 6.4 GHz for a supply of 1V. The root-mean-square (RMS) jitter is 59.6fs while the phase noise is integrated with the offset frequency from 1 kHz to 100MHz. The calculated figure of merit is −253dB. With the calibration, the maximal deviation of the loop bandwidth is reduced from −41.5% to −7.3% for the supply voltage of 0.9V~1.1V. The maximal deviation of the RMS jitter is reduced from 23.6% to 4.7%. For five chips, the maximal deviation of the loop bandwidth is reduced from −34.9% to 4% with calibration. And the maximal deviation of the RMS jitter is reduced from 10.9% to −3.4%.
{"title":"A 59.6fsrms Jitter Sub-Sampling PLL With Foreground Open-Loop Gain Calibration","authors":"Yu-Chi Yen;Shen-Iuan Liu","doi":"10.1109/TCSII.2024.3485011","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485011","url":null,"abstract":"A sub-sampling phase-locked loop (SSPLL) with foreground open-loop gain calibration is presented. By digitally adjusting the transconductance cell, the open-loop gain of the SSPLL is calibrated. This SSPLL is fabricated in 40 nm CMOS technology. Its active area is \u0000<inline-formula> <tex-math>$0.167~{mathrm { mm}}^{2}$ </tex-math></inline-formula>\u0000 and the power consumption is 14.08mW at 6.4 GHz for a supply of 1V. The root-mean-square (RMS) jitter is 59.6fs while the phase noise is integrated with the offset frequency from 1 kHz to 100MHz. The calculated figure of merit is −253dB. With the calibration, the maximal deviation of the loop bandwidth is reduced from −41.5% to −7.3% for the supply voltage of 0.9V~1.1V. The maximal deviation of the RMS jitter is reduced from 23.6% to 4.7%. For five chips, the maximal deviation of the loop bandwidth is reduced from −34.9% to 4% with calibration. And the maximal deviation of the RMS jitter is reduced from 10.9% to −3.4%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"73-77"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-23DOI: 10.1109/TCSII.2024.3485468
Mengxia He;S. C. Chan
Classical source number estimators are usually derived under the assumption of uniform white noise, which may degrade substantially with unknown nonuniform sensor noise. Advanced estimators designed for nonuniform noise are however computationally expensive with limited performance in unfavorable conditions, such as low signal-to-noise ratio, small number of snapshots, close angular separations and sources with different transmitter powers. This brief proposes a new likelihood ratio statistics-based method for source number estimation under uncorrelated nonuniform noise. Using the asymptotic theory, it is shown that the likelihood ratio follows a chi-square distribution. Hence, the number of sources can be estimated via a sequence of hypothesis tests using maximum likelihood estimators (MLEs) of the covariance matrix with different assumed source numbers. The low complexity subspace algorithm is proposed to obtain the ML estimates. Theoretical analysis demonstrates that the proposed estimator is consistent in the general asymptotic regime. Simulation results on 2D arrays such as uniform circular and L-shaped arrays show that the proposed estimator achieves a higher correct detection probability in unfavorable conditions and is more robust against nonuniformity of noise than state-of-the-art estimators.
{"title":"Source Number Estimation in 2D Uniform Circular and L-Shaped Arrays With Unknown Nonuniform Noise","authors":"Mengxia He;S. C. Chan","doi":"10.1109/TCSII.2024.3485468","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485468","url":null,"abstract":"Classical source number estimators are usually derived under the assumption of uniform white noise, which may degrade substantially with unknown nonuniform sensor noise. Advanced estimators designed for nonuniform noise are however computationally expensive with limited performance in unfavorable conditions, such as low signal-to-noise ratio, small number of snapshots, close angular separations and sources with different transmitter powers. This brief proposes a new likelihood ratio statistics-based method for source number estimation under uncorrelated nonuniform noise. Using the asymptotic theory, it is shown that the likelihood ratio follows a chi-square distribution. Hence, the number of sources can be estimated via a sequence of hypothesis tests using maximum likelihood estimators (MLEs) of the covariance matrix with different assumed source numbers. The low complexity subspace algorithm is proposed to obtain the ML estimates. Theoretical analysis demonstrates that the proposed estimator is consistent in the general asymptotic regime. Simulation results on 2D arrays such as uniform circular and L-shaped arrays show that the proposed estimator achieves a higher correct detection probability in unfavorable conditions and is more robust against nonuniformity of noise than state-of-the-art estimators.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"348-352"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-23DOI: 10.1109/TCSII.2024.3485493
Akash Dev Roshan;Prithwijit Guha;Gaurav Trivedi
The sigmoid and $hyperbolic tangent~(tanh)$ functions are widely recognized as the most commonly employed nonlinear activation functions in artificial neural networks. These functions incorporate exponential terms to introduce nonlinearity, which imposes significant challenges when realized on hardware. This brief presents a novel approach for the hardware implementation of sigmoid and tanh functions, leveraging a regression tree and linear regression. The proposed method divides their nonlinear region into small segments using a regression tree. These segments are further approximated using a linear regression technique, the line of best fit. Experimental results demonstrate the average errors of $4times 10^{-4}$ and $9times 10^{-4}$ of sigmoid and tanh functions compared to exact functions. The above functions produce 24.52% and 35.71% less average error than the best contemporary method when implemented on the hardware. Additionally, the hardware implementations of sigmoid and tanh functions are more area, power and delay efficient, showcasing the effectiveness of this method compared to other state-of-the-art designs.
{"title":"Hardware-Optimized Regression Tree-Based Sigmoid and Tanh Functions for Machine Learning Applications","authors":"Akash Dev Roshan;Prithwijit Guha;Gaurav Trivedi","doi":"10.1109/TCSII.2024.3485493","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485493","url":null,"abstract":"The sigmoid and \u0000<inline-formula> <tex-math>$hyperbolic tangent~(tanh)$ </tex-math></inline-formula>\u0000 functions are widely recognized as the most commonly employed nonlinear activation functions in artificial neural networks. These functions incorporate exponential terms to introduce nonlinearity, which imposes significant challenges when realized on hardware. This brief presents a novel approach for the hardware implementation of sigmoid and tanh functions, leveraging a regression tree and linear regression. The proposed method divides their nonlinear region into small segments using a regression tree. These segments are further approximated using a linear regression technique, the line of best fit. Experimental results demonstrate the average errors of \u0000<inline-formula> <tex-math>$4times 10^{-4}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$9times 10^{-4}$ </tex-math></inline-formula>\u0000 of sigmoid and tanh functions compared to exact functions. The above functions produce 24.52% and 35.71% less average error than the best contemporary method when implemented on the hardware. Additionally, the hardware implementations of sigmoid and tanh functions are more area, power and delay efficient, showcasing the effectiveness of this method compared to other state-of-the-art designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"283-287"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Spiking neural network (SNN) based mixed-signal neuromorphic hardware gives high benefit in terms of speed and energy efficiency compared to conventional computing platform, thanks to its energy efficient data processing nature. However, on-chip realization of Poisson spike train to represent spike-encoded data has not yet fully achieved. Furthermore, the analog circuit components in mixed-signal neuromorphic hardwares are prone to variations which might lead to accuracy drop in SNN applications. In this brief, we demonstrated robust noise induced spike pulse generator for on-chip realization of Poisson spike train. The stochastic sigmoid neuron developed in our work exhibits better robustness than LIF neurons towards diverse RRAM device variation factors: 1) Random Telegraph Noise (RTN), 2) Stuck-At-Faults (SAFs) and 3) Endurance failures, guaranteeing robust SNN application.
{"title":"All Stochastic-Spiking Neural Network (AS-SNN): Noise Induced Spike Pulse Generator for Input and Output Neurons With Resistive Synaptic Array","authors":"Honggu Kim;Yerim An;Minchul Kim;Gyeong-Chan Heo;Yong Shim","doi":"10.1109/TCSII.2024.3485178","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485178","url":null,"abstract":"Spiking neural network (SNN) based mixed-signal neuromorphic hardware gives high benefit in terms of speed and energy efficiency compared to conventional computing platform, thanks to its energy efficient data processing nature. However, on-chip realization of Poisson spike train to represent spike-encoded data has not yet fully achieved. Furthermore, the analog circuit components in mixed-signal neuromorphic hardwares are prone to variations which might lead to accuracy drop in SNN applications. In this brief, we demonstrated robust noise induced spike pulse generator for on-chip realization of Poisson spike train. The stochastic sigmoid neuron developed in our work exhibits better robustness than LIF neurons towards diverse RRAM device variation factors: 1) Random Telegraph Noise (RTN), 2) Stuck-At-Faults (SAFs) and 3) Endurance failures, guaranteeing robust SNN application.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"78-82"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief proposes a temperature-compensated Ku-band eight-element four-beam phased-array receiver with low attenuation and relative phase variations. By properly adjusting the gate voltage of the switch MOSFETs in the 6-bit step attenuator, the resistance of MOSFETs can remain constant with temperature variation. Furthermore, the attenuation and relative phase errors caused by ambient temperature variations can be effectively decreased to meet the requirements of phased-array systems. To verify the proposed method, an eight-element 10.7–12.7 GHz phased-array receiver is designed and fabricated using a 130-nm silicon-germanium (SiGe) BiCMOS process. With the help of minimized attenuation and phase variations, the phased-array receiver exhibits a root-mean-square (RMS) attenuation error less than 0.71 dB and a RMS relative phase error less than 2.7° from −40°C to 85°C at 10.7-12.7 GHz. Meanwhile, the measured noise figure (NF) and single-channel gain are 1.1-2.5 dB and 21.2-27.8 dB, respectively.
{"title":"A Temperature-Compensated Ku-Band Four-Beam Phased-Array Receiver With Low Attenuation and Relative Phase Variations","authors":"Shi Chao Jin;Jiaxing Sun;Zhuoheng Xie;Bo Huang;Dunge Liu;Yuqian Yang;Chenyu Mei;Jun Huang;Chenyu Wang;Xiulong Wu;Yu Jian Cheng","doi":"10.1109/TCSII.2024.3485476","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485476","url":null,"abstract":"This brief proposes a temperature-compensated Ku-band eight-element four-beam phased-array receiver with low attenuation and relative phase variations. By properly adjusting the gate voltage of the switch MOSFETs in the 6-bit step attenuator, the resistance of MOSFETs can remain constant with temperature variation. Furthermore, the attenuation and relative phase errors caused by ambient temperature variations can be effectively decreased to meet the requirements of phased-array systems. To verify the proposed method, an eight-element 10.7–12.7 GHz phased-array receiver is designed and fabricated using a 130-nm silicon-germanium (SiGe) BiCMOS process. With the help of minimized attenuation and phase variations, the phased-array receiver exhibits a root-mean-square (RMS) attenuation error less than 0.71 dB and a RMS relative phase error less than 2.7° from −40°C to 85°C at 10.7-12.7 GHz. Meanwhile, the measured noise figure (NF) and single-channel gain are 1.1-2.5 dB and 21.2-27.8 dB, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"83-87"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-22DOI: 10.1109/TCSII.2024.3473488
Zongxiang Wang;Jixin Chen;Debin Hou;Peigen Zhou;Zhe Chen;Long Wang;Xiaojie Xu;Wei Hong
{"title":"Erratum to “A 1–27 GHz SiGe Low Noise Amplifier With 27-dB Peak Gain and 2.85±1. 45 dB NF”","authors":"Zongxiang Wang;Jixin Chen;Debin Hou;Peigen Zhou;Zhe Chen;Long Wang;Xiaojie Xu;Wei Hong","doi":"10.1109/TCSII.2024.3473488","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3473488","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"353-353"},"PeriodicalIF":4.0,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10729228","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-22DOI: 10.1109/TCSII.2024.3484453
Chaolai Da;Fang Li;Lifang Wang;Chengxuan Tao;Shufan Li;Ming Nie
A novel pulse synchronization scheme is proposed in this brief based on simultaneous wireless power and data transfer (SWPDT) technology to address the pulse synchronization issue of the undersea bidirectional wireless power transfer (BWPT) system due to the special characteristics of the undersea environment. Accurate pulse synchronization can be implemented by adapting the software to the existing SWPDT system based on the DDQ coil. Furthermore, this brief proposes a phase lock scheme that can eliminate the issue of pulse false triggering, which is caused by the interference of the BWPT channel to the data channel. A prototype with an output power of 1 kW and a data rate of 1 Mb/s demonstrates the feasibility of the pulse synchronization scheme proposed in this brief. The work of this brief extends the application of SWPDT technology and also presents a new solution for pulse synchronization in the BWPT system.
{"title":"Pulse Synchronization Scheme for Undersea BWPT System Based on Simultaneous Wireless Power and Data Transfer Technology","authors":"Chaolai Da;Fang Li;Lifang Wang;Chengxuan Tao;Shufan Li;Ming Nie","doi":"10.1109/TCSII.2024.3484453","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3484453","url":null,"abstract":"A novel pulse synchronization scheme is proposed in this brief based on simultaneous wireless power and data transfer (SWPDT) technology to address the pulse synchronization issue of the undersea bidirectional wireless power transfer (BWPT) system due to the special characteristics of the undersea environment. Accurate pulse synchronization can be implemented by adapting the software to the existing SWPDT system based on the DDQ coil. Furthermore, this brief proposes a phase lock scheme that can eliminate the issue of pulse false triggering, which is caused by the interference of the BWPT channel to the data channel. A prototype with an output power of 1 kW and a data rate of 1 Mb/s demonstrates the feasibility of the pulse synchronization scheme proposed in this brief. The work of this brief extends the application of SWPDT technology and also presents a new solution for pulse synchronization in the BWPT system.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"333-337"},"PeriodicalIF":4.0,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A peak-valley current-mode (PVCM) Buck converter is presented to extend the duty cycle range. Compared with traditional single inductor current-controlled converters, the PVCM Buck converter employs both the peak inductor current (PIC) and the valley inductor current (VIC) to precisely regulate the output voltage. Additionally, the converter features a voltage-controlled delay circuit, to enable active adjustment of operating frequency and to extend the duty cycle range. The proposed converter is implemented using a $0.18mu $ m BCD process. Experimental results demonstrate that the prototype achieves the 3% to 95% duty cycle range with a peak efficiency of 92%.
{"title":"A Peak-Valley Current-Mode Buck Converter With 3% to 95% Duty Cycle","authors":"Zhong Zhao;Ping Luo;Zhiyuan Zhang;Jiahang Fan;Bo Zhang;Xiaowen Chen","doi":"10.1109/TCSII.2024.3484449","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3484449","url":null,"abstract":"A peak-valley current-mode (PVCM) Buck converter is presented to extend the duty cycle range. Compared with traditional single inductor current-controlled converters, the PVCM Buck converter employs both the peak inductor current (PIC) and the valley inductor current (VIC) to precisely regulate the output voltage. Additionally, the converter features a voltage-controlled delay circuit, to enable active adjustment of operating frequency and to extend the duty cycle range. The proposed converter is implemented using a \u0000<inline-formula> <tex-math>$0.18mu $ </tex-math></inline-formula>\u0000m BCD process. Experimental results demonstrate that the prototype achieves the 3% to 95% duty cycle range with a peak efficiency of 92%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"328-332"},"PeriodicalIF":4.0,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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