Pub Date : 2024-12-24DOI: 10.1109/TCSII.2024.3513175
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3513175","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3513175","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10814107","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-23DOI: 10.1109/TCSII.2024.3521444
Sizhen Li;Yuhao Qiu;Kai Yu;Mo Huang
This brief proposes a sub-nW PMOS-only voltage reference (VR) for low-power application. The proposed VR uses a 2-transitor (2-T) pre-regulation (PR) circuit to supply a 2-T core circuit for reducing the dependence of the reference voltage $(V_{mathrm { REF}})$ on the supply voltage $(V_{mathrm { DD}})$ . Both the core and the PR circuit are biased by the leakage current of the PMOS transistors. Gate and bulk feedback are utilized in the PR circuit to further improve the line sensitivity (LS) and the power supply rejection ratio (PSRR) without any other extra transistors. The proposed design is fabricated in the standard 0.18-$mu $ m CMOS process, while 7 samples have been measured. The design can generate a $V_{mathrm { REF}}$ of 235.6 mV and consume a supply current of 0.31 nA under a minimum $V_{mathrm { DD}}$ of 0.45 V at 25°C. The PSRRs measured at frequencies of 100 Hz and 1 kHz are −77 dB and −72 dB respectively. Moreover, the average LS is 0.033%/V when the $V_{mathrm { DD}}$ varies from 0.45 V to 1.8 V. The average temperature coefficient (TC) is 66.3 ppm/°C without trimming over the temperature range of −40°C to 85°C. The minimum power consumption is 140 pW, and the chip area is only 0.0007 mm2.
{"title":"A 140 pW, –77 dB PSRR, PMOS-Only Voltage Reference Using Pre-Regulation Technique With Gate and Bulk Feedback","authors":"Sizhen Li;Yuhao Qiu;Kai Yu;Mo Huang","doi":"10.1109/TCSII.2024.3521444","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3521444","url":null,"abstract":"This brief proposes a sub-nW PMOS-only voltage reference (VR) for low-power application. The proposed VR uses a 2-transitor (2-T) pre-regulation (PR) circuit to supply a 2-T core circuit for reducing the dependence of the reference voltage <inline-formula> <tex-math>$(V_{mathrm { REF}})$ </tex-math></inline-formula> on the supply voltage <inline-formula> <tex-math>$(V_{mathrm { DD}})$ </tex-math></inline-formula>. Both the core and the PR circuit are biased by the leakage current of the PMOS transistors. Gate and bulk feedback are utilized in the PR circuit to further improve the line sensitivity (LS) and the power supply rejection ratio (PSRR) without any other extra transistors. The proposed design is fabricated in the standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process, while 7 samples have been measured. The design can generate a <inline-formula> <tex-math>$V_{mathrm { REF}}$ </tex-math></inline-formula> of 235.6 mV and consume a supply current of 0.31 nA under a minimum <inline-formula> <tex-math>$V_{mathrm { DD}}$ </tex-math></inline-formula> of 0.45 V at 25°C. The PSRRs measured at frequencies of 100 Hz and 1 kHz are −77 dB and −72 dB respectively. Moreover, the average LS is 0.033%/V when the <inline-formula> <tex-math>$V_{mathrm { DD}}$ </tex-math></inline-formula> varies from 0.45 V to 1.8 V. The average temperature coefficient (TC) is 66.3 ppm/°C without trimming over the temperature range of −40°C to 85°C. The minimum power consumption is 140 pW, and the chip area is only 0.0007 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"379-383"},"PeriodicalIF":4.0,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-23DOI: 10.1109/TCSII.2024.3521081
Ayyappadas Rajagopal;Shaikshavali Chitraganti
This brief presents a development of a real-time hardware-in-the-loop system using software-defined radios to emulate multi-sensor networked control systems (NCS) under real-world conditions. Also, a dedicated estimation algorithm for NCS using binary phase shift keying modulation, addressing signal-to-noise ratio constraints and channel characteristics from a sensor fusion perspective is addressed. This system supports remote placement of modules like sensors, estimators, and controllers interconnected via wireless channels, enabling distributed operation. This brief experimentally evaluates two scenarios: one involving a single measurement and the other utilizing a fusion-based approach. The proposed system, acting as a testbed helps in system evaluation before deployment.
{"title":"A Real-Time Hardware-in-the-Loop System Incorporating Software Defined Radios for Emulating Multi-Sensor Networked Control Systems","authors":"Ayyappadas Rajagopal;Shaikshavali Chitraganti","doi":"10.1109/TCSII.2024.3521081","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3521081","url":null,"abstract":"This brief presents a development of a real-time hardware-in-the-loop system using software-defined radios to emulate multi-sensor networked control systems (NCS) under real-world conditions. Also, a dedicated estimation algorithm for NCS using binary phase shift keying modulation, addressing signal-to-noise ratio constraints and channel characteristics from a sensor fusion perspective is addressed. This system supports remote placement of modules like sensors, estimators, and controllers interconnected via wireless channels, enabling distributed operation. This brief experimentally evaluates two scenarios: one involving a single measurement and the other utilizing a fusion-based approach. The proposed system, acting as a testbed helps in system evaluation before deployment.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"409-413"},"PeriodicalIF":4.0,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-19DOI: 10.1109/TCSII.2024.3520144
Tao Zhang;Haohui Chen;Weihong Lu;Qijun Lu;Xiangkun Yin;Xin An;Bei Liu;Zhangming Zhu
A wideband, compact, digitally-assisted variable gain phase shifter (VGPS) in a 65-nm CMOS process is presented for Ka-band applications. A digitally-assisted variable gain amplifier (VGA) architecture with a wide gain-control dynamic range and minimal input/output impedance variations is proposed by combining bias and digital control. Using only a one-stage digitally-assisted VGA, the VGPS achieves orthogonal phase and gain control with low RMS gain and phase errors in a compact size. Theoretical analysis is explored to provide physical insight into the working mechanism of the VGPS. In this design, the proposed VGPS leverages 3 bits for 18-dB gain tuning and 4 bits for 360° phase control. Measurements show that the VGPS exhibits an average peak gain of 0.6 dB at 28.4 GHz with a 3-dB bandwidth from 25.4 to 35.6 GHz. The measured RMS gain and phase errors is below 0.37 dB and 3°, respectively, from 25.4 to 34 GHz. It is implemented in a 65-nm CMOS process with the core area of $0.19~{mathrm { mm}}^{2}$ excluding the pads.
{"title":"A Wideband Compact Digitally-Assisted Variable Gain Phase Shifter for Ka-Band Applications","authors":"Tao Zhang;Haohui Chen;Weihong Lu;Qijun Lu;Xiangkun Yin;Xin An;Bei Liu;Zhangming Zhu","doi":"10.1109/TCSII.2024.3520144","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3520144","url":null,"abstract":"A wideband, compact, digitally-assisted variable gain phase shifter (VGPS) in a 65-nm CMOS process is presented for Ka-band applications. A digitally-assisted variable gain amplifier (VGA) architecture with a wide gain-control dynamic range and minimal input/output impedance variations is proposed by combining bias and digital control. Using only a one-stage digitally-assisted VGA, the VGPS achieves orthogonal phase and gain control with low RMS gain and phase errors in a compact size. Theoretical analysis is explored to provide physical insight into the working mechanism of the VGPS. In this design, the proposed VGPS leverages 3 bits for 18-dB gain tuning and 4 bits for 360° phase control. Measurements show that the VGPS exhibits an average peak gain of 0.6 dB at 28.4 GHz with a 3-dB bandwidth from 25.4 to 35.6 GHz. The measured RMS gain and phase errors is below 0.37 dB and 3°, respectively, from 25.4 to 34 GHz. It is implemented in a 65-nm CMOS process with the core area of <inline-formula> <tex-math>$0.19~{mathrm { mm}}^{2}$ </tex-math></inline-formula> excluding the pads.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"404-408"},"PeriodicalIF":4.0,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief validates in silicon a four-channel non-return-to-zero (NRZ) output-overlapped (OO) time-interleaving (TI) digital-to-analog converter (DAC) for the first time. The proposed 4-ch TI DAC achieves a sampling rate (Fs) of 16-GS/s, with each sub-DAC operating at a speed of only Fs/4. Compared with conventional RZ structures, the proposed structure uses fewer clocks and avoids the use of high-speed clocks. Additionally, the output-overlapping design reduces DAC’s sensitivity to duty-cycle mismatches. The DAC was fabricated in 28nm CMOS, incorporating a low-complexity phase error correction (PEC) unit to ensure precise phase alignment for the sub-DACs. Experimental results demonstrate that this DAC achieves a spurious-free dynamic range (SFDR) of >60dBc (>40dBc) up to 2.3GHz (5.4GHz), representing a significant advancement over the state-of-the-art solutions within the 2.3GHz frequency range of interest.
{"title":"A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving","authors":"Sihao Chen;Chengyu Huang;Limeng Sun;Yang Liu;Wenjun Tang;Jiaxuan Fan;Nan Sun;Yong Chen;Huazhong Yang;Xueqing Li","doi":"10.1109/TCSII.2024.3518084","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3518084","url":null,"abstract":"This brief validates in silicon a four-channel non-return-to-zero (NRZ) output-overlapped (OO) time-interleaving (TI) digital-to-analog converter (DAC) for the first time. The proposed 4-ch TI DAC achieves a sampling rate (Fs) of 16-GS/s, with each sub-DAC operating at a speed of only Fs/4. Compared with conventional RZ structures, the proposed structure uses fewer clocks and avoids the use of high-speed clocks. Additionally, the output-overlapping design reduces DAC’s sensitivity to duty-cycle mismatches. The DAC was fabricated in 28nm CMOS, incorporating a low-complexity phase error correction (PEC) unit to ensure precise phase alignment for the sub-DACs. Experimental results demonstrate that this DAC achieves a spurious-free dynamic range (SFDR) of >60dBc (>40dBc) up to 2.3GHz (5.4GHz), representing a significant advancement over the state-of-the-art solutions within the 2.3GHz frequency range of interest.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"374-378"},"PeriodicalIF":4.0,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief introduces a time gap sense amplifier (TGSA) to address the challenges of managing thousands of sense amplifiers (SAs) for next-generation high-bandwidth memory (HBM). The TGSA converts two reference voltages and data into the time domain, making decisions by detecting the time gaps between them. This approach enhances robustness to inherent mismatches of SA and reference voltage error without significantly increasing transistor size. In addition, a 20-stacked through-silicon via (TSV) channel is emulated to follow the stack height trend and achieve accurate modeling by removing a direct connection to the silicon substrate. The prototype receiver (RX) and the emulated TSV channel are fabricated in a 28 nm CMOS process, occupying 87.7 um2, and 0.029 mm2, respectively. The RX achieves a data rate of 10 Gb/s at a 0.8 V supply voltage (VDD) with a power consumption of 0.64 mW, resulting in an energy efficiency of 0.064 pJ/b and 0.018 pJ/b/pF.
{"title":"A 10 Gb/s Single-Ended Receiver Using Time Gap Sense Amplifier for Next-Generation HBM","authors":"Taehwan Kim;Changmin Sim;Seungwoo Park;Jinwoo Park;Seongcheol Kim;Hwaseok Shin;Junseob So;Seon-Been Lee;Youngwook Kwon;Chulwoo Kim","doi":"10.1109/TCSII.2024.3514638","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3514638","url":null,"abstract":"This brief introduces a time gap sense amplifier (TGSA) to address the challenges of managing thousands of sense amplifiers (SAs) for next-generation high-bandwidth memory (HBM). The TGSA converts two reference voltages and data into the time domain, making decisions by detecting the time gaps between them. This approach enhances robustness to inherent mismatches of SA and reference voltage error without significantly increasing transistor size. In addition, a 20-stacked through-silicon via (TSV) channel is emulated to follow the stack height trend and achieve accurate modeling by removing a direct connection to the silicon substrate. The prototype receiver (RX) and the emulated TSV channel are fabricated in a 28 nm CMOS process, occupying 87.7 um2, and 0.029 mm2, respectively. The RX achieves a data rate of 10 Gb/s at a 0.8 V supply voltage (VDD) with a power consumption of 0.64 mW, resulting in an energy efficiency of 0.064 pJ/b and 0.018 pJ/b/pF.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"369-373"},"PeriodicalIF":4.0,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-29DOI: 10.1109/TCSII.2024.3508773
Jong-Won Park;Deok-Young Kim;Donggu Im
An inductor-less wideband LNA is designed for a 5G midband applications. The noise reduction technique is proposed to address the trade-off between input return loss $(S_{11})$ and noise figure (NF). The proposed structure combines self-cascode transistors and composite transistors to increase $g_{m}$ without consuming additional current, which can improve NF and linearity. In contrast to conventional noise cancellation techniques, the proposed technique improves the NF by reusing current without a path for noise cancellation. The proposed LNA is designed with a 0.13-$mu $ m CMOS process and measured. In experiments, the proposed LNA shows a power gain $(S_{21})$ of 21.5 dB over a 3dB bandwidth of $0.01sim 1$ .7 GHz, and $S_{11}$ is less than −10 dB over the range 0.01~2 GHz. Also minimum NF of proposed LNA is 1.1 dB. In case of the linearity, the proposed LNA shows an input-referred third-order intercept point (IIP3) of −7.5 - 2.3 dBm. The power consumption is 9.1 mW from a 1.3 V supply voltage and chip area is 0.18 mm2.
{"title":"A Broadband Gm-Boosted Active Feedback CMOS Low-Noise Amplifier for Low- and Mid-Band 5G Applications","authors":"Jong-Won Park;Deok-Young Kim;Donggu Im","doi":"10.1109/TCSII.2024.3508773","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3508773","url":null,"abstract":"An inductor-less wideband LNA is designed for a 5G midband applications. The noise reduction technique is proposed to address the trade-off between input return loss <inline-formula> <tex-math>$(S_{11})$ </tex-math></inline-formula> and noise figure (NF). The proposed structure combines self-cascode transistors and composite transistors to increase <inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula> without consuming additional current, which can improve NF and linearity. In contrast to conventional noise cancellation techniques, the proposed technique improves the NF by reusing current without a path for noise cancellation. The proposed LNA is designed with a 0.13-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process and measured. In experiments, the proposed LNA shows a power gain <inline-formula> <tex-math>$(S_{21})$ </tex-math></inline-formula> of 21.5 dB over a 3dB bandwidth of <inline-formula> <tex-math>$0.01sim 1$ </tex-math></inline-formula>.7 GHz, and <inline-formula> <tex-math>$S_{11}$ </tex-math></inline-formula> is less than −10 dB over the range 0.01~2 GHz. Also minimum NF of proposed LNA is 1.1 dB. In case of the linearity, the proposed LNA shows an input-referred third-order intercept point (IIP3) of −7.5 - 2.3 dBm. The power consumption is 9.1 mW from a 1.3 V supply voltage and chip area is 0.18 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"399-403"},"PeriodicalIF":4.0,"publicationDate":"2024-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/TCSII.2024.3507861
Yifu Guo;Zhongxiao Tian;Likai Shen;Hanbo Yu;Lei Qiu;Bingbing Yao
This brief presents a low power high resolution 1-bit quantization-based delta-sigma modulator (DSM). The DSM is designed based on a low-power folded-cascode (LP-FC) current-steering (CS) dynamic amplifier (DA), which has a wide output swing and high gain. A speed enhancement (SE) technique is proposed for LP-FC CS DA to reduce the power consumption further with little gain and noise penalty. Additionally, the proposed PVT-tracking technique (PVTT) compensates the PVT-variation of the output common-mode detection (CMD) circuit of DA with a low dropout regulator (LDO), improving the robustness of DA. The LDO’s output voltage tracks the PVT variations. The prototype DSM is fabricated in 180 nm CMOS technology. The DSM running at $f_{mathrm { S}}$ of 204.8 kHz achieves an SNDR/DR of 94.8/97.3 dB under 1.8 V power supply while consuming $9~mu $ W, translating into a DR-based Schreier figure of merit (FoMDR) of 176.9 dB.
{"title":"A 16-Bit 1.6-kS/s ΔΣ Modulator Based on Folded-Cascode Dynamic Amplifier With Speed Enhancement and PVT-Tracking Techniques","authors":"Yifu Guo;Zhongxiao Tian;Likai Shen;Hanbo Yu;Lei Qiu;Bingbing Yao","doi":"10.1109/TCSII.2024.3507861","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3507861","url":null,"abstract":"This brief presents a low power high resolution 1-bit quantization-based delta-sigma modulator (DSM). The DSM is designed based on a low-power folded-cascode (LP-FC) current-steering (CS) dynamic amplifier (DA), which has a wide output swing and high gain. A speed enhancement (SE) technique is proposed for LP-FC CS DA to reduce the power consumption further with little gain and noise penalty. Additionally, the proposed PVT-tracking technique (PVTT) compensates the PVT-variation of the output common-mode detection (CMD) circuit of DA with a low dropout regulator (LDO), improving the robustness of DA. The LDO’s output voltage tracks the PVT variations. The prototype DSM is fabricated in 180 nm CMOS technology. The DSM running at <inline-formula> <tex-math>$f_{mathrm { S}}$ </tex-math></inline-formula> of 204.8 kHz achieves an SNDR/DR of 94.8/97.3 dB under 1.8 V power supply while consuming <inline-formula> <tex-math>$9~mu $ </tex-math></inline-formula>W, translating into a DR-based Schreier figure of merit (FoMDR) of 176.9 dB.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"364-368"},"PeriodicalIF":4.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/TCSII.2024.3507175
Insu Han;Hanjung Lee;Seong-Mo Moon;Inchan Ju
This brief presents a dual power mode (DPM) Q/V-band SiGe HBT cascode power amplifier (PA) for emerging very low-earth-orbit (VLEO) satellite communication (SATCOM). A novel reconfigurable four-way Wilkinson power combiner balun (WPCB) is proposed, where built-in a collector-to-base (CB) junction of upper HBTs in a SiGe HBT cascode is reconfigured to either reverse- or forward-biased to support high power (HP) or low power (LP) modes of the PA, respectively. This DPM scheme neither requires any lossy series switch at the PA output nor dual power supplies, which improves PA efficiency at power back off (PBO) and reduces system complexity. The DPM PA prototype is fabricated in 0.13 $mu $ m SiGe HBT BiCMOS. For HP/LP modes, the PA attains measured peak output power (POUT) and peak power added efficiency (PAE) 23.3/18.7 dBm and 30.4/25.8% at 45.0 GHz, respectively, demonstrating its DPM capability. For HP/LP modes at 45 GHz, it delivers linear $P_{mathrm { OUT}}$ (PAVG) of 17.0/11.8 dBm with average PAE (PAEAVG) of 17.7/13.0% at 250MHz symbol rate DVB-S2X 64 ASPK modulation signal.
{"title":"A Dual Power Mode Q/V-Band SiGe HBT Cascode Power Amplifier With a Novel Reconfigurable Four-Way Wilkinson Power Combiner Balun","authors":"Insu Han;Hanjung Lee;Seong-Mo Moon;Inchan Ju","doi":"10.1109/TCSII.2024.3507175","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3507175","url":null,"abstract":"This brief presents a dual power mode (DPM) Q/V-band SiGe HBT cascode power amplifier (PA) for emerging very low-earth-orbit (VLEO) satellite communication (SATCOM). A novel reconfigurable four-way Wilkinson power combiner balun (WPCB) is proposed, where built-in a collector-to-base (CB) junction of upper HBTs in a SiGe HBT cascode is reconfigured to either reverse- or forward-biased to support high power (HP) or low power (LP) modes of the PA, respectively. This DPM scheme neither requires any lossy series switch at the PA output nor dual power supplies, which improves PA efficiency at power back off (PBO) and reduces system complexity. The DPM PA prototype is fabricated in 0.13 \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m SiGe HBT BiCMOS. For HP/LP modes, the PA attains measured peak output power (POUT) and peak power added efficiency (PAE) 23.3/18.7 dBm and 30.4/25.8% at 45.0 GHz, respectively, demonstrating its DPM capability. For HP/LP modes at 45 GHz, it delivers linear \u0000<inline-formula> <tex-math>$P_{mathrm { OUT}}$ </tex-math></inline-formula>\u0000 (PAVG) of 17.0/11.8 dBm with average PAE (PAEAVG) of 17.7/13.0% at 250MHz symbol rate DVB-S2X 64 ASPK modulation signal.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"168-172"},"PeriodicalIF":4.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TCSII.2024.3490935
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3490935","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3490935","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767316","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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