Pub Date : 2025-07-30DOI: 10.1109/TCSII.2025.3594199
Kyoungseok Song;Donggun Lee;Geunhaeng Lee;Yonghui Li;Tae Wook Kim
This brief presents an impulse radio-ultrawideband (IR-UWB) transmitter (Tx) that achieves high energy efficiency and data rate through a power-gating (PG) technique and hybrid modulation scheme. PG minimizes static power consumption by activating the digitally controlled oscillator (DCO) only during transmission. A hybrid modulation scheme combines frequency- shift keying (FSK) with digitalized multi pulse position modulation (D-MPPM) and pulse width modulation (PWM) to increase modulation order. Implemented in 6.5-8.5 GHz, the proposed PG-DCO Tx achieves a data rate of 2.54 Gbps with an energy efficiency of 1.22 pJ/bit, approaching the 1 pJ/bit energy-efficiency barrier for UWB transmitters.
{"title":"A 2.54 Gbps, 1.22 pJ/Bit, IR-UWB Transmitter With a Power-Gating Technique","authors":"Kyoungseok Song;Donggun Lee;Geunhaeng Lee;Yonghui Li;Tae Wook Kim","doi":"10.1109/TCSII.2025.3594199","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594199","url":null,"abstract":"This brief presents an impulse radio-ultrawideband (IR-UWB) transmitter (Tx) that achieves high energy efficiency and data rate through a power-gating (PG) technique and hybrid modulation scheme. PG minimizes static power consumption by activating the digitally controlled oscillator (DCO) only during transmission. A hybrid modulation scheme combines frequency- shift keying (FSK) with digitalized multi pulse position modulation (D-MPPM) and pulse width modulation (PWM) to increase modulation order. Implemented in 6.5-8.5 GHz, the proposed PG-DCO Tx achieves a data rate of 2.54 Gbps with an energy efficiency of 1.22 pJ/bit, approaching the 1 pJ/bit energy-efficiency barrier for UWB transmitters.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1208-1212"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-30DOI: 10.1109/TCSII.2025.3594027
Zonglin Ye;Hongyang Zhang;Yuxuan Sun;Xinlin Geng;Qian Xie;Shiheng Yang;Zheng Wang
A calibration-free fractional-N synthesizer is presented with octave tuning capability and low fractional spurs, which is fabricated using a 65-nm bulk CMOS process. The synthesizer is based on the harmonic-mixing (HM) architecture, featuring a unity gain for the quantization error transfer to achieve low fractional spur without any calibration. To support octave-tuning, a ring-oscilator(RO)-based first stage is utilized to save area with negligible jitter deterioration. Moreover, a variable sub-sampling ratio technique is employed to relax the tuning range requirement for the RO. The measurements demonstrate an octave-tuning synthesizer with −80.7 dBc fractional spur, 71.7% tuning range and −254.6 dB FoMT.
{"title":"A 6.8-14.4GHz Calibration-Free Fractional-N RO-Based Harmonic-Mixing Frequency Synthesizer Achieving −80.7dBc Fractional Spur","authors":"Zonglin Ye;Hongyang Zhang;Yuxuan Sun;Xinlin Geng;Qian Xie;Shiheng Yang;Zheng Wang","doi":"10.1109/TCSII.2025.3594027","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594027","url":null,"abstract":"A calibration-free fractional-N synthesizer is presented with octave tuning capability and low fractional spurs, which is fabricated using a 65-nm bulk CMOS process. The synthesizer is based on the harmonic-mixing (HM) architecture, featuring a unity gain for the quantization error transfer to achieve low fractional spur without any calibration. To support octave-tuning, a ring-oscilator(RO)-based first stage is utilized to save area with negligible jitter deterioration. Moreover, a variable sub-sampling ratio technique is employed to relax the tuning range requirement for the RO. The measurements demonstrate an octave-tuning synthesizer with −80.7 dBc fractional spur, 71.7% tuning range and −254.6 dB FoMT.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1183-1187"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-30DOI: 10.1109/TCSII.2025.3593898
Young-Ju Oh;Chan-Ho Lee;Jeong-Hun Kim;Hyeonho Park;Dowon Jeong;Sung-Wan Hong
This brief proposes a pseudo two-stage two-phase (P2S-2P) buck converter that enhances power efficiency by reducing current in the high-voltage (HV) domain, which has large parasitic components. In contrast, the low-voltage (LV) domain, which has small parasitic components, supplies the majority of the output current (IO) through two inductors that automatically balance their currents. The proposed converter achieves a peak efficiency of 91.7% at an input voltage (VIN) of 48V, an output voltage (VO) of 1V, and the IO of 1.5A. The chip was fabricated using a 180-nm BCD process.
{"title":"A 91.7% Peak-Efficiency 48V-to-1V Pseudo Two-Stage Two-Phase Hybrid Buck Converter","authors":"Young-Ju Oh;Chan-Ho Lee;Jeong-Hun Kim;Hyeonho Park;Dowon Jeong;Sung-Wan Hong","doi":"10.1109/TCSII.2025.3593898","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593898","url":null,"abstract":"This brief proposes a pseudo two-stage two-phase (P2S-2P) buck converter that enhances power efficiency by reducing current in the high-voltage (HV) domain, which has large parasitic components. In contrast, the low-voltage (LV) domain, which has small parasitic components, supplies the majority of the output current (IO) through two inductors that automatically balance their currents. The proposed converter achieves a peak efficiency of 91.7% at an input voltage (VIN) of 48V, an output voltage (VO) of 1V, and the IO of 1.5A. The chip was fabricated using a 180-nm BCD process.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1318-1322"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-30DOI: 10.1109/TCSII.2025.3589808
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3589808","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3589808","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11104808","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TCSII.2025.3593639
Xiao Yang;Hao Zhang;Guohua Zhou
Besides line frequency excitation, strong nonlinear crossing effect amongst three input/output ports exists in single-inductor dual-output (SIDO) boost power factor correction (PFC) converters, which leads to the occurrence of complex behaviors including slow-scale oscillation. In this brief, a nonlinear averaged model is derived to describe the nonlinear time-periodic coupling (NTPC) effect of the SIDO PFC converter, and importantly time-frequency characteristic representation method is proposed to obtain the analytical expression of periodic equilibrium solutions. Furthermore, two types of slow-scale oscillations are identified with the help of the loci movement of Floquet multipliers. It is shown that period-doubling bifurcation and Hopf bifurcation are responsible for type I alternating peak oscillation and type II discontinuous trajectory oscillation, respectively. Especially, Hopf bifurcation results in one incommensurable frequency component with respect to the line frequency, which explains the reason why the system enters one quasi-periodic orbit. Finally, these experimental results are given to verify the theoretical analysis. These above results are beneficial to guide circuit optimal design.
{"title":"Bifurcation Analysis of Slow-Scale Oscillation in SIDO Boost PFC Converter Using Time-Frequency Characteristic Representation Method","authors":"Xiao Yang;Hao Zhang;Guohua Zhou","doi":"10.1109/TCSII.2025.3593639","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593639","url":null,"abstract":"Besides line frequency excitation, strong nonlinear crossing effect amongst three input/output ports exists in single-inductor dual-output (SIDO) boost power factor correction (PFC) converters, which leads to the occurrence of complex behaviors including slow-scale oscillation. In this brief, a nonlinear averaged model is derived to describe the nonlinear time-periodic coupling (NTPC) effect of the SIDO PFC converter, and importantly time-frequency characteristic representation method is proposed to obtain the analytical expression of periodic equilibrium solutions. Furthermore, two types of slow-scale oscillations are identified with the help of the loci movement of Floquet multipliers. It is shown that period-doubling bifurcation and Hopf bifurcation are responsible for type I alternating peak oscillation and type II discontinuous trajectory oscillation, respectively. Especially, Hopf bifurcation results in one incommensurable frequency component with respect to the line frequency, which explains the reason why the system enters one quasi-periodic orbit. Finally, these experimental results are given to verify the theoretical analysis. These above results are beneficial to guide circuit optimal design.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1308-1312"},"PeriodicalIF":4.9,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Emerging low-altitude airspace economy has driven the development of high-resolution wireless sensors. Dedicated for the Ka-band monopulse radar applications, the design of a highly integrated 1T3R transceiver is detailed in this brief. The heterodyne transceiver incorporates full radio frequency (RF), intermediate frequency (IF) and local oscillator (LO) building blocks, supporting complete monopulse detection in azimuth and elevation. The calibration mode is introduced to enable system-level instant calibrations for enhanced detection accuracy. Dual injection style of the LO source facilitates the cascade of multiple chips for large-scale sensing systems. Fabricated in 65-nm CMOS technology and packaged with the wafer-level chip-scale packaging, the transceiver achieves the peak RX/TX gain of 18.4/33.2 dB across 32–36 GHz, with a minimum RX NF of 5.7 dB and peak saturated TX power of 15.6 dBm. The high integration level and flexible configuration of the transceiver make it suitable for Ka-band monopulse radar applications.
{"title":"A Ka-Band Fully Integrated CMOS 1T3R Transceiver for Monopulse Radar Applications","authors":"Peng Gu;Enqi Zheng;Xiaofei Liao;Hengzhi Wan;Chenyu Xu;Pengfei Diao;Huiqi Liu;Dixian Zhao","doi":"10.1109/TCSII.2025.3593382","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593382","url":null,"abstract":"Emerging low-altitude airspace economy has driven the development of high-resolution wireless sensors. Dedicated for the Ka-band monopulse radar applications, the design of a highly integrated 1T3R transceiver is detailed in this brief. The heterodyne transceiver incorporates full radio frequency (RF), intermediate frequency (IF) and local oscillator (LO) building blocks, supporting complete monopulse detection in azimuth and elevation. The calibration mode is introduced to enable system-level instant calibrations for enhanced detection accuracy. Dual injection style of the LO source facilitates the cascade of multiple chips for large-scale sensing systems. Fabricated in 65-nm CMOS technology and packaged with the wafer-level chip-scale packaging, the transceiver achieves the peak RX/TX gain of 18.4/33.2 dB across 32–36 GHz, with a minimum RX NF of 5.7 dB and peak saturated TX power of 15.6 dBm. The high integration level and flexible configuration of the transceiver make it suitable for Ka-band monopulse radar applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1178-1182"},"PeriodicalIF":4.9,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
HBM (high bandwidth memory) is an emerging technology for high performance computing, but it has a different structure from traditional memory, and thus a new solution is needed. In this brief, we present an ECC (error correcting code) configuration method for SWD (sub-wordline driver) fault correction in the two-tiered ECC structure of HBM. Existing method does not have the correction capability to cover the entire range of a SWD cluster fault. In this brief, the SWD fault correction capability of the proposed method is presented through mathematical inference. And the simulation results also showed the same correction capability as the inference. And it shows the result of reducing the overhead and latency of encoder and decoder hardware when compared to the existing method.
{"title":"A New Two-Tiered ECC Configuration Method for Cluster Error Correction in HBM Architecture","authors":"Jaeil Lim;Jaewon Chung;Donghun Jeong;Daegeun Jee;Euicheol Lim","doi":"10.1109/TCSII.2025.3593226","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593226","url":null,"abstract":"HBM (high bandwidth memory) is an emerging technology for high performance computing, but it has a different structure from traditional memory, and thus a new solution is needed. In this brief, we present an ECC (error correcting code) configuration method for SWD (sub-wordline driver) fault correction in the two-tiered ECC structure of HBM. Existing method does not have the correction capability to cover the entire range of a SWD cluster fault. In this brief, the SWD fault correction capability of the proposed method is presented through mathematical inference. And the simulation results also showed the same correction capability as the inference. And it shows the result of reducing the overhead and latency of encoder and decoder hardware when compared to the existing method.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1293-1297"},"PeriodicalIF":4.9,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-25DOI: 10.1109/TCSII.2025.3592482
Nan Jiang;Mohammad Elmi;Kambiz Moez
This brief presents a novel ultra-low-power (ULP) time-domain level-crossing (TD-LC) analog-to-digital converter (ADC) with an adaptive sampling rate. By integrating a non-uniform LC sampling technique, the proposed TD-LC ADC further reduces power consumption compared to conventional TD ADCs. A voltage-to-time converter (VTC) is employed to convert the input voltage signal into a time signal, which is then subtracted from a time signal generated by a digital-to-time converter (DTC), converting the digital output from the previous digital output. The time residue determines the necessary adjustment for the digital output. Consequently, the proposed TD-LC ADC achieves 6-bit resolution using only a 3-bit time-to-digital converter (TDC). Fabricated in TSMC’s 0.13-$mu $ m CMOS process, the proposed TD-LC ADC achieves SNDR of 35.4 dB and SFDR of 45.25 dB at 518.31 KHz of BW, and SNDR of 33.59 dB and SFDR of 39.66 dB at 2.07 MHz of BW. The minimum power consumption is 206 nW with a supply voltage of 0.5 V.
{"title":"An Ultra-Low-Power Time-Domain Level-Crossing ADC With Adaptive Sampling Rate","authors":"Nan Jiang;Mohammad Elmi;Kambiz Moez","doi":"10.1109/TCSII.2025.3592482","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3592482","url":null,"abstract":"This brief presents a novel ultra-low-power (ULP) time-domain level-crossing (TD-LC) analog-to-digital converter (ADC) with an adaptive sampling rate. By integrating a non-uniform LC sampling technique, the proposed TD-LC ADC further reduces power consumption compared to conventional TD ADCs. A voltage-to-time converter (VTC) is employed to convert the input voltage signal into a time signal, which is then subtracted from a time signal generated by a digital-to-time converter (DTC), converting the digital output from the previous digital output. The time residue determines the necessary adjustment for the digital output. Consequently, the proposed TD-LC ADC achieves 6-bit resolution using only a 3-bit time-to-digital converter (TDC). Fabricated in TSMC’s 0.13-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process, the proposed TD-LC ADC achieves SNDR of 35.4 dB and SFDR of 45.25 dB at 518.31 KHz of BW, and SNDR of 33.59 dB and SFDR of 39.66 dB at 2.07 MHz of BW. The minimum power consumption is 206 nW with a supply voltage of 0.5 V.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1173-1177"},"PeriodicalIF":4.9,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-25DOI: 10.1109/TCSII.2025.3592480
Nadeem Atif;Saquib Mazhar;Mohammed Ameen;Shaik Rafi Ahamed;M. K. Bhuyan
Semantic segmentation is a pixel-level visual recognition task widely used in autonomous driving. Attaining a decent trade-off between accuracy and speed is critically important for the effective physical deployment of networks on resource-constrained edge devices. Towards this challenging task, we propose an efficient basic block that is designed to leverage local, short-range, and long-range contextual information at different abstraction levels. We introduce a simple technique inside the basic block, called Iterative Context Embedding (ICE), to reinforce the short and long-range contextual details in an iterative fashion. Based on the resulting short and long-range ICE or SLICE module, we propose an ultra-lightweight network, called SLICENet. Our model is the fastest among the existing ultra-lightweight models while achieving a decent accuracy. Specifically, with only 0.3 million parameters, it achieves 69.1% mean IoUs on the cityscapes test set, making it the smallest model to achieve this accuracy. In addition, it achieves an inference speed of 224.8 frames per second (FPS) on the RTX 3090 with $512times 1024$ resolution. To achieve a power-efficient solution meant for battery-operated devices, we also deploy our model on Xilinx’s ZCU102 development board (Zync UltraScale+ MPSoC). Despite achieving an impressive performance, its power consumption is only 950 mW; significantly lower than GPU-based inferences. Our code will be shared at https://github.com/NadeemAtif-Alig/SLICENet.
{"title":"SLICENet: An FPGA-Based Efficient Semantic Segmentation Network for Edge Deployment","authors":"Nadeem Atif;Saquib Mazhar;Mohammed Ameen;Shaik Rafi Ahamed;M. K. Bhuyan","doi":"10.1109/TCSII.2025.3592480","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3592480","url":null,"abstract":"Semantic segmentation is a pixel-level visual recognition task widely used in autonomous driving. Attaining a decent trade-off between accuracy and speed is critically important for the effective physical deployment of networks on resource-constrained edge devices. Towards this challenging task, we propose an efficient basic block that is designed to leverage local, short-range, and long-range contextual information at different abstraction levels. We introduce a simple technique inside the basic block, called Iterative Context Embedding (ICE), to reinforce the short and long-range contextual details in an iterative fashion. Based on the resulting short and long-range ICE or SLICE module, we propose an ultra-lightweight network, called SLICENet. Our model is the fastest among the existing ultra-lightweight models while achieving a decent accuracy. Specifically, with only 0.3 million parameters, it achieves 69.1% mean IoUs on the cityscapes test set, making it the smallest model to achieve this accuracy. In addition, it achieves an inference speed of 224.8 frames per second (FPS) on the RTX 3090 with <inline-formula> <tex-math>$512times 1024$ </tex-math></inline-formula> resolution. To achieve a power-efficient solution meant for battery-operated devices, we also deploy our model on Xilinx’s ZCU102 development board (Zync UltraScale+ MPSoC). Despite achieving an impressive performance, its power consumption is only 950 mW; significantly lower than GPU-based inferences. Our code will be shared at <uri>https://github.com/NadeemAtif-Alig/SLICENet</uri>.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1338-1342"},"PeriodicalIF":4.9,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-24DOI: 10.1109/TCSII.2025.3592475
Chun-Tse Su;Chao-Yen Hsu;Tai-Cheng Lee
This brief presents a calibration-free 12-bit 1.5-GS/s pipelined ADC employing a merged sub-ADC quantization (MSAQ) technique. Building upon the conventional pipelined ADC architecture, the proposed technique can extend the amplification time, thereby relaxing the design of the inner-stage residue amplifier. A prototype ADC implemented in a 28-nm CMOS technology achieves an SFDR of 70.52 dB and an SNDR of 58.03 dB at a Nyquist input, while consuming 18.5 mW from a 1-V supply. It yields Schreier and Walden figure of merits (FoM) of 164.1 dB and 18.9 fJ/conv.-step, respectively.
{"title":"A Calibration-Free 12-Bit 1.5-GS/s Pipelined ADC With Merged Sub-ADC Quantization Technique","authors":"Chun-Tse Su;Chao-Yen Hsu;Tai-Cheng Lee","doi":"10.1109/TCSII.2025.3592475","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3592475","url":null,"abstract":"This brief presents a calibration-free 12-bit 1.5-GS/s pipelined ADC employing a merged sub-ADC quantization (MSAQ) technique. Building upon the conventional pipelined ADC architecture, the proposed technique can extend the amplification time, thereby relaxing the design of the inner-stage residue amplifier. A prototype ADC implemented in a 28-nm CMOS technology achieves an SFDR of 70.52 dB and an SNDR of 58.03 dB at a Nyquist input, while consuming 18.5 mW from a 1-V supply. It yields Schreier and Walden figure of merits (FoM) of 164.1 dB and 18.9 fJ/conv.-step, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1168-1172"},"PeriodicalIF":4.9,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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