Pub Date : 2024-09-09DOI: 10.1109/TCSII.2024.3456470
Geuntae Park;Seongil Yeo;Chanjung Park;Kunhee Cho
This brief describes a real-time built-in-resistance (BIR) compensation for a switching charger designed to achieve fast charging. The proposed BIR detection utilizes the ripple components of the switching charger, enabling the detection of the BIR information at every switching cycle. The proposed BIR compensation can continuously detect the BIR information, thereby allowing the battery to be charged in constant-current (CC) mode for almost the entire charging period. The proposed switching charger has been implemented in a $0.18~mu $ m CMOS process, occupying a die area of 0.205mm2. The switching charger with the proposed BIR detection can charge in CC mode up to 98%, with CC mode charging time occupying 92.7% of the total charging time. The total charging time is reduced by 38.8% compared to conventional charging architecture. A peak efficiency of 95% is achieved.
本简介介绍了一种用于开关充电器的实时内置电阻（BIR）补偿装置，旨在实现快速充电。所提出的 BIR 检测利用了开关充电器的纹波元件，从而能够在每个开关周期检测 BIR 信息。拟议的 BIR 补偿可持续检测 BIR 信息，从而使电池在几乎整个充电期间都能以恒流 (CC) 模式充电。建议的开关充电器已在 0.18~mu $ m CMOS 工艺中实现，芯片面积为 0.205mm2。采用 BIR 检测技术的开关充电器在 CC 模式下的充电率高达 98%，CC 模式充电时间占总充电时间的 92.7%。与传统充电结构相比，总充电时间缩短了 38.8%。峰值效率达到 95%。
{"title":"A Ripple-Based Real-Time Built-in-Resistance Compensation for Switching Battery Charger Achieving Fast Charging","authors":"Geuntae Park;Seongil Yeo;Chanjung Park;Kunhee Cho","doi":"10.1109/TCSII.2024.3456470","DOIUrl":"10.1109/TCSII.2024.3456470","url":null,"abstract":"This brief describes a real-time built-in-resistance (BIR) compensation for a switching charger designed to achieve fast charging. The proposed BIR detection utilizes the ripple components of the switching charger, enabling the detection of the BIR information at every switching cycle. The proposed BIR compensation can continuously detect the BIR information, thereby allowing the battery to be charged in constant-current (CC) mode for almost the entire charging period. The proposed switching charger has been implemented in a \u0000<inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>\u0000m CMOS process, occupying a die area of 0.205mm2. The switching charger with the proposed BIR detection can charge in CC mode up to 98%, with CC mode charging time occupying 92.7% of the total charging time. The total charging time is reduced by 38.8% compared to conventional charging architecture. A peak efficiency of 95% is achieved.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4698-4702"},"PeriodicalIF":4.0,"publicationDate":"2024-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-05DOI: 10.1109/TCSII.2024.3442051
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3442051","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3442051","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 9","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10666915","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-05DOI: 10.1109/TCSII.2024.3454929
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TCSII.2024.3454929","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3454929","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 9","pages":"4406-4406"},"PeriodicalIF":4.0,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10666942","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-05DOI: 10.1109/TCSII.2024.3442053
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3442053","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3442053","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 9","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10666891","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-04DOI: 10.1109/TCSII.2024.3454348
Heungsik Eum;Kofi A. A. Makinwa;Inhee Lee;Youngcheol Chae
This brief presents a capacitively-biased CMOS voltage reference, which can operate from a sub-1V supply while achieving a low temperature coefficient (TC) and a competitive power-supply rejection ratio (PSRR). The reference voltage is generated by a capacitive bias circuit that provides a well-defined proportional-to-absolute-temperature (PTAT) bias current for a $Delta $ Vth type reference that consists of two stacked MOSFETs with different threshold voltages. The generated output voltage is sampled by an auto-zeroed (AZ) buffer, which can drive capacitive loads up to 2 nF. Fabricated in a 65 nm CMOS process, the prototype voltage reference occupies 0.058 mm2, including the AZ buffer and an on-chip timing generator. It outputs a reference voltage of 204.1 mV with a minimum supply voltage of 0.7 V. It achieves a TC of 18 ppm/°C from $- 40~^{circ }$ C to $85~^{circ }$ C and a PSRR of −75 dB at 100 Hz with only $200~mu $ V ripple.
{"title":"A Sub-1-V Capacitively-Biased Voltage Reference With an Auto-Zeroed Buffer and a TC of 18-ppm/°C","authors":"Heungsik Eum;Kofi A. A. Makinwa;Inhee Lee;Youngcheol Chae","doi":"10.1109/TCSII.2024.3454348","DOIUrl":"10.1109/TCSII.2024.3454348","url":null,"abstract":"This brief presents a capacitively-biased CMOS voltage reference, which can operate from a sub-1V supply while achieving a low temperature coefficient (TC) and a competitive power-supply rejection ratio (PSRR). The reference voltage is generated by a capacitive bias circuit that provides a well-defined proportional-to-absolute-temperature (PTAT) bias current for a \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000 Vth type reference that consists of two stacked MOSFETs with different threshold voltages. The generated output voltage is sampled by an auto-zeroed (AZ) buffer, which can drive capacitive loads up to 2 nF. Fabricated in a 65 nm CMOS process, the prototype voltage reference occupies 0.058 mm2, including the AZ buffer and an on-chip timing generator. It outputs a reference voltage of 204.1 mV with a minimum supply voltage of 0.7 V. It achieves a TC of 18 ppm/°C from \u0000<inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>\u0000 C to \u0000<inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>\u0000 C and a PSRR of −75 dB at 100 Hz with only \u0000<inline-formula> <tex-math>$200~mu $ </tex-math></inline-formula>\u0000 V ripple.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"8-12"},"PeriodicalIF":4.0,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-03DOI: 10.1109/TCSII.2024.3454024
Jianfei Wang;Chen Yang;Jia Hou;Fahong Zhang;Yishuo Meng;Yang Su;Leibo Liu
To accelerate RNS-CKKS, little attention is paid to the acceleration of the operations on the edge-client. However, the devices used by the edge-client are often low-end and have limited resources and computing power, so the performance of RNS-CKKS encoding, decoding, encryption and decryption also needs to be improved. Consequently, we propose a compact and efficient hardware accelerator architecture named CAEA for these operations. In order to improve the compactness of CAEA, a reconfigurable butterfly unit is proposed, which considers both complex number arithmetic and integer modular arithmetic, so that FFT/IFFT and NTT/INTT can be executed on unified hardware processing elements without additional resource and waste. Moreover, in order to improve the computational efficiency, we also improved the dataflow of encoding, decoding, encryption, and decryption on CAEA to reduce the number of required operations and latency. CAEA is synthesized based on SMIC 40nm technology, and is also implemented on Xilinx Kintex-7 and Zynq UltraScale+ FPGA. Compared with the prior related works, in terms of performance, CAEA can achieve $2.01times $ speedup for encoding and decoding, $1.13times sim ~87.86times $ speedup for encryption, and $3.03times sim ~69.64times $ speedup for decryption. Compared with the state-of-the-art work, CAEA can achieve $1.06times sim ~4.96times $ improvement in terms of area efficiency.
{"title":"A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption","authors":"Jianfei Wang;Chen Yang;Jia Hou;Fahong Zhang;Yishuo Meng;Yang Su;Leibo Liu","doi":"10.1109/TCSII.2024.3454024","DOIUrl":"10.1109/TCSII.2024.3454024","url":null,"abstract":"To accelerate RNS-CKKS, little attention is paid to the acceleration of the operations on the edge-client. However, the devices used by the edge-client are often low-end and have limited resources and computing power, so the performance of RNS-CKKS encoding, decoding, encryption and decryption also needs to be improved. Consequently, we propose a compact and efficient hardware accelerator architecture named CAEA for these operations. In order to improve the compactness of CAEA, a reconfigurable butterfly unit is proposed, which considers both complex number arithmetic and integer modular arithmetic, so that FFT/IFFT and NTT/INTT can be executed on unified hardware processing elements without additional resource and waste. Moreover, in order to improve the computational efficiency, we also improved the dataflow of encoding, decoding, encryption, and decryption on CAEA to reduce the number of required operations and latency. CAEA is synthesized based on SMIC 40nm technology, and is also implemented on Xilinx Kintex-7 and Zynq UltraScale+ FPGA. Compared with the prior related works, in terms of performance, CAEA can achieve \u0000<inline-formula> <tex-math>$2.01times $ </tex-math></inline-formula>\u0000 speedup for encoding and decoding, \u0000<inline-formula> <tex-math>$1.13times sim ~87.86times $ </tex-math></inline-formula>\u0000 speedup for encryption, and \u0000<inline-formula> <tex-math>$3.03times sim ~69.64times $ </tex-math></inline-formula>\u0000 speedup for decryption. Compared with the state-of-the-art work, CAEA can achieve \u0000<inline-formula> <tex-math>$1.06times sim ~4.96times $ </tex-math></inline-formula>\u0000 improvement in terms of area efficiency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"243-247"},"PeriodicalIF":4.0,"publicationDate":"2024-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-02DOI: 10.1109/TCSII.2024.3452727
Liting Li;Mei Su;Guo Xu;Li Jiang;Yonglu Liu
To address the demands for a wide voltage range and high efficiency in unidirectional low power applications, a semi dual active half bridge (DAHB) converter with soft switching capability and a voltage match trapezoidal modulation (VM-TZM) control are proposed. This converter has the fewest number of active switches among existing dual active bridge converters. With the proposed control law, the converter always works under voltage match condition, effectively decoupling the control variables while achieving low root-mean-square current. Besides, the active switches can realize zero-voltage-switching (ZVS) on and the diode can obtain zero-current-switching (ZCS) off within full working range. These characteristics and benefits of the proposed converter and control law are validated through an experimental prototype.
{"title":"A Soft-Switched Semi Dual Active Half Bridge Converter With Voltage Match Trapezoidal Modulation Control","authors":"Liting Li;Mei Su;Guo Xu;Li Jiang;Yonglu Liu","doi":"10.1109/TCSII.2024.3452727","DOIUrl":"10.1109/TCSII.2024.3452727","url":null,"abstract":"To address the demands for a wide voltage range and high efficiency in unidirectional low power applications, a semi dual active half bridge (DAHB) converter with soft switching capability and a voltage match trapezoidal modulation (VM-TZM) control are proposed. This converter has the fewest number of active switches among existing dual active bridge converters. With the proposed control law, the converter always works under voltage match condition, effectively decoupling the control variables while achieving low root-mean-square current. Besides, the active switches can realize zero-voltage-switching (ZVS) on and the diode can obtain zero-current-switching (ZCS) off within full working range. These characteristics and benefits of the proposed converter and control law are validated through an experimental prototype.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"303-307"},"PeriodicalIF":4.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this brief, an adaptive dynamic programming (ADP)-based self-triggered control (STC) method was proposed to address the optimization control problem of power buffer systems in DC microgrids. The optimization control problem of power buffers is addressed in the framework of non-zero sum games to ensure mutual cooperation among power buffers. In the proposed STC mechanism, the next triggering moment is determined by the current triggering information, avoiding continuous monitoring of devices under the event-triggered control (ETC) and reducing the occupation of system communication and computing resources. Besides, an experience replay (ER) method is introduced when updating the weights of the critic neural networks (NNs). The proposed method ensures the stability of the system, eliminates the Zeno phenomenon, and leads to an adjustable positive minimum triggering interval. The effectiveness of the proposed method is ultimately verified by using a DC microgrid case study.
{"title":"ADP-Based Self-Triggered Optimal Control of Active Loads in DC Microgrid","authors":"Hanguang Su;Gan Zhi;Huaguang Zhang;Jiawei Wang;Goran Strbac;He Ren","doi":"10.1109/TCSII.2024.3452964","DOIUrl":"10.1109/TCSII.2024.3452964","url":null,"abstract":"In this brief, an adaptive dynamic programming (ADP)-based self-triggered control (STC) method was proposed to address the optimization control problem of power buffer systems in DC microgrids. The optimization control problem of power buffers is addressed in the framework of non-zero sum games to ensure mutual cooperation among power buffers. In the proposed STC mechanism, the next triggering moment is determined by the current triggering information, avoiding continuous monitoring of devices under the event-triggered control (ETC) and reducing the occupation of system communication and computing resources. Besides, an experience replay (ER) method is introduced when updating the weights of the critic neural networks (NNs). The proposed method ensures the stability of the system, eliminates the Zeno phenomenon, and leads to an adjustable positive minimum triggering interval. The effectiveness of the proposed method is ultimately verified by using a DC microgrid case study.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"193-197"},"PeriodicalIF":4.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-30DOI: 10.1109/TCSII.2024.3452098
Dongin Min;Changkun Park
In this brief, we designed a Ka-band variable-gain amplifier (VGA) using a 65-nm RFCMOS process. A capacitive compensation technique was proposed to suppress the phase error of the CMOS VGA without the additional required chip area. To this end, the cascode structure widely used in CMOS VGAs was analyzed, and based on the analyzed results, a technique of using an additional capacitor in the drain node of the common-source transistor of the cascode structure was proposed to suppress phase error. Because the proposed technique may be implemented by adding only one shunt capacitor, it is possible to efficiently utilize the chip area. In order to verify the feasibility of the proposed capacitive compensation technique, an CMOS VGA was fabricated using a 65-nm RFCMOS process. In the operating frequency range of 26.5 GHz to 30.0 GHz, the variable gain range was measured to be 20.4 dB. In this case, the measured RMS phase error was suppressed to be lower than 1.0°. In addition, only one capacitor was added for the proposed technique, so the chip size was compactly designed to be 0.056 mm2.
{"title":"Ka-Band CMOS Variable-Gain Amplifier Using Capacitive Compensation Technique to Suppress Phase Error","authors":"Dongin Min;Changkun Park","doi":"10.1109/TCSII.2024.3452098","DOIUrl":"10.1109/TCSII.2024.3452098","url":null,"abstract":"In this brief, we designed a Ka-band variable-gain amplifier (VGA) using a 65-nm RFCMOS process. A capacitive compensation technique was proposed to suppress the phase error of the CMOS VGA without the additional required chip area. To this end, the cascode structure widely used in CMOS VGAs was analyzed, and based on the analyzed results, a technique of using an additional capacitor in the drain node of the common-source transistor of the cascode structure was proposed to suppress phase error. Because the proposed technique may be implemented by adding only one shunt capacitor, it is possible to efficiently utilize the chip area. In order to verify the feasibility of the proposed capacitive compensation technique, an CMOS VGA was fabricated using a 65-nm RFCMOS process. In the operating frequency range of 26.5 GHz to 30.0 GHz, the variable gain range was measured to be 20.4 dB. In this case, the measured RMS phase error was suppressed to be lower than 1.0°. In addition, only one capacitor was added for the proposed technique, so the chip size was compactly designed to be 0.056 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"118-122"},"PeriodicalIF":4.0,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-30DOI: 10.1109/TCSII.2024.3452112
Junde Li;Guoqiang Xin;Wei-Han Yu;Ka-Fai Un;Rui P. Martins;Pui-In Mak
Analog Voice Activity Detector (VAD) is a promising candidate for a power and cost-efficient solution for AIoT voice assistants. Regrettably, the PVT variation from the analog circuits and data misalignment from sensors limit the VAD accuracy with conventional backpropagation model-based training (BPMBT). This brief presents a forward-forward closed box trainer (FFBBT) for analog VADs. It trains the analog circuit without knowing the circuit model or finding its gradient. Thus, it is insensitive to PVT variation and offset, achieving a measured VAD accuracy improvement of ~3% and an accuracy variation reduction of $5.6{times }$ . Moreover, a Tensor-Compressed Derivative-Free Optimizer (TCDFO) is also proposed to reduce the required memory for FFBBT by $1600{times }$ . The FFBBT with TCDFO is synthesized in 28 nm CMOS with a power of 512 nW and an area of 0.003 mm2.
{"title":"A 512-nW 0.003-mm² Forward-Forward Closed Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS","authors":"Junde Li;Guoqiang Xin;Wei-Han Yu;Ka-Fai Un;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2024.3452112","DOIUrl":"10.1109/TCSII.2024.3452112","url":null,"abstract":"Analog Voice Activity Detector (VAD) is a promising candidate for a power and cost-efficient solution for AIoT voice assistants. Regrettably, the PVT variation from the analog circuits and data misalignment from sensors limit the VAD accuracy with conventional backpropagation model-based training (BPMBT). This brief presents a forward-forward closed box trainer (FFBBT) for analog VADs. It trains the analog circuit without knowing the circuit model or finding its gradient. Thus, it is insensitive to PVT variation and offset, achieving a measured VAD accuracy improvement of ~3% and an accuracy variation reduction of \u0000<inline-formula> <tex-math>$5.6{times }$ </tex-math></inline-formula>\u0000. Moreover, a Tensor-Compressed Derivative-Free Optimizer (TCDFO) is also proposed to reduce the required memory for FFBBT by \u0000<inline-formula> <tex-math>$1600{times }$ </tex-math></inline-formula>\u0000. The FFBBT with TCDFO is synthesized in 28 nm CMOS with a power of 512 nW and an area of 0.003 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4703-4707"},"PeriodicalIF":4.0,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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