Pub Date : 2025-07-30DOI: 10.1109/TCSII.2025.3589808
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3589808","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3589808","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11104808","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TCSII.2025.3593639
Xiao Yang;Hao Zhang;Guohua Zhou
Besides line frequency excitation, strong nonlinear crossing effect amongst three input/output ports exists in single-inductor dual-output (SIDO) boost power factor correction (PFC) converters, which leads to the occurrence of complex behaviors including slow-scale oscillation. In this brief, a nonlinear averaged model is derived to describe the nonlinear time-periodic coupling (NTPC) effect of the SIDO PFC converter, and importantly time-frequency characteristic representation method is proposed to obtain the analytical expression of periodic equilibrium solutions. Furthermore, two types of slow-scale oscillations are identified with the help of the loci movement of Floquet multipliers. It is shown that period-doubling bifurcation and Hopf bifurcation are responsible for type I alternating peak oscillation and type II discontinuous trajectory oscillation, respectively. Especially, Hopf bifurcation results in one incommensurable frequency component with respect to the line frequency, which explains the reason why the system enters one quasi-periodic orbit. Finally, these experimental results are given to verify the theoretical analysis. These above results are beneficial to guide circuit optimal design.
{"title":"Bifurcation Analysis of Slow-Scale Oscillation in SIDO Boost PFC Converter Using Time-Frequency Characteristic Representation Method","authors":"Xiao Yang;Hao Zhang;Guohua Zhou","doi":"10.1109/TCSII.2025.3593639","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593639","url":null,"abstract":"Besides line frequency excitation, strong nonlinear crossing effect amongst three input/output ports exists in single-inductor dual-output (SIDO) boost power factor correction (PFC) converters, which leads to the occurrence of complex behaviors including slow-scale oscillation. In this brief, a nonlinear averaged model is derived to describe the nonlinear time-periodic coupling (NTPC) effect of the SIDO PFC converter, and importantly time-frequency characteristic representation method is proposed to obtain the analytical expression of periodic equilibrium solutions. Furthermore, two types of slow-scale oscillations are identified with the help of the loci movement of Floquet multipliers. It is shown that period-doubling bifurcation and Hopf bifurcation are responsible for type I alternating peak oscillation and type II discontinuous trajectory oscillation, respectively. Especially, Hopf bifurcation results in one incommensurable frequency component with respect to the line frequency, which explains the reason why the system enters one quasi-periodic orbit. Finally, these experimental results are given to verify the theoretical analysis. These above results are beneficial to guide circuit optimal design.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1308-1312"},"PeriodicalIF":4.9,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Emerging low-altitude airspace economy has driven the development of high-resolution wireless sensors. Dedicated for the Ka-band monopulse radar applications, the design of a highly integrated 1T3R transceiver is detailed in this brief. The heterodyne transceiver incorporates full radio frequency (RF), intermediate frequency (IF) and local oscillator (LO) building blocks, supporting complete monopulse detection in azimuth and elevation. The calibration mode is introduced to enable system-level instant calibrations for enhanced detection accuracy. Dual injection style of the LO source facilitates the cascade of multiple chips for large-scale sensing systems. Fabricated in 65-nm CMOS technology and packaged with the wafer-level chip-scale packaging, the transceiver achieves the peak RX/TX gain of 18.4/33.2 dB across 32–36 GHz, with a minimum RX NF of 5.7 dB and peak saturated TX power of 15.6 dBm. The high integration level and flexible configuration of the transceiver make it suitable for Ka-band monopulse radar applications.
{"title":"A Ka-Band Fully Integrated CMOS 1T3R Transceiver for Monopulse Radar Applications","authors":"Peng Gu;Enqi Zheng;Xiaofei Liao;Hengzhi Wan;Chenyu Xu;Pengfei Diao;Huiqi Liu;Dixian Zhao","doi":"10.1109/TCSII.2025.3593382","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593382","url":null,"abstract":"Emerging low-altitude airspace economy has driven the development of high-resolution wireless sensors. Dedicated for the Ka-band monopulse radar applications, the design of a highly integrated 1T3R transceiver is detailed in this brief. The heterodyne transceiver incorporates full radio frequency (RF), intermediate frequency (IF) and local oscillator (LO) building blocks, supporting complete monopulse detection in azimuth and elevation. The calibration mode is introduced to enable system-level instant calibrations for enhanced detection accuracy. Dual injection style of the LO source facilitates the cascade of multiple chips for large-scale sensing systems. Fabricated in 65-nm CMOS technology and packaged with the wafer-level chip-scale packaging, the transceiver achieves the peak RX/TX gain of 18.4/33.2 dB across 32–36 GHz, with a minimum RX NF of 5.7 dB and peak saturated TX power of 15.6 dBm. The high integration level and flexible configuration of the transceiver make it suitable for Ka-band monopulse radar applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1178-1182"},"PeriodicalIF":4.9,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
HBM (high bandwidth memory) is an emerging technology for high performance computing, but it has a different structure from traditional memory, and thus a new solution is needed. In this brief, we present an ECC (error correcting code) configuration method for SWD (sub-wordline driver) fault correction in the two-tiered ECC structure of HBM. Existing method does not have the correction capability to cover the entire range of a SWD cluster fault. In this brief, the SWD fault correction capability of the proposed method is presented through mathematical inference. And the simulation results also showed the same correction capability as the inference. And it shows the result of reducing the overhead and latency of encoder and decoder hardware when compared to the existing method.
{"title":"A New Two-Tiered ECC Configuration Method for Cluster Error Correction in HBM Architecture","authors":"Jaeil Lim;Jaewon Chung;Donghun Jeong;Daegeun Jee;Euicheol Lim","doi":"10.1109/TCSII.2025.3593226","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593226","url":null,"abstract":"HBM (high bandwidth memory) is an emerging technology for high performance computing, but it has a different structure from traditional memory, and thus a new solution is needed. In this brief, we present an ECC (error correcting code) configuration method for SWD (sub-wordline driver) fault correction in the two-tiered ECC structure of HBM. Existing method does not have the correction capability to cover the entire range of a SWD cluster fault. In this brief, the SWD fault correction capability of the proposed method is presented through mathematical inference. And the simulation results also showed the same correction capability as the inference. And it shows the result of reducing the overhead and latency of encoder and decoder hardware when compared to the existing method.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1293-1297"},"PeriodicalIF":4.9,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-25DOI: 10.1109/TCSII.2025.3592482
Nan Jiang;Mohammad Elmi;Kambiz Moez
This brief presents a novel ultra-low-power (ULP) time-domain level-crossing (TD-LC) analog-to-digital converter (ADC) with an adaptive sampling rate. By integrating a non-uniform LC sampling technique, the proposed TD-LC ADC further reduces power consumption compared to conventional TD ADCs. A voltage-to-time converter (VTC) is employed to convert the input voltage signal into a time signal, which is then subtracted from a time signal generated by a digital-to-time converter (DTC), converting the digital output from the previous digital output. The time residue determines the necessary adjustment for the digital output. Consequently, the proposed TD-LC ADC achieves 6-bit resolution using only a 3-bit time-to-digital converter (TDC). Fabricated in TSMC’s 0.13-$mu $ m CMOS process, the proposed TD-LC ADC achieves SNDR of 35.4 dB and SFDR of 45.25 dB at 518.31 KHz of BW, and SNDR of 33.59 dB and SFDR of 39.66 dB at 2.07 MHz of BW. The minimum power consumption is 206 nW with a supply voltage of 0.5 V.
{"title":"An Ultra-Low-Power Time-Domain Level-Crossing ADC With Adaptive Sampling Rate","authors":"Nan Jiang;Mohammad Elmi;Kambiz Moez","doi":"10.1109/TCSII.2025.3592482","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3592482","url":null,"abstract":"This brief presents a novel ultra-low-power (ULP) time-domain level-crossing (TD-LC) analog-to-digital converter (ADC) with an adaptive sampling rate. By integrating a non-uniform LC sampling technique, the proposed TD-LC ADC further reduces power consumption compared to conventional TD ADCs. A voltage-to-time converter (VTC) is employed to convert the input voltage signal into a time signal, which is then subtracted from a time signal generated by a digital-to-time converter (DTC), converting the digital output from the previous digital output. The time residue determines the necessary adjustment for the digital output. Consequently, the proposed TD-LC ADC achieves 6-bit resolution using only a 3-bit time-to-digital converter (TDC). Fabricated in TSMC’s 0.13-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process, the proposed TD-LC ADC achieves SNDR of 35.4 dB and SFDR of 45.25 dB at 518.31 KHz of BW, and SNDR of 33.59 dB and SFDR of 39.66 dB at 2.07 MHz of BW. The minimum power consumption is 206 nW with a supply voltage of 0.5 V.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1173-1177"},"PeriodicalIF":4.9,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-25DOI: 10.1109/TCSII.2025.3592480
Nadeem Atif;Saquib Mazhar;Mohammed Ameen;Shaik Rafi Ahamed;M. K. Bhuyan
Semantic segmentation is a pixel-level visual recognition task widely used in autonomous driving. Attaining a decent trade-off between accuracy and speed is critically important for the effective physical deployment of networks on resource-constrained edge devices. Towards this challenging task, we propose an efficient basic block that is designed to leverage local, short-range, and long-range contextual information at different abstraction levels. We introduce a simple technique inside the basic block, called Iterative Context Embedding (ICE), to reinforce the short and long-range contextual details in an iterative fashion. Based on the resulting short and long-range ICE or SLICE module, we propose an ultra-lightweight network, called SLICENet. Our model is the fastest among the existing ultra-lightweight models while achieving a decent accuracy. Specifically, with only 0.3 million parameters, it achieves 69.1% mean IoUs on the cityscapes test set, making it the smallest model to achieve this accuracy. In addition, it achieves an inference speed of 224.8 frames per second (FPS) on the RTX 3090 with $512times 1024$ resolution. To achieve a power-efficient solution meant for battery-operated devices, we also deploy our model on Xilinx’s ZCU102 development board (Zync UltraScale+ MPSoC). Despite achieving an impressive performance, its power consumption is only 950 mW; significantly lower than GPU-based inferences. Our code will be shared at https://github.com/NadeemAtif-Alig/SLICENet.
{"title":"SLICENet: An FPGA-Based Efficient Semantic Segmentation Network for Edge Deployment","authors":"Nadeem Atif;Saquib Mazhar;Mohammed Ameen;Shaik Rafi Ahamed;M. K. Bhuyan","doi":"10.1109/TCSII.2025.3592480","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3592480","url":null,"abstract":"Semantic segmentation is a pixel-level visual recognition task widely used in autonomous driving. Attaining a decent trade-off between accuracy and speed is critically important for the effective physical deployment of networks on resource-constrained edge devices. Towards this challenging task, we propose an efficient basic block that is designed to leverage local, short-range, and long-range contextual information at different abstraction levels. We introduce a simple technique inside the basic block, called Iterative Context Embedding (ICE), to reinforce the short and long-range contextual details in an iterative fashion. Based on the resulting short and long-range ICE or SLICE module, we propose an ultra-lightweight network, called SLICENet. Our model is the fastest among the existing ultra-lightweight models while achieving a decent accuracy. Specifically, with only 0.3 million parameters, it achieves 69.1% mean IoUs on the cityscapes test set, making it the smallest model to achieve this accuracy. In addition, it achieves an inference speed of 224.8 frames per second (FPS) on the RTX 3090 with <inline-formula> <tex-math>$512times 1024$ </tex-math></inline-formula> resolution. To achieve a power-efficient solution meant for battery-operated devices, we also deploy our model on Xilinx’s ZCU102 development board (Zync UltraScale+ MPSoC). Despite achieving an impressive performance, its power consumption is only 950 mW; significantly lower than GPU-based inferences. Our code will be shared at <uri>https://github.com/NadeemAtif-Alig/SLICENet</uri>.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1338-1342"},"PeriodicalIF":4.9,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-24DOI: 10.1109/TCSII.2025.3592475
Chun-Tse Su;Chao-Yen Hsu;Tai-Cheng Lee
This brief presents a calibration-free 12-bit 1.5-GS/s pipelined ADC employing a merged sub-ADC quantization (MSAQ) technique. Building upon the conventional pipelined ADC architecture, the proposed technique can extend the amplification time, thereby relaxing the design of the inner-stage residue amplifier. A prototype ADC implemented in a 28-nm CMOS technology achieves an SFDR of 70.52 dB and an SNDR of 58.03 dB at a Nyquist input, while consuming 18.5 mW from a 1-V supply. It yields Schreier and Walden figure of merits (FoM) of 164.1 dB and 18.9 fJ/conv.-step, respectively.
{"title":"A Calibration-Free 12-Bit 1.5-GS/s Pipelined ADC With Merged Sub-ADC Quantization Technique","authors":"Chun-Tse Su;Chao-Yen Hsu;Tai-Cheng Lee","doi":"10.1109/TCSII.2025.3592475","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3592475","url":null,"abstract":"This brief presents a calibration-free 12-bit 1.5-GS/s pipelined ADC employing a merged sub-ADC quantization (MSAQ) technique. Building upon the conventional pipelined ADC architecture, the proposed technique can extend the amplification time, thereby relaxing the design of the inner-stage residue amplifier. A prototype ADC implemented in a 28-nm CMOS technology achieves an SFDR of 70.52 dB and an SNDR of 58.03 dB at a Nyquist input, while consuming 18.5 mW from a 1-V supply. It yields Schreier and Walden figure of merits (FoM) of 164.1 dB and 18.9 fJ/conv.-step, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1168-1172"},"PeriodicalIF":4.9,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-22DOI: 10.1109/TCSII.2025.3591633
Haikuo Shao;Aotao Wang;Zhongfeng Wang
Layer normalization (LN) function is widely adopted in Transformer-based neural networks. The efficient training of Transformers on personal devices is attracting attention for data privacy and latency concerns. However, the critical LN function involves extreme outliers for quantization, as well as hardware-unfriendly square-root and division operations, posing resource challenges for training deployment on the edge. This brief proposes an efficient LN training architecture with algorithm and hardware co-optimization. Specifically, we present a dynamic quantized algorithm based on integer arithmetics to smooth outliers for sufficient training accuracy. Then, we develop a reconfigurable hardware architecture to efficiently support various operations during LN training, with a vector-wise pipelined dataflow to improve hardware efficiency further. Experimental results show that our architecture achieves up to 0.25 and 1.0 Giga input per Second (GinS) in throughput at FPGA and ASIC platforms, respectively, outperforming prior works.
{"title":"An Efficient Layer Normalization Training Module With Dynamic Quantization for Transformers","authors":"Haikuo Shao;Aotao Wang;Zhongfeng Wang","doi":"10.1109/TCSII.2025.3591633","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3591633","url":null,"abstract":"Layer normalization (LN) function is widely adopted in Transformer-based neural networks. The efficient training of Transformers on personal devices is attracting attention for data privacy and latency concerns. However, the critical LN function involves extreme outliers for quantization, as well as hardware-unfriendly square-root and division operations, posing resource challenges for training deployment on the edge. This brief proposes an efficient LN training architecture with algorithm and hardware co-optimization. Specifically, we present a dynamic quantized algorithm based on integer arithmetics to smooth outliers for sufficient training accuracy. Then, we develop a reconfigurable hardware architecture to efficiently support various operations during LN training, with a vector-wise pipelined dataflow to improve hardware efficiency further. Experimental results show that our architecture achieves up to 0.25 and 1.0 Giga input per Second (GinS) in throughput at FPGA and ASIC platforms, respectively, outperforming prior works.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1288-1292"},"PeriodicalIF":4.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-22DOI: 10.1109/TCSII.2025.3590998
Qing Yang;Jing Wang;Hao Shen;Ju H. Park
This brief addresses the optimization problem for Markov jump systems (MJSs) with unknown dynamics via a novel scaling-based reinforcement learning scheme. First, by employing subsystem transformation, the optimal controller design problem for MJSs is reformulated into solving a set of parallel and decoupled algebraic Riccati equations (DAREs). Traditional learning schemes for solving these equations either require initially admissible control policies or suffer from slow convergence. To overcome these limitations, a novel scaling-based reinforcement learning algorithm is proposed. Several notable advantages are exhibited by the proposed algorithm: it eliminates the need for system dynamics during the learning process, achieves faster convergence, and relaxes the requirement for an initially admissible control policy. The effectiveness of the proposed scheme is rigorously proven through a mathematical induction method. Finally, the feasibility of the proposed scheme is verified using an operational amplifier circuit example, and its superiority is demonstrated through a series of comparative simulations.
{"title":"Learning-Based Scaling Scheme for Markov Jump Systems and Its Application in Operational Amplifier Circuit","authors":"Qing Yang;Jing Wang;Hao Shen;Ju H. Park","doi":"10.1109/TCSII.2025.3590998","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3590998","url":null,"abstract":"This brief addresses the optimization problem for Markov jump systems (MJSs) with unknown dynamics via a novel scaling-based reinforcement learning scheme. First, by employing subsystem transformation, the optimal controller design problem for MJSs is reformulated into solving a set of parallel and decoupled algebraic Riccati equations (DAREs). Traditional learning schemes for solving these equations either require initially admissible control policies or suffer from slow convergence. To overcome these limitations, a novel scaling-based reinforcement learning algorithm is proposed. Several notable advantages are exhibited by the proposed algorithm: it eliminates the need for system dynamics during the learning process, achieves faster convergence, and relaxes the requirement for an initially admissible control policy. The effectiveness of the proposed scheme is rigorously proven through a mathematical induction method. Finally, the feasibility of the proposed scheme is verified using an operational amplifier circuit example, and its superiority is demonstrated through a series of comparative simulations.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1238-1242"},"PeriodicalIF":4.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The multi-coils configuration presents an effective approach for high-power wireless power transfer (WPT) systems. Among them, mitigating complex cross-coupling in magnetic couplers remains critical to achieving high efficiency and stable power delivery. Thus, this brief proposes a compact dual-channel WPT system with decoupled coils to enhance the overall power capacity. The transmitter and receiver have the same structure, with each charging pad constructed by solenoid coils wound around Q-coils and ferrite cores. Solenoid coils and Q-coils are naturally decoupled from each other, thereby eliminating additional coupling interference and only their main mutual inductance $M_{1}$ , $M_{2}$ are retained. Furthermore, the principle of power enhancement and constant current (CC) output is thoroughly analyzed, and a more generalized output model is derived. Finally, a 305 W experimental prototype was constructed, with results in agreement with theoretical analyses. Compared with the single-channel system, the output current (2.82 A) of the proposed system is amplified by (1+$M_{1}$ /${M} _{2}$ ), with the peak efficiency reaching 90.5%, an improvement of about 6%.
{"title":"A Compact Dual-Channel WPT System Based on Decoupled Integrated Coils for Power Enhancement","authors":"Jiawei Xie;Yandong Chen;Yuhang Zhou;Cong Luo;Jian Guo","doi":"10.1109/TCSII.2025.3591215","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3591215","url":null,"abstract":"The multi-coils configuration presents an effective approach for high-power wireless power transfer (WPT) systems. Among them, mitigating complex cross-coupling in magnetic couplers remains critical to achieving high efficiency and stable power delivery. Thus, this brief proposes a compact dual-channel WPT system with decoupled coils to enhance the overall power capacity. The transmitter and receiver have the same structure, with each charging pad constructed by solenoid coils wound around Q-coils and ferrite cores. Solenoid coils and Q-coils are naturally decoupled from each other, thereby eliminating additional coupling interference and only their main mutual inductance <inline-formula> <tex-math>$M_{1}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$M_{2}$ </tex-math></inline-formula> are retained. Furthermore, the principle of power enhancement and constant current (CC) output is thoroughly analyzed, and a more generalized output model is derived. Finally, a 305 W experimental prototype was constructed, with results in agreement with theoretical analyses. Compared with the single-channel system, the output current (2.82 A) of the proposed system is amplified by (1+<inline-formula> <tex-math>$M_{1}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${M} _{2}$ </tex-math></inline-formula>), with the peak efficiency reaching 90.5%, an improvement of about 6%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1243-1247"},"PeriodicalIF":4.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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