This brief is concerned with the frequency control problem of the unknown Markov jump power systems via model-free static output feedback control approach. Due to introduction of PID control strategy, the power system is modeled as a multi-output system. The multi-output system is first converted to the single-output one which remains observable. A new reconfiguration model is therewith established by using input-output data from the single-output power system, and then the data-based reconfiguration model is given. According to the data-based expression, the stochastic stability conditions of the closed-loop system for the Markov jump power system are constructed in the form of data-based linear matrix inequalities, and the mode-dependent output feedback gain is determined. Finally, the availability of the proposed method is demonstrated by a simulation example.
{"title":"Model-Free Frequency Control of Power Systems With Unknown Markov Jump Parameters","authors":"Shicheng Huo;Zhipeng Wang;Guobao Liu;Feng Li;Hao Shen","doi":"10.1109/TCSII.2024.3430269","DOIUrl":"10.1109/TCSII.2024.3430269","url":null,"abstract":"This brief is concerned with the frequency control problem of the unknown Markov jump power systems via model-free static output feedback control approach. Due to introduction of PID control strategy, the power system is modeled as a multi-output system. The multi-output system is first converted to the single-output one which remains observable. A new reconfiguration model is therewith established by using input-output data from the single-output power system, and then the data-based reconfiguration model is given. According to the data-based expression, the stochastic stability conditions of the closed-loop system for the Markov jump power system are constructed in the form of data-based linear matrix inequalities, and the mode-dependent output feedback gain is determined. Finally, the availability of the proposed method is demonstrated by a simulation example.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4934-4938"},"PeriodicalIF":4.0,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141738733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-15DOI: 10.1109/TCSII.2024.3427832
Raghav Bansal;Shouri Chatterjee
This brief presents an ultra-low power, output-capacitor-less low-dropout regulator (OCL-LDO) with a multiple-feedback loop (MFL) for Internet-of-Things (IoT) devices. The proposed LDO consists of five feedback loops that offer excellent steady-state and transient performance. A tri-loop flipped-voltage-follower (FVF) stage enhances both line and load regulation. The slew-rate enhancement loop based on source cross-coupled error amplifier (SXCEA) provides a fast transient response. Moreover, the proposed LDO utilizes a dynamic feedback loop that significantly improves the undershoot recovery time during the full load step current. The design was fabricated in a 65-nm low-power CMOS process and occupies an area of 0.025 mm2. The LDO can deliver a maximum of 50 mA load current at a 1 V output voltage and consume only 22 nA measured quiescent current. The measurement results show that the proposed LDO achieves a load regulation of 0.004 mV/mA and a low-frequency power supply rejection (PSR) at full load of −63.5 dB. For a load current step from 200 nA to 50 mA with a 10 ns edge time, the measured voltage undershoot is 574 mV and settles within 200 ns. We achieve a figure-of-merit of 0.5 fs.
{"title":"A 22-nA Quiescent Current, 50-mA Output-Capacitor-Less Low-Dropout Regulator With Multiple-Feedback Loop for IoT Devices","authors":"Raghav Bansal;Shouri Chatterjee","doi":"10.1109/TCSII.2024.3427832","DOIUrl":"10.1109/TCSII.2024.3427832","url":null,"abstract":"This brief presents an ultra-low power, output-capacitor-less low-dropout regulator (OCL-LDO) with a multiple-feedback loop (MFL) for Internet-of-Things (IoT) devices. The proposed LDO consists of five feedback loops that offer excellent steady-state and transient performance. A tri-loop flipped-voltage-follower (FVF) stage enhances both line and load regulation. The slew-rate enhancement loop based on source cross-coupled error amplifier (SXCEA) provides a fast transient response. Moreover, the proposed LDO utilizes a dynamic feedback loop that significantly improves the undershoot recovery time during the full load step current. The design was fabricated in a 65-nm low-power CMOS process and occupies an area of 0.025 mm2. The LDO can deliver a maximum of 50 mA load current at a 1 V output voltage and consume only 22 nA measured quiescent current. The measurement results show that the proposed LDO achieves a load regulation of 0.004 mV/mA and a low-frequency power supply rejection (PSR) at full load of −63.5 dB. For a load current step from 200 nA to 50 mA with a 10 ns edge time, the measured voltage undershoot is 574 mV and settles within 200 ns. We achieve a figure-of-merit of 0.5 fs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4608-4612"},"PeriodicalIF":4.0,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141721617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-15DOI: 10.1109/TCSII.2024.3427767
Xing Li;Lei Zhou;Xuan Guo;Hanbo Jia;Danyu Wu;Jin Wu;Xinyu Liu
This brief presents a 16-bit 5 GS/s current-steering digital-to-analog converter (DAC) with a redundant-MSB based digital pre-distortion (RMDPD) technique. 1-bit MSB is added during decoding to accommodate digital compensation of element mismatch errors, enhancing both the low-frequency and high-frequency linearity without penalty on the noise floor. In addition, an improved data/dummy-data scheme, which incorporates the dummy-data generation logic into the 2:1 multiplexer (MUX) with half-rate clock, is used to mitigate the code-dependent supply ripples and induced retiming errors. The implemented DAC achieves > 61 dBc spurious-free dynamic range (SFDR) and < −72 dBc third-order intermodulation distortion (IM3) for output frequencies up to Nyquist. The DAC core occupies $0.42~mm^{2}$ active area and dissipates about 360 mW at 1.8V/1.0V/-1.8V supply.
{"title":"A 16-Bit 5 GS/s DAC With Redundant-MSB-Based Digital Pre-Distortion Achieving SFDR >61 dBc Up to 2.4 GHz in 40-nm CMOS","authors":"Xing Li;Lei Zhou;Xuan Guo;Hanbo Jia;Danyu Wu;Jin Wu;Xinyu Liu","doi":"10.1109/TCSII.2024.3427767","DOIUrl":"10.1109/TCSII.2024.3427767","url":null,"abstract":"This brief presents a 16-bit 5 GS/s current-steering digital-to-analog converter (DAC) with a redundant-MSB based digital pre-distortion (RMDPD) technique. 1-bit MSB is added during decoding to accommodate digital compensation of element mismatch errors, enhancing both the low-frequency and high-frequency linearity without penalty on the noise floor. In addition, an improved data/dummy-data scheme, which incorporates the dummy-data generation logic into the 2:1 multiplexer (MUX) with half-rate clock, is used to mitigate the code-dependent supply ripples and induced retiming errors. The implemented DAC achieves > 61 dBc spurious-free dynamic range (SFDR) and < −72 dBc third-order intermodulation distortion (IM3) for output frequencies up to Nyquist. The DAC core occupies \u0000<inline-formula> <tex-math>$0.42~mm^{2}$ </tex-math></inline-formula>\u0000 active area and dissipates about 360 mW at 1.8V/1.0V/-1.8V supply.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4829-4833"},"PeriodicalIF":4.0,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141721615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-15DOI: 10.1109/tcsii.2024.3427851
Chen Qi, Shuangyin Yang, Xin Jin, Xiyou Chen, Peng Wang
{"title":"Frequency Selection to Achieve CV/CC Output for Single-Wire Power Transfer Systems","authors":"Chen Qi, Shuangyin Yang, Xin Jin, Xiyou Chen, Peng Wang","doi":"10.1109/tcsii.2024.3427851","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3427851","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"23 1","pages":""},"PeriodicalIF":4.4,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141722438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-10DOI: 10.1109/TCSII.2024.3426551
Seyed Hadi Mirfarshbafan;Christoph Studer
We present a GlobalFoundries 22FDX FD-SOI application-specific integrated circuit (ASIC) of a beamspace equalizer for millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) systems. The ASIC implements a recently-proposed power-saving technique called sparsity-adaptive equalization (SPADE). SPADE exploits the inherent sparsity of mmWave channels in the beamspace domain to reduce the dynamic power of matrix-vector products by skipping multiplications for which the magnitude of both operands are below pre-defined thresholds. Simulations with realistic mmWave channels show that SPADE incurs less than 0.7 dB SNR degradation at 1% target bit error rate compared to antenna-domain equalization. ASIC measurement results demonstrate an equalization throughput of 46 Gbps and show that SPADE offers up to 38% power savings compared to antenna-domain equalization. A comparison with state-of-the-art massive MIMO equalizer designs reveals that our ASIC achieves superior normalized energy efficiency.
{"title":"A 46 Gbps 12 pJ/b Sparsity-Adaptive Beamspace Equalizer for mmWave Massive MIMO in 22FDX","authors":"Seyed Hadi Mirfarshbafan;Christoph Studer","doi":"10.1109/TCSII.2024.3426551","DOIUrl":"10.1109/TCSII.2024.3426551","url":null,"abstract":"We present a GlobalFoundries 22FDX FD-SOI application-specific integrated circuit (ASIC) of a beamspace equalizer for millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) systems. The ASIC implements a recently-proposed power-saving technique called sparsity-adaptive equalization (SPADE). SPADE exploits the inherent sparsity of mmWave channels in the beamspace domain to reduce the dynamic power of matrix-vector products by skipping multiplications for which the magnitude of both operands are below pre-defined thresholds. Simulations with realistic mmWave channels show that SPADE incurs less than 0.7 dB SNR degradation at 1% target bit error rate compared to antenna-domain equalization. ASIC measurement results demonstrate an equalization throughput of 46 Gbps and show that SPADE offers up to 38% power savings compared to antenna-domain equalization. A comparison with state-of-the-art massive MIMO equalizer designs reveals that our ASIC achieves superior normalized energy efficiency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4969-4973"},"PeriodicalIF":4.0,"publicationDate":"2024-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141587446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-10DOI: 10.1109/TCSII.2024.3426952
Jiawei Xu;Jing Wang;Ju H. Park;Xiangpeng Xie;Hao Shen
This brief addresses the optimal control issue of a three-phase grid-connected voltage source inverter under electromagnetic interference. Aiming to reduce the computational burden brought by the phase-locked loop, grid voltage modulation is used to transform the nonlinear inverter system into a linear system. A novel auxiliary variable is proposed to design a linear quadratic regulator, and the controller can exponentially stabilize the system globally. The nonlinear observer is used to estimate the grid voltage, and the unscented Kalman filter is utilized to filter the output of the nonlinear observer and the current sampling data. The control scheme proposed in this brief can achieve satisfactory transient and steady-state performance under severe electromagnetic interference. The simulation validates the theoretical analysis and the effectiveness of the proposed control scheme.
{"title":"An Optimal Control Scheme for a Grid-Connected Inverter Under Measurement Noise","authors":"Jiawei Xu;Jing Wang;Ju H. Park;Xiangpeng Xie;Hao Shen","doi":"10.1109/TCSII.2024.3426952","DOIUrl":"10.1109/TCSII.2024.3426952","url":null,"abstract":"This brief addresses the optimal control issue of a three-phase grid-connected voltage source inverter under electromagnetic interference. Aiming to reduce the computational burden brought by the phase-locked loop, grid voltage modulation is used to transform the nonlinear inverter system into a linear system. A novel auxiliary variable is proposed to design a linear quadratic regulator, and the controller can exponentially stabilize the system globally. The nonlinear observer is used to estimate the grid voltage, and the unscented Kalman filter is utilized to filter the output of the nonlinear observer and the current sampling data. The control scheme proposed in this brief can achieve satisfactory transient and steady-state performance under severe electromagnetic interference. The simulation validates the theoretical analysis and the effectiveness of the proposed control scheme.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4929-4933"},"PeriodicalIF":4.0,"publicationDate":"2024-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141587447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-09DOI: 10.1109/TCSII.2024.3425595
Omer Lutfi Nuzumlalı;Tufan Coskun Karalar
This brief introduces a current calibration circuit that is specifically designed for use in a column-parallel Dual-Ramp Single-Slope (DRSS) ADC. This circuit creates two current sources with a precise current ratio. These currents are then used in coarse and fine conversion stages. The desired current ratio can be achieved by adjusting the integration times based on standard clock sources in typical CMOS circuits. A 14-bit DRSS ADC that utilizes this calibration technique has been implemented in a $0.18~mu $ m CMOS technology to be used in an Infrared Detector (IR) Read-Out Integrated Circuit (ROIC). Experiments demonstrate that a DNL error smaller than ±0.4 LSB is successfully achieved when the current calibration circuit is active.
{"title":"A Current Calibration Circuit for a 14-Bit Column-Parallel Dual-Ramp Single-Slope ADC in Infrared Image Sensors","authors":"Omer Lutfi Nuzumlalı;Tufan Coskun Karalar","doi":"10.1109/TCSII.2024.3425595","DOIUrl":"10.1109/TCSII.2024.3425595","url":null,"abstract":"This brief introduces a current calibration circuit that is specifically designed for use in a column-parallel Dual-Ramp Single-Slope (DRSS) ADC. This circuit creates two current sources with a precise current ratio. These currents are then used in coarse and fine conversion stages. The desired current ratio can be achieved by adjusting the integration times based on standard clock sources in typical CMOS circuits. A 14-bit DRSS ADC that utilizes this calibration technique has been implemented in a \u0000<inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>\u0000 m CMOS technology to be used in an Infrared Detector (IR) Read-Out Integrated Circuit (ROIC). Experiments demonstrate that a DNL error smaller than ±0.4 LSB is successfully achieved when the current calibration circuit is active.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4824-4828"},"PeriodicalIF":4.0,"publicationDate":"2024-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141570630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-05DOI: 10.1109/TCSII.2024.3423839
Hui Nie;Tiancheng Yu;Jiangbo Chen;Jiabing Liu;Dongdong Liu;Xiaopeng Yu;Qun Jane Gu;Zhiwei Xu
This brief presents a 0.5-8 GHz CMOS RF receiver front-end (RxFE) tailored for cognitive radio (CR) and digital phased array (DPA) applications. The RxFE comprises a wideband mixer with noise suppression capability, along with a reconfigurable band-pass filter (BPF) designed to adapt to different intermediate frequencies (IFs) and signal bandwidths (SBWs). Additionally, the BPF functions as a programmable gain amplifier (PGA), enabling support for a large dynamic range with fine gain adjustment. The BPF offers a programmable center frequency (CF) range from 250 MHz to 450 MHz with a 5 MHz step, as well as support for tunable passbands from 60 MHz to 240 MHz with 5 MHz resolution. The RF RxFE provides a gain control range of 15-to-55 dB with a 0.5 dB gain step. Fabricated in a standard 55 nm CMOS process, the prototype occupies an area of $2.29~mm^{2}$ including pads, consuming 75.6mW power without an on-chip high-IF BPF and 226.8mW with it at 2.3GHz LO input. Measurement results indicate that the prototype achieves approximately 10 ns gain switching time and 350 ns frequency hopping time when driven by an external fast-switching local oscillation (LO) signal, attributed to its high IF architecture. The receiver demonstrates exceptional agility, meeting the stringent requirements of CR and DPA applications.
{"title":"A 0.5-8GHz Reconfigurable CMOS RF Receiver Front-End for CR and DPA Applications","authors":"Hui Nie;Tiancheng Yu;Jiangbo Chen;Jiabing Liu;Dongdong Liu;Xiaopeng Yu;Qun Jane Gu;Zhiwei Xu","doi":"10.1109/TCSII.2024.3423839","DOIUrl":"10.1109/TCSII.2024.3423839","url":null,"abstract":"This brief presents a 0.5-8 GHz CMOS RF receiver front-end (RxFE) tailored for cognitive radio (CR) and digital phased array (DPA) applications. The RxFE comprises a wideband mixer with noise suppression capability, along with a reconfigurable band-pass filter (BPF) designed to adapt to different intermediate frequencies (IFs) and signal bandwidths (SBWs). Additionally, the BPF functions as a programmable gain amplifier (PGA), enabling support for a large dynamic range with fine gain adjustment. The BPF offers a programmable center frequency (CF) range from 250 MHz to 450 MHz with a 5 MHz step, as well as support for tunable passbands from 60 MHz to 240 MHz with 5 MHz resolution. The RF RxFE provides a gain control range of 15-to-55 dB with a 0.5 dB gain step. Fabricated in a standard 55 nm CMOS process, the prototype occupies an area of \u0000<inline-formula> <tex-math>$2.29~mm^{2}$ </tex-math></inline-formula>\u0000 including pads, consuming 75.6mW power without an on-chip high-IF BPF and 226.8mW with it at 2.3GHz LO input. Measurement results indicate that the prototype achieves approximately 10 ns gain switching time and 350 ns frequency hopping time when driven by an external fast-switching local oscillation (LO) signal, attributed to its high IF architecture. The receiver demonstrates exceptional agility, meeting the stringent requirements of CR and DPA applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4819-4823"},"PeriodicalIF":4.0,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141570631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-04DOI: 10.1109/TCSII.2024.3423313
Francesco Gagliardi;Alessandro Catania;Massimo Piotto;Paolo Bruschi;Michele Dei
Enhancing the slew-rate and settling speed of amplifiers in switched-capacitor circuits without incurring in static power penalties has long been a focal point. Standardized solutions remain elusive due to significant design challenges, particularly when confronted with capacitive loads close to the range of internal parasitic capacitances. Herein, we present a novel parallel-type slew-rate enhancer based on a current-recycling core, along with insights regarding settling time optimization under power constraints. We designed a switched-capacitor integrator based on a recycling folded cascode OTA, assisted by the proposed slew-rate enhancer, in a 180-nm 1.8-V CMOS technology. The circuit is operated with an equivalent capacitive load of approximately 8 pF and an input differential voltage step as large as 3.6 V. The system is required to settle in less than 40 ns, with a relative error on the final value below 0.1%. Simulation results show that, within the power budget of $540~mu $ W, the proposed solution achieves a $times 3.5$ improvement in settling time compared to the OTA alone and a $times 2.1$ improvement compared to the OTA assisted by a standard parallel slew-rate enhancer.
长期以来，提高开关电容器电路中放大器的回转速率和沉降速度，同时不产生静态功率损耗一直是一个焦点问题。由于设计上的巨大挑战，特别是在面对接近内部寄生电容范围的电容性负载时，标准化解决方案仍然难以实现。在本文中，我们介绍了一种基于电流回收磁芯的新型并联型回转速率增强器，以及在功率限制条件下优化沉淀时间的见解。我们设计了一种基于循环折叠级联 OTA 的开关电容积分器，并采用 180 纳米 1.8-V CMOS 技术，辅以所提出的回转速率增强器。电路在约 8 pF 的等效电容负载和高达 3.6 V 的输入差分电压阶跃下运行。系统要求在 40 ns 内稳定下来，最终值的相对误差低于 0.1%。仿真结果表明，在 540~mu $ W 的功率预算范围内，与单独的 OTA 相比，所提出的解决方案可将安顿时间缩短 3.5 倍，与由标准并行压摆率增强器辅助的 OTA 相比，可将安顿时间缩短 2.1 倍。
{"title":"Parallel Slew-Rate Enhancer With Current-Recycling Core for Switched-Capacitors Circuits","authors":"Francesco Gagliardi;Alessandro Catania;Massimo Piotto;Paolo Bruschi;Michele Dei","doi":"10.1109/TCSII.2024.3423313","DOIUrl":"10.1109/TCSII.2024.3423313","url":null,"abstract":"Enhancing the slew-rate and settling speed of amplifiers in switched-capacitor circuits without incurring in static power penalties has long been a focal point. Standardized solutions remain elusive due to significant design challenges, particularly when confronted with capacitive loads close to the range of internal parasitic capacitances. Herein, we present a novel parallel-type slew-rate enhancer based on a current-recycling core, along with insights regarding settling time optimization under power constraints. We designed a switched-capacitor integrator based on a recycling folded cascode OTA, assisted by the proposed slew-rate enhancer, in a 180-nm 1.8-V CMOS technology. The circuit is operated with an equivalent capacitive load of approximately 8 pF and an input differential voltage step as large as 3.6 V. The system is required to settle in less than 40 ns, with a relative error on the final value below 0.1%. Simulation results show that, within the power budget of \u0000<inline-formula> <tex-math>$540~mu $ </tex-math></inline-formula>\u0000W, the proposed solution achieves a \u0000<inline-formula> <tex-math>$times 3.5$ </tex-math></inline-formula>\u0000 improvement in settling time compared to the OTA alone and a \u0000<inline-formula> <tex-math>$times 2.1$ </tex-math></inline-formula>\u0000 improvement compared to the OTA assisted by a standard parallel slew-rate enhancer.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4814-4818"},"PeriodicalIF":4.0,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10585330","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141549479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-03DOI: 10.1109/TCSII.2024.3422656
Aoran Han;Xun Luo
In this brief, a current-reused noise-canceling low noise amplifier (LNA) operating at 60-GHz is proposed. To reduce the noise of cascode at millimeter-wave (mm-wave) frequency, an auxiliary path is introduced to neutralize the extra thermal noise of common-gate (CG) transistor caused by parasitic capacitance. The noise-canceling path is implemented in a current-reused way to prevent an excessive rise in dc power consumption. A size-aggregated self-coupling-canceling transformer is developed to decrease chip area without compromising noise cancellation effectiveness. The proposed cascode noise-canceling LNA is fabricated in a conventional 40-nm CMOS technology. The measurement results show a peak gain of 16.8 dB at 53.6 GHz and a 3-dB bandwidth from 50.6 to 67 GHz. The measured typical noise figure (NF) is 4.4–6.3 dB within the operating frequency range. The in-band input 1-dB compression point (IP1dB) is −13.0 dBm at 60 GHz. The proposed LNA can support 64-QAM with a 500-MHz channel bandwidth at 60 GHz achieving 2.3% Error Vector Magnitude (EVM).
{"title":"A 60-GHz Current-Reused Cascode Noise-Canceling Low Noise Amplifier","authors":"Aoran Han;Xun Luo","doi":"10.1109/TCSII.2024.3422656","DOIUrl":"10.1109/TCSII.2024.3422656","url":null,"abstract":"In this brief, a current-reused noise-canceling low noise amplifier (LNA) operating at 60-GHz is proposed. To reduce the noise of cascode at millimeter-wave (mm-wave) frequency, an auxiliary path is introduced to neutralize the extra thermal noise of common-gate (CG) transistor caused by parasitic capacitance. The noise-canceling path is implemented in a current-reused way to prevent an excessive rise in dc power consumption. A size-aggregated self-coupling-canceling transformer is developed to decrease chip area without compromising noise cancellation effectiveness. The proposed cascode noise-canceling LNA is fabricated in a conventional 40-nm CMOS technology. The measurement results show a peak gain of 16.8 dB at 53.6 GHz and a 3-dB bandwidth from 50.6 to 67 GHz. The measured typical noise figure (NF) is 4.4–6.3 dB within the operating frequency range. The in-band input 1-dB compression point (IP1dB) is −13.0 dBm at 60 GHz. The proposed LNA can support 64-QAM with a 500-MHz channel bandwidth at 60 GHz achieving 2.3% Error Vector Magnitude (EVM).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4809-4813"},"PeriodicalIF":4.0,"publicationDate":"2024-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141549480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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