Lattice-based cryptography (LBC) exploits the learning with errors (LWE) problem and is the main algorithm standardized for Post-Quantum Cryptography (PQC). Number theoretic transforms (NTT) account for most of the latency and energy in the computation of the LWE problem. This brief presents a Compute-in-Memory (CIM) configurable-pipeline NTT accelerator for PQC. The accelerator incorporates a bidirectional pipeline array to minimize data latency, CIM processing elements to reduce memory access, and a parallel PQC circuit for LBC protocol deployment. A 28 nm chip of the accelerator consumes only 13 nJ per 256-point NTT, while achieving a throughput of 75.6 KOPS that achieves a remarkable reduction of up to 78% in clock cycles and a 45% reduction in energy consumption than state-of-the-art designs.
{"title":"A 28 nm 75.6 KOPS 13 nJ Computing-in-Memory Pipeline Number Theoretic Transform Accelerator for PQC","authors":"Jialiang Zhu;Yiyang Yuan;Long Nie;Weiye Tang;Ming Li;Hao Wu;Xiaojin Zhao;Guozhong Xing;Feng Zhang","doi":"10.1109/TCSII.2024.3481996","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3481996","url":null,"abstract":"Lattice-based cryptography (LBC) exploits the learning with errors (LWE) problem and is the main algorithm standardized for Post-Quantum Cryptography (PQC). Number theoretic transforms (NTT) account for most of the latency and energy in the computation of the LWE problem. This brief presents a Compute-in-Memory (CIM) configurable-pipeline NTT accelerator for PQC. The accelerator incorporates a bidirectional pipeline array to minimize data latency, CIM processing elements to reduce memory access, and a parallel PQC circuit for LBC protocol deployment. A 28 nm chip of the accelerator consumes only 13 nJ per 256-point NTT, while achieving a throughput of 75.6 KOPS that achieves a remarkable reduction of up to 78% in clock cycles and a 45% reduction in energy consumption than state-of-the-art designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"273-277"},"PeriodicalIF":4.0,"publicationDate":"2024-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-15DOI: 10.1109/TCSII.2024.3481002
Ke Chang;Guohe Zhang;Yang Pu;Yan Wang;Yuxin Wang
This brief proposes an improved architecture for multi-stage noise-shaping (MASH) $Sigma Delta $ modulators ( $Sigma Delta $ Ms), which can reduce quantization noise leakage and eliminate the requirement of high-gain opamps. Based on the proposed filter mismatch shaping (FMS) technique, filter mismatch between analog and digital domains in the MASH $Sigma Delta $ M can be mitigated, reducing inband quantization noise leakage and obtaining less sensitivity to opamps gain. Hence, the DC gain of opamps can be minimized, and simpler opamps with fewer stacked transistors would be allowed, facilitating low-voltage and energy-efficient operation. Fabricated in 55-nm CMOS and sampled at 3.2 MHz, the prototype modulator achieves a peak SNDR of 77.4 dB in a 110.3-kHz bandwidth (BW) while dissipating $116.5~mu $ W from a 1.2-V supply.
{"title":"MASH ΣΔ Modulator With Filter Mismatch Shaping Technique","authors":"Ke Chang;Guohe Zhang;Yang Pu;Yan Wang;Yuxin Wang","doi":"10.1109/TCSII.2024.3481002","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3481002","url":null,"abstract":"This brief proposes an improved architecture for multi-stage noise-shaping (MASH) \u0000<inline-formula> <tex-math>$Sigma Delta $ </tex-math></inline-formula>\u0000 modulators (\u0000<inline-formula> <tex-math>$Sigma Delta $ </tex-math></inline-formula>\u0000Ms), which can reduce quantization noise leakage and eliminate the requirement of high-gain opamps. Based on the proposed filter mismatch shaping (FMS) technique, filter mismatch between analog and digital domains in the MASH \u0000<inline-formula> <tex-math>$Sigma Delta $ </tex-math></inline-formula>\u0000M can be mitigated, reducing inband quantization noise leakage and obtaining less sensitivity to opamps gain. Hence, the DC gain of opamps can be minimized, and simpler opamps with fewer stacked transistors would be allowed, facilitating low-voltage and energy-efficient operation. Fabricated in 55-nm CMOS and sampled at 3.2 MHz, the prototype modulator achieves a peak SNDR of 77.4 dB in a 110.3-kHz bandwidth (BW) while dissipating \u0000<inline-formula> <tex-math>$116.5~mu $ </tex-math></inline-formula>\u0000W from a 1.2-V supply.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"63-67"},"PeriodicalIF":4.0,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-15DOI: 10.1109/TCSII.2024.3481068
Xiangwen Xin;Ping Luo;Hao Wang;Jingwei Huang;Xiaowen Chen;Chang Liu
This brief proposes an ultra-low-power low dropout (LDO) regulator using adaptive pole tracking and adaptive transconductance technique, aimed at further enhancing the efficiency of power management integrated circuits (PMIC). In light current loads, only the folded cascode amplifier is opened to provide excellent output voltage accuracy while reducing power consumption. In heavy current loads, activating the operational transconductance amplifier improves transient performance. An adaptive pole-tracking technique has been applied in the proposed LDO to ensure loop stability. In addition, a low-power bandgap reference was embedded into the proposed LDO, which simplifies the peripheral circuit of LDO in practical application. The proposed ultra-low-power LDO was fabricated in a $0.18~mu $ m BCD process, with an overshoot and undershoot voltage of 12mV, and ultra-low quiescent current of 96nA.
{"title":"A 96-nA Quiescent Current LDO With Embedded BGR Using Adaptive Pole Tracking and Adaptive Transconductance Technique","authors":"Xiangwen Xin;Ping Luo;Hao Wang;Jingwei Huang;Xiaowen Chen;Chang Liu","doi":"10.1109/TCSII.2024.3481068","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3481068","url":null,"abstract":"This brief proposes an ultra-low-power low dropout (LDO) regulator using adaptive pole tracking and adaptive transconductance technique, aimed at further enhancing the efficiency of power management integrated circuits (PMIC). In light current loads, only the folded cascode amplifier is opened to provide excellent output voltage accuracy while reducing power consumption. In heavy current loads, activating the operational transconductance amplifier improves transient performance. An adaptive pole-tracking technique has been applied in the proposed LDO to ensure loop stability. In addition, a low-power bandgap reference was embedded into the proposed LDO, which simplifies the peripheral circuit of LDO in practical application. The proposed ultra-low-power LDO was fabricated in a \u0000<inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>\u0000m BCD process, with an overshoot and undershoot voltage of 12mV, and ultra-low quiescent current of 96nA.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"318-322"},"PeriodicalIF":4.0,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-15DOI: 10.1109/TCSII.2024.3481069
Juwon Kim;Youngjoo Lee;Byung-Wook Min
This brief presents a compact Ka-band bi-directional variable gain phase shifter (BVGPS) using 28-nm CMOS technology. The BVGPS consists of a phase inverting bi-directional variable gain amplifier (PI-BVGA) and 3-bit switched-delay type phase shifter (STPS). The proposed PI-BVGA is implemented with a current cancelling topology for a low phase variation over a gain control range. The PI-BVGA can operate bi-directionally and provide 180° phase shift. Therefore, comparing the conventional BVGPS, this BVGPS achieves a high gain with the compact size since 180° phase shifter and single-pole double-throw (SPDT) switches are eliminated. The average rms phase error over the 16 dB gain control is 1.1° and measured rms phase and gain errors of 16 different phase states are 8.3° and 0.74 dB, respectively, at the center frequency. The maximum gain of the BVGPS is $0.7{pm }1$ .3 dB in the 16 different phase states with a power consumption of 40 mW. The BVGPS occupies 0.21 mm2, excluding the pads.
{"title":"A Compact Ka-Band Variable Gain Phase Shifter With Bi-Directional Phase Inverting Amplifier","authors":"Juwon Kim;Youngjoo Lee;Byung-Wook Min","doi":"10.1109/TCSII.2024.3481069","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3481069","url":null,"abstract":"This brief presents a compact Ka-band bi-directional variable gain phase shifter (BVGPS) using 28-nm CMOS technology. The BVGPS consists of a phase inverting bi-directional variable gain amplifier (PI-BVGA) and 3-bit switched-delay type phase shifter (STPS). The proposed PI-BVGA is implemented with a current cancelling topology for a low phase variation over a gain control range. The PI-BVGA can operate bi-directionally and provide 180° phase shift. Therefore, comparing the conventional BVGPS, this BVGPS achieves a high gain with the compact size since 180° phase shifter and single-pole double-throw (SPDT) switches are eliminated. The average rms phase error over the 16 dB gain control is 1.1° and measured rms phase and gain errors of 16 different phase states are 8.3° and 0.74 dB, respectively, at the center frequency. The maximum gain of the BVGPS is \u0000<inline-formula> <tex-math>$0.7{pm }1$ </tex-math></inline-formula>\u0000.3 dB in the 16 different phase states with a power consumption of 40 mW. The BVGPS occupies 0.21 mm2, excluding the pads.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"133-137"},"PeriodicalIF":4.0,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a balanced power amplifier (BPA) with adaptive-bias for 5G applications based on 28-nm bulk CMOS process. The PA utilizes a differential balanced structure which cancels out reflected signals at the isolation ports, thereby improving return losses. A folded differential quadrature coupler is designed to connect respectively to the input and output of the PAs. The folded layout effectively reduces the chip size. In addition, a complementary adaptive bias is implemented to cancel out the nonlinear effects of the two PAs, significantly enhancing the overall linearity. The measure PA realizes a 3-dB bandwidth of $21.3sim 28$ .4 GHz with a peak gain of 21.1 dB. The large-signal measurement results show that the PA achieve an OP1dB of 20.3 dBm, a $P_{mathrm { sat}}$ of 21.6 dBm, and a peak PAE (PAEmax) of 30.9%. The measured |AM-PM|P1dB is less than 8.9°, which is $3sim 8^{circ }$ lower than when using a normal bias. For 5G NR FR2 200-MHz 64QAM signals, the measured $P_{mathrm { avg}}$ / ${mathrm { PAE}}_{mathrm { avg}}$ / ACPR of 11.2 dBm / 6% / –24.9 dBc are achieved at the EVM of –25 dB. The DC power supply voltage is 1.8 V. The core chip size is only 0.27 mm2, demonstrating a compact design within a balanced architecture.
{"title":"A Balanced Power Amplifier With Complementary Adaptive Bias in 28-nm Bulk CMOS for 5G Millimeter-Wave Systems","authors":"Ning-Zheng Sun;Li Gao;Weisen Zeng;Jie Hu;Xinyang Liu;Xiu Yin Zhang","doi":"10.1109/TCSII.2024.3480706","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3480706","url":null,"abstract":"This brief presents a balanced power amplifier (BPA) with adaptive-bias for 5G applications based on 28-nm bulk CMOS process. The PA utilizes a differential balanced structure which cancels out reflected signals at the isolation ports, thereby improving return losses. A folded differential quadrature coupler is designed to connect respectively to the input and output of the PAs. The folded layout effectively reduces the chip size. In addition, a complementary adaptive bias is implemented to cancel out the nonlinear effects of the two PAs, significantly enhancing the overall linearity. The measure PA realizes a 3-dB bandwidth of \u0000<inline-formula> <tex-math>$21.3sim 28$ </tex-math></inline-formula>\u0000.4 GHz with a peak gain of 21.1 dB. The large-signal measurement results show that the PA achieve an OP1dB of 20.3 dBm, a \u0000<inline-formula> <tex-math>$P_{mathrm { sat}}$ </tex-math></inline-formula>\u0000 of 21.6 dBm, and a peak PAE (PAEmax) of 30.9%. The measured |AM-PM|P1dB is less than 8.9°, which is \u0000<inline-formula> <tex-math>$3sim 8^{circ }$ </tex-math></inline-formula>\u0000 lower than when using a normal bias. For 5G NR FR2 200-MHz 64QAM signals, the measured \u0000<inline-formula> <tex-math>$P_{mathrm { avg}}$ </tex-math></inline-formula>\u0000 / \u0000<inline-formula> <tex-math>${mathrm { PAE}}_{mathrm { avg}}$ </tex-math></inline-formula>\u0000 / ACPR of 11.2 dBm / 6% / –24.9 dBc are achieved at the EVM of –25 dB. The DC power supply voltage is 1.8 V. The core chip size is only 0.27 mm2, demonstrating a compact design within a balanced architecture.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"58-62"},"PeriodicalIF":4.0,"publicationDate":"2024-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-11DOI: 10.1109/TCSII.2024.3478774
Hua Chen;Yuzhong Xiao;Zhenqi Chen;Run Chen;Zhaohui Wu;Bin Li
This brief presents an IEEE 802.15.4z-compliant impulse-radio ultra-wideband (IR-UWB) transmitter for an indoor positioning system. Controlled by the digital baseband, a current-mode digital power amplifier (DPA) generates programmable pulse waveforms, ensuring optimal spectrum utilization and sidelobe suppression. Uniquely, it can directly measure AM-PM distortion caused by non-linear power networks, offering an exclusive compensation method to enhance linearity and elevate in-band spectrum utilization. As a proof-of-concept, a prototype was implemented in a 22-nm FD-SOI process. The measurement result demonstrates that the design can support channels from 6.5 to 10 GHz with 13 dBm peak output power. After calibration, the output spectrum has an in-band spectrum utilization of 81% at peak output power. The chip consumes 33.4 mW at a maximum output power spectral density of −41.3 dBm/MHz.
{"title":"A Digital IR-UWB Transmitter With High Spectrum Utilization and AM-PM Distortion Calibration","authors":"Hua Chen;Yuzhong Xiao;Zhenqi Chen;Run Chen;Zhaohui Wu;Bin Li","doi":"10.1109/TCSII.2024.3478774","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3478774","url":null,"abstract":"This brief presents an IEEE 802.15.4z-compliant impulse-radio ultra-wideband (IR-UWB) transmitter for an indoor positioning system. Controlled by the digital baseband, a current-mode digital power amplifier (DPA) generates programmable pulse waveforms, ensuring optimal spectrum utilization and sidelobe suppression. Uniquely, it can directly measure AM-PM distortion caused by non-linear power networks, offering an exclusive compensation method to enhance linearity and elevate in-band spectrum utilization. As a proof-of-concept, a prototype was implemented in a 22-nm FD-SOI process. The measurement result demonstrates that the design can support channels from 6.5 to 10 GHz with 13 dBm peak output power. After calibration, the output spectrum has an in-band spectrum utilization of 81% at peak output power. The chip consumes 33.4 mW at a maximum output power spectral density of −41.3 dBm/MHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"53-57"},"PeriodicalIF":4.0,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-11DOI: 10.1109/TCSII.2024.3478797
Xiaoyan Diao;Jun Xia;Jinlin Sun;Shihong Ding;Lu Liu
This brief presents a continuous practical terminal sliding mode (CPTSM) control method for precisely regulating the output voltage of boost converters, effectively addressing the converters’ nonlinear and nonminimum phase characteristics. The proposed CPTSM control method starts with the generalized super-twisting extended state observers to estimate the input voltage and load, thereby generating a reference current that adapts to real-time variations of the operating condition. Based on the exact feedback linearization technique, the CPTSM control strategy is developed. The benefits of the proposed strategy lie in its fast transient response and strong robustness. Furthermore, stringent theoretical analysis verifies the CPTSM control system. Finally, simulation and experimental results demonstrate the effectiveness and superiority of the proposed control scheme.
{"title":"Continuous Practical Terminal Sliding Mode Controller for Boost Converters: Design and Experimental Evaluation","authors":"Xiaoyan Diao;Jun Xia;Jinlin Sun;Shihong Ding;Lu Liu","doi":"10.1109/TCSII.2024.3478797","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3478797","url":null,"abstract":"This brief presents a continuous practical terminal sliding mode (CPTSM) control method for precisely regulating the output voltage of boost converters, effectively addressing the converters’ nonlinear and nonminimum phase characteristics. The proposed CPTSM control method starts with the generalized super-twisting extended state observers to estimate the input voltage and load, thereby generating a reference current that adapts to real-time variations of the operating condition. Based on the exact feedback linearization technique, the CPTSM control strategy is developed. The benefits of the proposed strategy lie in its fast transient response and strong robustness. Furthermore, stringent theoretical analysis verifies the CPTSM control system. Finally, simulation and experimental results demonstrate the effectiveness and superiority of the proposed control scheme.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"203-207"},"PeriodicalIF":4.0,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel background calibration technique for timing mismatch in time-interleaved ADCs (TI ADCs) with fast convergence speed is presented in this brief. The proposed calibration applies a customized neural network (NN) to extract the information of timing skews for compensation. Compared to the conventional background methods for calibrating timing mismatches without reference, this brief significantly increases the convergence speed with high accuracy. In comparison with prior NN-based calibration works, this brief could follow the error changes in the background and has stronger robustness, also without any risk of fidelity problem. A 12-bit 3GSps 4-channel TI ADC model with noise and jitter is simulated for verifying the effectiveness of this technique. Simulation results show that the proposed technique could improve the SNDR and SFDR by 7.41dB and 24.73dB respectively, with only 1536 samples for convergence. Off-chip validation with a 12-bit 3GSps 4-channel TI ADC also proves the effectiveness and practicality of this brief.
{"title":"A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs","authors":"Zhifei Lu;Boyuan Zhang;Yutao Peng;Xizhu Peng;He Tang;Jie Pu;Ling Qin;Mingqiang Guo","doi":"10.1109/TCSII.2024.3477463","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3477463","url":null,"abstract":"A novel background calibration technique for timing mismatch in time-interleaved ADCs (TI ADCs) with fast convergence speed is presented in this brief. The proposed calibration applies a customized neural network (NN) to extract the information of timing skews for compensation. Compared to the conventional background methods for calibrating timing mismatches without reference, this brief significantly increases the convergence speed with high accuracy. In comparison with prior NN-based calibration works, this brief could follow the error changes in the background and has stronger robustness, also without any risk of fidelity problem. A 12-bit 3GSps 4-channel TI ADC model with noise and jitter is simulated for verifying the effectiveness of this technique. Simulation results show that the proposed technique could improve the SNDR and SFDR by 7.41dB and 24.73dB respectively, with only 1536 samples for convergence. Off-chip validation with a 12-bit 3GSps 4-channel TI ADC also proves the effectiveness and practicality of this brief.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"48-52"},"PeriodicalIF":4.0,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/TCSII.2024.3474676
Guangyao Li;Hailong Zhang;Yafei Chen;Junchen Xie;Cheol-Hee Jo;Chunbo Zhu;Shumei Cui;Dong-Hee Kim
The inevitable misalignment of magnetic couplers presents a substantial challenge to the power transmission and efficiency of inductive power transfer (IPT) systems. In this brief, an integrated mutually compensated dual receiver (IMCDR) IPT system for automated guided vehicles with high-efficiency constant current (CC) charging over a large misalignment tolerance (MT) range is proposed. The dual-channel receiver comprises two solenoid coils perpendicularly wound to each other to capture the magnetic flux along the y- and z-axes generated by the transmitter. In this way, two mutual inductances with opposite changing trends are utilized to synthesize an equivalent mutual inductance $(M_{mathrm { eq}})$ over an MT range. Further, the proposed IMCDR structure was optimized using the finite element method to obtain the optimal receiver length and $M_{mathrm { eq}}$ fluctuation rate. Finally, a 535-W/85-kHz experimental prototype was conducted. Experimental results showed that the proposed IPT system can maintain the output current fluctuation rate within 5.82% with fixed duty/frequency condition when operating over a 172% MT range, and the system efficiency ranges from 88.42% to 90.67%.
{"title":"An Integrated Mutually Compensatory Dual Receiver for AGV Misalignment-Tolerant IPT Charging","authors":"Guangyao Li;Hailong Zhang;Yafei Chen;Junchen Xie;Cheol-Hee Jo;Chunbo Zhu;Shumei Cui;Dong-Hee Kim","doi":"10.1109/TCSII.2024.3474676","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3474676","url":null,"abstract":"The inevitable misalignment of magnetic couplers presents a substantial challenge to the power transmission and efficiency of inductive power transfer (IPT) systems. In this brief, an integrated mutually compensated dual receiver (IMCDR) IPT system for automated guided vehicles with high-efficiency constant current (CC) charging over a large misalignment tolerance (MT) range is proposed. The dual-channel receiver comprises two solenoid coils perpendicularly wound to each other to capture the magnetic flux along the y- and z-axes generated by the transmitter. In this way, two mutual inductances with opposite changing trends are utilized to synthesize an equivalent mutual inductance \u0000<inline-formula> <tex-math>$(M_{mathrm { eq}})$ </tex-math></inline-formula>\u0000 over an MT range. Further, the proposed IMCDR structure was optimized using the finite element method to obtain the optimal receiver length and \u0000<inline-formula> <tex-math>$M_{mathrm { eq}}$ </tex-math></inline-formula>\u0000 fluctuation rate. Finally, a 535-W/85-kHz experimental prototype was conducted. Experimental results showed that the proposed IPT system can maintain the output current fluctuation rate within 5.82% with fixed duty/frequency condition when operating over a 172% MT range, and the system efficiency ranges from 88.42% to 90.67%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"313-317"},"PeriodicalIF":4.0,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/TCSII.2024.3474700
Jiaxu Cong;Jingyu Wang;Bin Tong;Delong Shang
In the rapidly evolving landscape of the Internet of Things (IoT), efficient and low-power communication solutions with minimal I/O count are essential for the effective connectivity of a multitude of devices. This brief presents Spike Refresh Receiver-Transmitter (SRRT), a novel ultra-low power unidirectional single-wire inter-chip communication protocol designed specifically for IoT applications. The protocol distinguishes continuous identical data through spike refresh and ensures data reliability via stability detection. We conduct theoretical analysis of the SRRT and performed post-layout simulations using layouts generated by ICC. The results show that the SRRT achieves a power consumption of 0.0605mW, a performance of 200Mbps, an energy efficiency of 0.3025pJ/bit, and an area of 0.001508mm2. Additionally, the protocol is validated in a real-world environment using a PCB comprising two FPGAs.
{"title":"SRRT: An Ultra-Low-Power Unidirectional Single-Wire Inter-Chip Communication for IoT","authors":"Jiaxu Cong;Jingyu Wang;Bin Tong;Delong Shang","doi":"10.1109/TCSII.2024.3474700","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3474700","url":null,"abstract":"In the rapidly evolving landscape of the Internet of Things (IoT), efficient and low-power communication solutions with minimal I/O count are essential for the effective connectivity of a multitude of devices. This brief presents Spike Refresh Receiver-Transmitter (SRRT), a novel ultra-low power unidirectional single-wire inter-chip communication protocol designed specifically for IoT applications. The protocol distinguishes continuous identical data through spike refresh and ensures data reliability via stability detection. We conduct theoretical analysis of the SRRT and performed post-layout simulations using layouts generated by ICC. The results show that the SRRT achieves a power consumption of 0.0605mW, a performance of 200Mbps, an energy efficiency of 0.3025pJ/bit, and an area of 0.001508mm2. Additionally, the protocol is validated in a real-world environment using a PCB comprising two FPGAs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"128-132"},"PeriodicalIF":4.0,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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