Pub Date : 2024-08-06DOI: 10.1109/TCSII.2024.3439319
Ruoyang Liu;Wenxun Wang;Chen Tang;Weichen Gao;Huazhong Yang;Yongpan Liu
Fine-grained mixed-precision fully-quantized methods have great potential to accelerate neural network training, but existing methods exhibit large accuracy loss for more complex models such as diffusion networks. This brief introduces a fully-quantized training accelerator for diffusion networks. It features a novel training framework with tensor-type- and noise-strength-aware precision scheduling to optimize bit-width allocation. The processing cluster design enables dynamical switching bit-width mappings for model weights, allows concurrent processing in 4 different bit-widths, and incorporates a gradient square sum collection unit to minimize on-chip memory access. Experimental results show up to 2.4 $times $ training speedup and 81% operation bit-width overhead reduction compared to existing designs, with minimal impact on image generation quality.
{"title":"A Fully Quantized Training Accelerator for Diffusion Network With Tensor Type & Noise Strength Aware Precision Scheduling","authors":"Ruoyang Liu;Wenxun Wang;Chen Tang;Weichen Gao;Huazhong Yang;Yongpan Liu","doi":"10.1109/TCSII.2024.3439319","DOIUrl":"10.1109/TCSII.2024.3439319","url":null,"abstract":"Fine-grained mixed-precision fully-quantized methods have great potential to accelerate neural network training, but existing methods exhibit large accuracy loss for more complex models such as diffusion networks. This brief introduces a fully-quantized training accelerator for diffusion networks. It features a novel training framework with tensor-type- and noise-strength-aware precision scheduling to optimize bit-width allocation. The processing cluster design enables dynamical switching bit-width mappings for model weights, allows concurrent processing in 4 different bit-widths, and incorporates a gradient square sum collection unit to minimize on-chip memory access. Experimental results show up to 2.4\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 training speedup and 81% operation bit-width overhead reduction compared to existing designs, with minimal impact on image generation quality.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4994-4998"},"PeriodicalIF":4.0,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141932476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-02DOI: 10.1109/TCSII.2024.3437449
Junyoung Maeng;Inho Park;Jinwoo Jeon;Hyunjin Kim;Hoi Lee;Chulwoo Kim
This brief proposes a reconfigurable DC-DC converter for an energy-harvesting system with a tri-mode recharging method for miniature Internet of Things (IoT) batteries operating at various temperatures. The proposed system and IoT battery operate at temperatures as low as – $5~^{circ }$ C with an internal resistance $(R_{INT})$ of up to 1.9 k $Omega $ . The proposed recharging method utilizes a low-dropout regulator and DC-DC converter with a negative inductor current to rapidly recharge a storage capacitor $(C_{STOR})$ and isolate the IoT battery from the $C_{STOR}$ . With a 180 nm CMOS process, the charge of the $C_{STOR}$ can be restored rapidly with the aid of the IoT battery, which reduces the ratio of the activation time $(t_{mathrm {ACT}})$ to the recharging time $(t_{mathrm {RCHG}})$ to 0.27 at – $5~^{circ }$ C.
{"title":"A Tri-Mode Reconfigurable DC-DC Converter With Photovoltaic Energy Harvesting for Miniature IoT Batteries","authors":"Junyoung Maeng;Inho Park;Jinwoo Jeon;Hyunjin Kim;Hoi Lee;Chulwoo Kim","doi":"10.1109/TCSII.2024.3437449","DOIUrl":"10.1109/TCSII.2024.3437449","url":null,"abstract":"This brief proposes a reconfigurable DC-DC converter for an energy-harvesting system with a tri-mode recharging method for miniature Internet of Things (IoT) batteries operating at various temperatures. The proposed system and IoT battery operate at temperatures as low as –\u0000<inline-formula> <tex-math>$5~^{circ }$ </tex-math></inline-formula>\u0000C with an internal resistance \u0000<inline-formula> <tex-math>$(R_{INT})$ </tex-math></inline-formula>\u0000 of up to 1.9 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000. The proposed recharging method utilizes a low-dropout regulator and DC-DC converter with a negative inductor current to rapidly recharge a storage capacitor \u0000<inline-formula> <tex-math>$(C_{STOR})$ </tex-math></inline-formula>\u0000 and isolate the IoT battery from the \u0000<inline-formula> <tex-math>$C_{STOR}$ </tex-math></inline-formula>\u0000. With a 180 nm CMOS process, the charge of the \u0000<inline-formula> <tex-math>$C_{STOR}$ </tex-math></inline-formula>\u0000 can be restored rapidly with the aid of the IoT battery, which reduces the ratio of the activation time \u0000<inline-formula> <tex-math>$(t_{mathrm {ACT}})$ </tex-math></inline-formula>\u0000 to the recharging time \u0000<inline-formula> <tex-math>$(t_{mathrm {RCHG}})$ </tex-math></inline-formula>\u0000 to 0.27 at –\u0000<inline-formula> <tex-math>$5~^{circ }$ </tex-math></inline-formula>\u0000C.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4844-4848"},"PeriodicalIF":4.0,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141880855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-02DOI: 10.1109/TCSII.2024.3437235
Ayoub Sadeghi;Rami Rasheedi;Inna Partin-Vaisband;Debjit Pal
The primary goal of approximate computing is enhancing system performance, such as energy efficiency, speed, and form factor. Despite the growing use of approximate multipliers, the design of efficient approximate compressors — a fundamental multiplier block — remains a significant challenge. In this brief, 8-transistor and 14-transistor 4:2 compressors are proposed. Both compressors exploit CMOS technology and a constant and conditional approximation of selected inputs, exhibiting fewer negative errors. As a result, a resource-expensive error recovery module is eliminated, yielding superior performance as compared with prior art. The 14-transistor architecture yields a lower error rate compared to the 8-transistor architecture, trading off lower area for higher accuracy. The compressor-tailored circuit architecture is also proposed and evaluated using image multiplication. The proposed multiplier exhibits 50% area savings and 93% lower power-delay-product compared to the exact multiplier, as well as higher accuracy, and 38% PDP enhancement compared with the state-of-the-art.
{"title":"Energy Efficient Compact Approximate Multiplier for Error-Resilient Applications","authors":"Ayoub Sadeghi;Rami Rasheedi;Inna Partin-Vaisband;Debjit Pal","doi":"10.1109/TCSII.2024.3437235","DOIUrl":"10.1109/TCSII.2024.3437235","url":null,"abstract":"The primary goal of approximate computing is enhancing system performance, such as energy efficiency, speed, and form factor. Despite the growing use of approximate multipliers, the design of efficient approximate compressors — a fundamental multiplier block — remains a significant challenge. In this brief, 8-transistor and 14-transistor 4:2 compressors are proposed. Both compressors exploit CMOS technology and a constant and conditional approximation of selected inputs, exhibiting fewer negative errors. As a result, a resource-expensive error recovery module is eliminated, yielding superior performance as compared with prior art. The 14-transistor architecture yields a lower error rate compared to the 8-transistor architecture, trading off lower area for higher accuracy. The compressor-tailored circuit architecture is also proposed and evaluated using image multiplication. The proposed multiplier exhibits 50% area savings and 93% lower power-delay-product compared to the exact multiplier, as well as higher accuracy, and 38% PDP enhancement compared with the state-of-the-art.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4989-4993"},"PeriodicalIF":4.0,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10621609","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141880823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a dynamic impedance matcher (DIM) for high-power rectifier in microwave wireless power transmission (MWPT) to enhance microwave rectifier efficiency over wide ranges of input power and load. The DIM based on an isolated Sepic converter performs dynamic impedance matching with the maximum power point tracking (MPPT). One digital processor is used to control multiple DIMs simultaneously to reduce power consumption. The DIM is implemented by a microcontroller and analog circuits and applied to 2.45 GHz system-level verification. The experimental results show that the overall power conversion efficiency (PCE) of the rectifier with DIM can reach more than 60% for the input power of 30 - 37 dBm and the load of 10 - $4000~Omega $ , where the efficiency of the isolated DIM reaches 91.7%. The input power range above 60% PCE of the rectifier is at least 3 times of that under the situation without DIM and 10 times for the load range as well.
本文介绍了一种用于微波无线功率传输（MWPT）中大功率整流器的动态阻抗匹配器（DIM），以提高微波整流器在宽输入功率和负载范围内的效率。基于隔离式 Sepic 转换器的 DIM 通过最大功率点跟踪 (MPPT) 实现动态阻抗匹配。一个数字处理器可同时控制多个 DIM，以降低功耗。DIM 由微控制器和模拟电路实现，并应用于 2.45 GHz 系统级验证。实验结果表明，在输入功率为 30 - 37 dBm、负载为 10 - $4000~Omega $ 时，带 DIM 的整流器的整体功率转换效率（PCE）可达到 60% 以上，其中隔离式 DIM 的效率达到 91.7%。整流器 60% 以上 PCE 的输入功率范围至少是无 DIM 情况下的 3 倍，负载范围也是 10 倍。
{"title":"A Dynamic Impedance Matcher to Broaden Input Power and Load Ranges for High-Power Rectifier in Microwave Wireless Power Transmission","authors":"Shuang Pan;Weiguo Lu;Wei Song;Hui Xiao;Huaiqing Zhang","doi":"10.1109/TCSII.2024.3436884","DOIUrl":"10.1109/TCSII.2024.3436884","url":null,"abstract":"This brief presents a dynamic impedance matcher (DIM) for high-power rectifier in microwave wireless power transmission (MWPT) to enhance microwave rectifier efficiency over wide ranges of input power and load. The DIM based on an isolated Sepic converter performs dynamic impedance matching with the maximum power point tracking (MPPT). One digital processor is used to control multiple DIMs simultaneously to reduce power consumption. The DIM is implemented by a microcontroller and analog circuits and applied to 2.45 GHz system-level verification. The experimental results show that the overall power conversion efficiency (PCE) of the rectifier with DIM can reach more than 60% for the input power of 30 - 37 dBm and the load of 10 - \u0000<inline-formula> <tex-math>$4000~Omega $ </tex-math></inline-formula>\u0000, where the efficiency of the isolated DIM reaches 91.7%. The input power range above 60% PCE of the rectifier is at least 3 times of that under the situation without DIM and 10 times for the load range as well.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4839-4843"},"PeriodicalIF":4.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141880824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-31DOI: 10.1109/TCSII.2024.3427234
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3427234","DOIUrl":"10.1109/TCSII.2024.3427234","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 8","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10616244","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141865955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-31DOI: 10.1109/TCSII.2024.3427232
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3427232","DOIUrl":"10.1109/TCSII.2024.3427232","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 8","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10616242","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141865957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-29DOI: 10.1109/TCSII.2024.3435066
Jiahao Dai;Jing-Wen Yi;Li Chai
Consensus, as one of the most fundamental tasks of multi-agent systems, can be accelerated by introducing the memory term into the control protocol. It has been demonstrated that on any given network, the one-tap node memory can accelerate the convergence rate, while the two-tap node memory cannot. Then, a problem arises: can the rate of consensus be further improved by adding more taps of memory? By using a novel method based on the Routh stability criterion, this brief shows that more taps of memory can further accelerate the convergence rate on special networks with star or bipartite structure. Specially, explicit formulas for the convergence rate and control parameters are derived to prove that three-tap and five-tap node memory can accelerate the convergence rate, but four-tap node memory cannot. In addition, it is found by extensive simulations that six-tap memory cannot accelerate the rate, but seven-tap memory can. Finally, a conjecture is proposed that the optimal convergence rate can be further improved when the memory taps progress from $2k$ to $2k+1$ , where $kin mathbb {N}$ .
{"title":"Accelerating Consensus for Systems on Star and Bipartite Networks Using Multi-Tap Memory","authors":"Jiahao Dai;Jing-Wen Yi;Li Chai","doi":"10.1109/TCSII.2024.3435066","DOIUrl":"10.1109/TCSII.2024.3435066","url":null,"abstract":"Consensus, as one of the most fundamental tasks of multi-agent systems, can be accelerated by introducing the memory term into the control protocol. It has been demonstrated that on any given network, the one-tap node memory can accelerate the convergence rate, while the two-tap node memory cannot. Then, a problem arises: can the rate of consensus be further improved by adding more taps of memory? By using a novel method based on the Routh stability criterion, this brief shows that more taps of memory can further accelerate the convergence rate on special networks with star or bipartite structure. Specially, explicit formulas for the convergence rate and control parameters are derived to prove that three-tap and five-tap node memory can accelerate the convergence rate, but four-tap node memory cannot. In addition, it is found by extensive simulations that six-tap memory cannot accelerate the rate, but seven-tap memory can. Finally, a conjecture is proposed that the optimal convergence rate can be further improved when the memory taps progress from \u0000<inline-formula> <tex-math>$2k$ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$2k+1$ </tex-math></inline-formula>\u0000, where \u0000<inline-formula> <tex-math>$kin mathbb {N}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4944-4948"},"PeriodicalIF":4.0,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141865956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-29DOI: 10.1109/TCSII.2024.3434562
Tianyang Yu;Bi Wu;Ke Chen;Gong Zhang;Weiqiang Liu
The low power and latency of hyperdimensional associative memory (HAM) promotes hyperdimensional computing (HDC)’s efficiency. However, overheads of HAM can be hardly further reduced, since HAM needs to store all class hypervectors, and complete the similarity calculation between them and the input sample hypervector. To address this issue, an attentioned-autocorrelation based query method called AttnACQ is proposed to avoid the storage and operations corresponding to class hypervectors. Furthermore, levearging SOT-MRAM’s ultra-low read/write delay, a high-efficient HAM matching to AttnACQ is proposed. Experiments show that this AttnACQ boosted HAM saves more than 95% area and 50% latency.
超维关联内存（HAM）的低功耗和低延迟提高了超维计算（HDC）的效率。然而，由于 HAM 需要存储所有类超向量，并完成它们与输入样本超向量之间的相似性计算，因此很难进一步降低 HAM 的开销。为了解决这个问题，我们提出了一种名为 AttnACQ 的基于关注-自相关的查询方法，以避免类超向量的存储和操作。此外，利用 SOT-MRAM 的超低读写延迟，提出了一种与 AttnACQ 匹配的高效 HAM。实验表明，这种 AttnACQ 增强型 HAM 可节省 95% 以上的面积和 50% 的延迟。
{"title":"AttnACQ: Attentioned-AutoCorrelation-Based Query for Hyperdimensional Associative Memory","authors":"Tianyang Yu;Bi Wu;Ke Chen;Gong Zhang;Weiqiang Liu","doi":"10.1109/TCSII.2024.3434562","DOIUrl":"10.1109/TCSII.2024.3434562","url":null,"abstract":"The low power and latency of hyperdimensional associative memory (HAM) promotes hyperdimensional computing (HDC)’s efficiency. However, overheads of HAM can be hardly further reduced, since HAM needs to store all class hypervectors, and complete the similarity calculation between them and the input sample hypervector. To address this issue, an attentioned-autocorrelation based query method called AttnACQ is proposed to avoid the storage and operations corresponding to class hypervectors. Furthermore, levearging SOT-MRAM’s ultra-low read/write delay, a high-efficient HAM matching to AttnACQ is proposed. Experiments show that this AttnACQ boosted HAM saves more than 95% area and 50% latency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4984-4988"},"PeriodicalIF":4.0,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141865959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A converter with high voltage gain is generally necessary for interfacing the photovoltaic (PV) systems with grid. However, more semiconductor components are needed to obtain a higher voltage gain, which results in increased losses. This brief proposes a novel non-isolated cubic boost (NNICB) DC-DC converter for high-voltage PV applications with a wide voltage gain at a lower duty ratio. Compared to traditional high-gain DC-DC converter, the NNICB converter counters the drawbacks of increased component count and high voltage stress. The NNICB DC-DC converter has a continuous source current for PV applications with low-voltage stress across the diodes and switches. A detailed steady-state analysis of the NNICB topology is carried out for the ideal and non-ideal models, and their corresponding voltage gain equations are computed. Furthermore, the analysis is performed using MATLAB/Simulink and is validated using a 230 W laboratory prototype. The experimental results show that the efficiency of the proposed NNICB topology is 94.42% with a voltage gain of 10.5 at 45% duty ratio. This proves the superior performance of the proposed novel converter in comparison with the existing topologies.
{"title":"A Novel Cubic Boost Converter With Continuous Source Current for PV Applications","authors":"Birru Srinivas;Raghavendra Rao P;H. Nagendrappa;B. Venkatesaperumal","doi":"10.1109/TCSII.2024.3434985","DOIUrl":"10.1109/TCSII.2024.3434985","url":null,"abstract":"A converter with high voltage gain is generally necessary for interfacing the photovoltaic (PV) systems with grid. However, more semiconductor components are needed to obtain a higher voltage gain, which results in increased losses. This brief proposes a novel non-isolated cubic boost (NNICB) DC-DC converter for high-voltage PV applications with a wide voltage gain at a lower duty ratio. Compared to traditional high-gain DC-DC converter, the NNICB converter counters the drawbacks of increased component count and high voltage stress. The NNICB DC-DC converter has a continuous source current for PV applications with low-voltage stress across the diodes and switches. A detailed steady-state analysis of the NNICB topology is carried out for the ideal and non-ideal models, and their corresponding voltage gain equations are computed. Furthermore, the analysis is performed using MATLAB/Simulink and is validated using a 230 W laboratory prototype. The experimental results show that the efficiency of the proposed NNICB topology is 94.42% with a voltage gain of 10.5 at 45% duty ratio. This proves the superior performance of the proposed novel converter in comparison with the existing topologies.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5014-5018"},"PeriodicalIF":4.0,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141866118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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