Pub Date : 2024-09-26DOI: 10.1109/TCSII.2024.3462215
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3462215","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3462215","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 10","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142328374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/TCSII.2024.3462211
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3462211","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3462211","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 10","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695795","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142324351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-24DOI: 10.1109/TCSII.2024.3466902
Chao-Yen Hsu;Tai-Cheng Lee
This brief presents a nested ring amplifier with dynamic-cascode-bias and gain-boosting techniques. The proposed amplifier achieves a gain of 90 dB while preserving the high-slew capability. The amplifier is employed in a MDAC for a calibration-free 11-bit 1-GS/s single-channel pipelined ADC. Furthermore, the proposed biasing circuits are utilized to alleviate PVT sensitivity. Fabricated in a 28-nm CMOS technology, the ADC achieves a 61.72-dB SFDR and 53.52-dB SNDR at a Nyquist input, while consuming 14.7 mW from a 1-V supply and yielding Schreier and Walden figure-of-merit (FoM) values of 159 dB and 37.9 fJ/conv.-step, respectively.
{"title":"A Calibration-Free 9.3-ENOB 1-GS/s Pipelined ADC With PVT-Insensitive Nested Ring Amplifiers","authors":"Chao-Yen Hsu;Tai-Cheng Lee","doi":"10.1109/TCSII.2024.3466902","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3466902","url":null,"abstract":"This brief presents a nested ring amplifier with dynamic-cascode-bias and gain-boosting techniques. The proposed amplifier achieves a gain of 90 dB while preserving the high-slew capability. The amplifier is employed in a MDAC for a calibration-free 11-bit 1-GS/s single-channel pipelined ADC. Furthermore, the proposed biasing circuits are utilized to alleviate PVT sensitivity. Fabricated in a 28-nm CMOS technology, the ADC achieves a 61.72-dB SFDR and 53.52-dB SNDR at a Nyquist input, while consuming 14.7 mW from a 1-V supply and yielding Schreier and Walden figure-of-merit (FoM) values of 159 dB and 37.9 fJ/conv.-step, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"28-32"},"PeriodicalIF":4.0,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chimera states have attracted significant research interest due to their potential in modeling brain network functionality. Memristive nano-crossbars, known for their energy efficiency, massive parallelism, and synaptic-like properties, serve as a promising coupling medium in brain-inspired applications. The operation of these devices is strongly dictated by the non-linear mechanisms of memristor devices when studying synchronization phenomena. Expanding upon our previous work, which explored sneak-path currents in Chimera states, this study investigates the impact of fabricated Silicon Nitride (SiN) devices on the dynamics of Chua circuit (CC) networks. We conducted experimental evaluations to confirm the ability of SiN devices to retain their resistance state, thereby ensuring consistency in the crossbar array, a critical factor in maintaining chimera states during experiments. We employed an exponential memristor model to further investigate the non-linear dynamics within the CC network. Our results not only confirm the formation of various synchronization structures, such as chimera states and full chaotic synchronization but also reveal the intriguing formation of phase-lag structures. These structures, induced by the SiN-fitted model, exhibit distinctive characteristics marked by subtle and non-linear coupling behaviors, particularly evident at near-zero voltages. After analyzing our results, we present a comprehensive phase-parametric regime map, obtained by varying the coupling strength bifurcation parameter. This map provides valuable insights into the mechanisms governing the dynamics of CC networks equipepd with SiN-based memristor nanodevices, which have proven capable of capturing the complex dynamics of chimera states.
{"title":"Experimental Evaluation of Silicon Nitride Memristors as Coupling Elements for Chimera States in Chaotic Oscillator Networks","authors":"Karolos-Alexandros Tsakalos;Vasileios Ntinas;Nikolaos Vasileiadis;Astero Provata;Panagiotis Dimitrakis;Georgios Ch. Sirakoulis","doi":"10.1109/TCSII.2024.3466963","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3466963","url":null,"abstract":"Chimera states have attracted significant research interest due to their potential in modeling brain network functionality. Memristive nano-crossbars, known for their energy efficiency, massive parallelism, and synaptic-like properties, serve as a promising coupling medium in brain-inspired applications. The operation of these devices is strongly dictated by the non-linear mechanisms of memristor devices when studying synchronization phenomena. Expanding upon our previous work, which explored sneak-path currents in Chimera states, this study investigates the impact of fabricated Silicon Nitride (SiN) devices on the dynamics of Chua circuit (CC) networks. We conducted experimental evaluations to confirm the ability of SiN devices to retain their resistance state, thereby ensuring consistency in the crossbar array, a critical factor in maintaining chimera states during experiments. We employed an exponential memristor model to further investigate the non-linear dynamics within the CC network. Our results not only confirm the formation of various synchronization structures, such as chimera states and full chaotic synchronization but also reveal the intriguing formation of phase-lag structures. These structures, induced by the SiN-fitted model, exhibit distinctive characteristics marked by subtle and non-linear coupling behaviors, particularly evident at near-zero voltages. After analyzing our results, we present a comprehensive phase-parametric regime map, obtained by varying the coupling strength bifurcation parameter. This map provides valuable insights into the mechanisms governing the dynamics of CC networks equipepd with SiN-based memristor nanodevices, which have proven capable of capturing the complex dynamics of chimera states.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"33-37"},"PeriodicalIF":4.0,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-23DOI: 10.1109/TCSII.2024.3465832
Weidong Xue;Xinwei Yu;Yisen Zhang;Junyan Ren
This brief introduces a 24V-to-1V hybrid converter with low-voltage power switches. By incorporating three flying capacitors in series with a two-phase switched-inductor, the proposed converter effectively functions as a 4.8V-to-1V converter. Thus, a high-voltage design is realized with low-voltage transistors known for their excellent figure of merit. As a result, the hybrid converter achieves an effective duty cycle five times higher and a better conversion efficiency compared with a double step-down converter (DSD) and a double series-capacitor converter (DSCBC) under identical power switch sizes and working conditions. The circuit is designed using a 0.15- $mu $ m Bipolar-CMOS-DMOS (BCD) process to achieve a conversion from 24 V to 1 V. It can support a load current range of 200 mA to 6 A, with each sub-converter operating at a frequency of 1-MHz. Post-layout simulations show a peak power efficiency of 90.07% under a 2-A current load, with an efficiency of 85% even at a load of 6-A.
{"title":"A 24V-to-1V Triple Series-Capacitor Buck Converter With Low-Voltage Power Switches","authors":"Weidong Xue;Xinwei Yu;Yisen Zhang;Junyan Ren","doi":"10.1109/TCSII.2024.3465832","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3465832","url":null,"abstract":"This brief introduces a 24V-to-1V hybrid converter with low-voltage power switches. By incorporating three flying capacitors in series with a two-phase switched-inductor, the proposed converter effectively functions as a 4.8V-to-1V converter. Thus, a high-voltage design is realized with low-voltage transistors known for their excellent figure of merit. As a result, the hybrid converter achieves an effective duty cycle five times higher and a better conversion efficiency compared with a double step-down converter (DSD) and a double series-capacitor converter (DSCBC) under identical power switch sizes and working conditions. The circuit is designed using a 0.15-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m Bipolar-CMOS-DMOS (BCD) process to achieve a conversion from 24 V to 1 V. It can support a load current range of 200 mA to 6 A, with each sub-converter operating at a frequency of 1-MHz. Post-layout simulations show a peak power efficiency of 90.07% under a 2-A current load, with an efficiency of 85% even at a load of 6-A.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"308-312"},"PeriodicalIF":4.0,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief introduces a multi-level phase-change memory (PCM) readout circuit that realizes a true M-metric readout scheme that inherently has a wide dynamic input range. In order to overcome the limited readout speed of a basic M-metric scheme that draws a small current through a PCM cell over a large bit-line capacitance and senses the voltage, we propose an opamp-less M-metric readout circuit that drives the bit-line in a successive approximation manner with a comparator-based push-pull driver (CPPD). The bit-line driving speed of the proposed readout circuit is comparable with that of a conventional voltage driver, but the power consumption is greatly reduced owing to the absence of a power hungry opamp. The prototype design achieves a full 6-bit linearity and 245-uW power consumption at a 270-ns readout speed.
{"title":"An M-Metric Readout Circuit for MLC Phase-Change Memory With a Comparator-Based Push-Pull Bit-Line Driver","authors":"Ji-Wook Kwon;Dong-Hwan Jin;Min-Jae Seo;Seung-Tak Ryu","doi":"10.1109/TCSII.2024.3465888","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3465888","url":null,"abstract":"This brief introduces a multi-level phase-change memory (PCM) readout circuit that realizes a true M-metric readout scheme that inherently has a wide dynamic input range. In order to overcome the limited readout speed of a basic M-metric scheme that draws a small current through a PCM cell over a large bit-line capacitance and senses the voltage, we propose an opamp-less M-metric readout circuit that drives the bit-line in a successive approximation manner with a comparator-based push-pull driver (CPPD). The bit-line driving speed of the proposed readout circuit is comparable with that of a conventional voltage driver, but the power consumption is greatly reduced owing to the absence of a power hungry opamp. The prototype design achieves a full 6-bit linearity and 245-uW power consumption at a 270-ns readout speed.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4658-4662"},"PeriodicalIF":4.0,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-20DOI: 10.1109/TCSII.2024.3465273
Khalid Javeed;David Gregg
The Number Theoretic Transform (NTT) is a central primitive to compute polynomial multiplication in a finite ring for both post-quantum cryptography (PQC) and fully homomorphic encryption (FHE) schemes. This brief presents a novel, efficient NTT hardware architecture suitable for CRYSTALS-Kyber, one of the NIST PQC standards. It is based on a new novel unified butterfly unit (UBU) developed by combining interleaved multiplication, radix-4, and resource-sharing strategies. This unit computes all butterfly operations for any generic prime modulus value and is re-configurable to any modulus length. In the proposed NTT architecture, multiple UBUs are deployed, demonstrating an area-time tradeoff. UBU and NTT architectures are synthesized and implemented over the Xilinix Artix-7 FPGA platform and results are shown for different performance evaluation metrics. The implementation results show our lightweight and high-speed designs achieve up to $5.6times $ and $7times $ improvements in resource consumption and efficiency, respectively. To the authors’ knowledge, it is the first generic NTT architecture based on interleaved multiplication approaches.
{"title":"Efficient Number Theoretic Transform Architecture for CRYSTALS-Kyber","authors":"Khalid Javeed;David Gregg","doi":"10.1109/TCSII.2024.3465273","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3465273","url":null,"abstract":"The Number Theoretic Transform (NTT) is a central primitive to compute polynomial multiplication in a finite ring for both post-quantum cryptography (PQC) and fully homomorphic encryption (FHE) schemes. This brief presents a novel, efficient NTT hardware architecture suitable for CRYSTALS-Kyber, one of the NIST PQC standards. It is based on a new novel unified butterfly unit (UBU) developed by combining interleaved multiplication, radix-4, and resource-sharing strategies. This unit computes all butterfly operations for any generic prime modulus value and is re-configurable to any modulus length. In the proposed NTT architecture, multiple UBUs are deployed, demonstrating an area-time tradeoff. UBU and NTT architectures are synthesized and implemented over the Xilinix Artix-7 FPGA platform and results are shown for different performance evaluation metrics. The implementation results show our lightweight and high-speed designs achieve up to \u0000<inline-formula> <tex-math>$5.6times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$7times $ </tex-math></inline-formula>\u0000 improvements in resource consumption and efficiency, respectively. To the authors’ knowledge, it is the first generic NTT architecture based on interleaved multiplication approaches.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"263-267"},"PeriodicalIF":4.0,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1109/TCSII.2024.3463200
Wenyue Zhang;Pingcheng Dong;Lei Chen;Zhengyu Ma;Fengwei An
Semi-global matching (SGM) is a low-cost method suitable for hardware implementation, while it suffers from significant memory consumption. This brief presents a stereo-vision processor that leverages a min-pooling cost aggregation method for SGM. The min-pooling method addresses this issue by eliminating redundant values and employing an up-sampling technique to restore the original size without requiring clock domain crossing. As a result, this method effectively reduces memory usage by almost half, leading to a significant improvement in large-scale depth measurement. The experimental results demonstrate that the min-pooling method enhances the continuity of disparity maps, particularly in areas with less texture, by capturing more global information and reducing noise and discontinuities. Evaluations on the Middlebury and KITTI datasets show an average accuracy of 12.19% and 5.3%, respectively, indicating a more pronounced impact on the Middlebury dataset. Resource utilization analysis reveals a 1.6-fold increase in LUT usage and a 1.5-fold increase in register usage with min-pooling, while memory size effectively reduces memory usage by 41.2% compared to the method without min-pooling.
{"title":"Min-Pooling Cost Aggregation for Semi-Global Matching of Stereo Vision Processor","authors":"Wenyue Zhang;Pingcheng Dong;Lei Chen;Zhengyu Ma;Fengwei An","doi":"10.1109/TCSII.2024.3463200","DOIUrl":"10.1109/TCSII.2024.3463200","url":null,"abstract":"Semi-global matching (SGM) is a low-cost method suitable for hardware implementation, while it suffers from significant memory consumption. This brief presents a stereo-vision processor that leverages a min-pooling cost aggregation method for SGM. The min-pooling method addresses this issue by eliminating redundant values and employing an up-sampling technique to restore the original size without requiring clock domain crossing. As a result, this method effectively reduces memory usage by almost half, leading to a significant improvement in large-scale depth measurement. The experimental results demonstrate that the min-pooling method enhances the continuity of disparity maps, particularly in areas with less texture, by capturing more global information and reducing noise and discontinuities. Evaluations on the Middlebury and KITTI datasets show an average accuracy of 12.19% and 5.3%, respectively, indicating a more pronounced impact on the Middlebury dataset. Resource utilization analysis reveals a 1.6-fold increase in LUT usage and a 1.5-fold increase in register usage with min-pooling, while memory size effectively reduces memory usage by 41.2% compared to the method without min-pooling.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"258-262"},"PeriodicalIF":4.0,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142268059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-17DOI: 10.1109/TCSII.2024.3462560
Rujian Cao;Zhongyu Zhao;Ka-Fai Un;Wei-Han Yu;Rui P. Martins;Pui-In Mak
Dataflow management provides limited performance improvement to the transformer model due to its lesser weight reuse than the convolution neural network. The cosFormer reduced computational complexity while achieving comparable performance to the vanilla transformer for natural language processing tasks. However, the unstructured sparsity in the cosFormer makes it a challenge to be implemented efficiently. This brief proposes a parallel unstructured sparsity handling (PUSH) scheme to compute sparse-dense matrix multiplication (SDMM) efficiently. It transforms unstructured sparsity into structured sparsity and reduces the total memory access by balancing the memory accesses of the sparse and dense matrices in the SDMM. We also employ unstructured weight pruning cooperating with PUSH to further increase the structured sparsity of the model. Through verification on an FPGA platform, the proposed accelerator achieves a throughput of 2.82 TOPS and an energy efficiency of 144.8 GOPs/W for HotpotQA dataset with long sequences.
{"title":"An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications","authors":"Rujian Cao;Zhongyu Zhao;Ka-Fai Un;Wei-Han Yu;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2024.3462560","DOIUrl":"10.1109/TCSII.2024.3462560","url":null,"abstract":"Dataflow management provides limited performance improvement to the transformer model due to its lesser weight reuse than the convolution neural network. The cosFormer reduced computational complexity while achieving comparable performance to the vanilla transformer for natural language processing tasks. However, the unstructured sparsity in the cosFormer makes it a challenge to be implemented efficiently. This brief proposes a parallel unstructured sparsity handling (PUSH) scheme to compute sparse-dense matrix multiplication (SDMM) efficiently. It transforms unstructured sparsity into structured sparsity and reduces the total memory access by balancing the memory accesses of the sparse and dense matrices in the SDMM. We also employ unstructured weight pruning cooperating with PUSH to further increase the structured sparsity of the model. Through verification on an FPGA platform, the proposed accelerator achieves a throughput of 2.82 TOPS and an energy efficiency of 144.8 GOPs/W for HotpotQA dataset with long sequences.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4688-4692"},"PeriodicalIF":4.0,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142268060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：