Pub Date : 2025-08-25DOI: 10.1109/TCSII.2025.3602634
Jiayu Kuang;Mingyi Chen
Multi-channel multiplexing front-ends based on current domain-frequency division multiplexing (CD-FDM) can alleviate the contradiction between higher single-channel power and the number of channels. Direct digital conversion (DDC) architecture eliminates the amplification stage, saving power consumption and area. However, research on multi-channel DDC is still lacking up to date. This brief demonstrates a four-channel CD-FDM DDC front-end for the first time. The prototype was fabricated in a 180 nm BCD process, occupying a core area of 1.602 mm2. The measurement shows a total harmonic distortion (THD) of 0.073% at a 260 mVpp input. The signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) are 54.55 dB and 62.52 dB, respectively. The integrated noise from 0.5 Hz to 9.77 kHz is measured at $5.79~mu $ Vrms, corresponding to a 9.34 noise efficiency factor (NEF). The experimental results demonstrate it to be a promising candidate for multi-channel artifacts-tolerant front-ends with high compactness as well as high energy efficiency.
{"title":"A Multi-Channel Direct-Digital-Conversion Front-End Based on Current-Domain Frequency Division Multiplexing","authors":"Jiayu Kuang;Mingyi Chen","doi":"10.1109/TCSII.2025.3602634","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3602634","url":null,"abstract":"Multi-channel multiplexing front-ends based on current domain-frequency division multiplexing (CD-FDM) can alleviate the contradiction between higher single-channel power and the number of channels. Direct digital conversion (DDC) architecture eliminates the amplification stage, saving power consumption and area. However, research on multi-channel DDC is still lacking up to date. This brief demonstrates a four-channel CD-FDM DDC front-end for the first time. The prototype was fabricated in a 180 nm BCD process, occupying a core area of 1.602 mm2. The measurement shows a total harmonic distortion (THD) of 0.073% at a 260 mVpp input. The signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) are 54.55 dB and 62.52 dB, respectively. The integrated noise from 0.5 Hz to 9.77 kHz is measured at <inline-formula> <tex-math>$5.79~mu $ </tex-math></inline-formula> Vrms, corresponding to a 9.34 noise efficiency factor (NEF). The experimental results demonstrate it to be a promising candidate for multi-channel artifacts-tolerant front-ends with high compactness as well as high energy efficiency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1373-1377"},"PeriodicalIF":4.9,"publicationDate":"2025-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-21DOI: 10.1109/TCSII.2025.3601095
Mingrui Zhang;Xuguang Hu;Jingyu Wang
This brief presents a signal processing system and its optimize control strategy for power systems. The proposed approach addresses the challenges of increased computational energy consumption and unbalanced processing task allocation. Firstly, a joint edge collaboration and relay assistance signal processing system architecture for power systems is proposed to address the issue of uneven signal processing task allocation. Secondly, a five-slot signal transmission architecture based on non-orthogonal multiple access technology is proposed, along with a method for representing signal processing costs, which solves the problem of signal processing cost quantification. Thirdly, a collaboration assistance computing and resource allocation algorithm is proposed to minimize signal processing costs. Finally, the proposed signal processing system is tested on a power system in China. The results demonstrate that it effectively mitigates the uneven resource allocation issue while significantly reducing signal processing costs.
{"title":"Optimal Control for Power System Signal Processing: A Joint Edge Collaboration and Relay Assistance Framework","authors":"Mingrui Zhang;Xuguang Hu;Jingyu Wang","doi":"10.1109/TCSII.2025.3601095","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3601095","url":null,"abstract":"This brief presents a signal processing system and its optimize control strategy for power systems. The proposed approach addresses the challenges of increased computational energy consumption and unbalanced processing task allocation. Firstly, a joint edge collaboration and relay assistance signal processing system architecture for power systems is proposed to address the issue of uneven signal processing task allocation. Secondly, a five-slot signal transmission architecture based on non-orthogonal multiple access technology is proposed, along with a method for representing signal processing costs, which solves the problem of signal processing cost quantification. Thirdly, a collaboration assistance computing and resource allocation algorithm is proposed to minimize signal processing costs. Finally, the proposed signal processing system is tested on a power system in China. The results demonstrate that it effectively mitigates the uneven resource allocation issue while significantly reducing signal processing costs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1463-1467"},"PeriodicalIF":4.9,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145134917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-21DOI: 10.1109/TCSII.2025.3601156
Linlin Nie;Yewei Yu;Miaolei Zhou;Xiuyu Zhang;Chun-Yi Su
This brief addresses the high-precision motion control of piezoelectric micro-positioning stages (PMPSs) subject to time-varying output constraints, input hysteresis nonlinearity, and system uncertainties. The key features of the developed hysteresis-estimator-based adaptive fuzzy control (HEAFC) method are as follows. First, an asymmetric rate-dependent hysteresis operator is used to construct an extended fuzzy input space, enabling a fuzzy dynamic hysteresis estimator (FDHE) for real-time hysteresis estimation via adaptive fuzzy logic. Second, auxiliary functions are embedded into a backstepping-like control framework to explicitly handle time-varying output constraints. Moreover, by leveraging the structural characteristics of fuzzy systems, the HEAFC scheme avoids repeated differentiation or filtering of virtual control laws. This feature can substantially simplify the control structure. The HEAFC method guarantees prespecified constraint satisfaction and high-accuracy trajectory tracking. Lyapunov-based analysis ensures closed-loop stability, and experimental results on a PMPS demonstrate the effectiveness of the HEAFC strategy.
{"title":"Hysteresis-Estimator-Based Adaptive Fuzzy Control for Piezoelectric Micro-Positioning Stage With Time-Varying Output Constraints","authors":"Linlin Nie;Yewei Yu;Miaolei Zhou;Xiuyu Zhang;Chun-Yi Su","doi":"10.1109/TCSII.2025.3601156","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3601156","url":null,"abstract":"This brief addresses the high-precision motion control of piezoelectric micro-positioning stages (PMPSs) subject to time-varying output constraints, input hysteresis nonlinearity, and system uncertainties. The key features of the developed hysteresis-estimator-based adaptive fuzzy control (HEAFC) method are as follows. First, an asymmetric rate-dependent hysteresis operator is used to construct an extended fuzzy input space, enabling a fuzzy dynamic hysteresis estimator (FDHE) for real-time hysteresis estimation via adaptive fuzzy logic. Second, auxiliary functions are embedded into a backstepping-like control framework to explicitly handle time-varying output constraints. Moreover, by leveraging the structural characteristics of fuzzy systems, the HEAFC scheme avoids repeated differentiation or filtering of virtual control laws. This feature can substantially simplify the control structure. The HEAFC method guarantees prespecified constraint satisfaction and high-accuracy trajectory tracking. Lyapunov-based analysis ensures closed-loop stability, and experimental results on a PMPS demonstrate the effectiveness of the HEAFC strategy.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1418-1422"},"PeriodicalIF":4.9,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-19DOI: 10.1109/TCSII.2025.3600432
Xiong Yang;Ding Wang
This brief investigates a decentralized event-driven control (EDC) problem of multi-machine power systems having asymmetric constraints imposed on inputs. Initially, the decentralized input-constrained EDC problem is transformed into a set of input-unconstrained optimal EDC subproblems by introducing enhanced cost functions for nominal subsystems. Then, with the construction of dynamic event-triggering mechanisms, the event-driven Hamilton-Jacobi-Bellman equations (ED-HJBEs) are derived for these subproblems. To approximately solve these ED-HJBEs, only critic neural networks are utilized in the reinforcement learning framework, and their weights are updated via the gradient descent approach. After that, based on Lyapunov method, uniform ultimate boundedness of the closed-loop multi-machine power systems is established. Finally, simulations are conducted on a two-machine power system to validate the developed decentralized EDC policy.
{"title":"Reinforcement Learning for Dynamic Event-Driven Control of Multi-Machine Power Systems","authors":"Xiong Yang;Ding Wang","doi":"10.1109/TCSII.2025.3600432","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3600432","url":null,"abstract":"This brief investigates a decentralized event-driven control (EDC) problem of multi-machine power systems having asymmetric constraints imposed on inputs. Initially, the decentralized input-constrained EDC problem is transformed into a set of input-unconstrained optimal EDC subproblems by introducing enhanced cost functions for nominal subsystems. Then, with the construction of dynamic event-triggering mechanisms, the event-driven Hamilton-Jacobi-Bellman equations (ED-HJBEs) are derived for these subproblems. To approximately solve these ED-HJBEs, only critic neural networks are utilized in the reinforcement learning framework, and their weights are updated via the gradient descent approach. After that, based on Lyapunov method, uniform ultimate boundedness of the closed-loop multi-machine power systems is established. Finally, simulations are conducted on a two-machine power system to validate the developed decentralized EDC policy.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1413-1417"},"PeriodicalIF":4.9,"publicationDate":"2025-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-18DOI: 10.1109/TCSII.2025.3599886
Donghai Zhu;Xiangjinwen Li;Shiying Zhou;Xuejiao Zhong;Xudong Zou;Yong Kang
In this brief, the power decoupling mechanism of grid-forming converter is analyzed, which indicates that the suitable voltage compensation is crucial for decoupling. Then, an optimized power decoupling control is proposed, which can provide positive or negative voltage compensation for decoupling, resulting in efficient power decoupling under different R/X ratios of grid impedance.
{"title":"Optimized Power Decoupling Control for Grid-Forming Converter Under Different R/X Ratios of Grid Impedance","authors":"Donghai Zhu;Xiangjinwen Li;Shiying Zhou;Xuejiao Zhong;Xudong Zou;Yong Kang","doi":"10.1109/TCSII.2025.3599886","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3599886","url":null,"abstract":"In this brief, the power decoupling mechanism of grid-forming converter is analyzed, which indicates that the suitable voltage compensation is crucial for decoupling. Then, an optimized power decoupling control is proposed, which can provide positive or negative voltage compensation for decoupling, resulting in efficient power decoupling under different R/X ratios of grid impedance.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 12","pages":"2052-2056"},"PeriodicalIF":4.9,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145595102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-14DOI: 10.1109/TCSII.2025.3598759
Ziying Xie;Tianchi Ye;Ziyue Dang;Xi Xiao;Min Tan
Pulse-width-modulated (PWM) thermo-optic tuning in silicon photonics calls for a power supply featuring high-speed PWM power output with short settling time, high efficiency, and a compact size. However, the transient response of the traditional digital low-dropout regulators (DLDOs) is limited by the closed-loop response, which makes it difficult to meet the speed requirements of the PWM power output. This brief presents a State-Switching DLDO (SS-DLDO), specially optimized for PWM thermo-optic tuning. Two state selectors, controlled by a PWM signal, are inserted into the SS-DLDO structure to control the connections and operational states of the DLDO asynchronously. This enables the speed of PWM tuning to be decoupled from the feedback loop of the DLDO. The proposed design is fabricated in a 65nm CMOS process with an active area of 0.00634 mm2. Measurement results show that the rising-edge settling time and falling-edge settling time of the PWM power output are 16.3 ns and 14 ns, respectively, which effectively reduces the limit of the edge settling time to the achievable PWM duty cycle range. Under a 2 MHz PWM frequency, this design can achieve PWM duty cycles ranging from 5.92% to 97.2%, corresponding to output power ranging from 1.47 mW to 24.12 mW.
{"title":"A State-Switching Digital LDO for PWM Thermo-Optic Tuning in Silicon Photonics","authors":"Ziying Xie;Tianchi Ye;Ziyue Dang;Xi Xiao;Min Tan","doi":"10.1109/TCSII.2025.3598759","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3598759","url":null,"abstract":"Pulse-width-modulated (PWM) thermo-optic tuning in silicon photonics calls for a power supply featuring high-speed PWM power output with short settling time, high efficiency, and a compact size. However, the transient response of the traditional digital low-dropout regulators (DLDOs) is limited by the closed-loop response, which makes it difficult to meet the speed requirements of the PWM power output. This brief presents a State-Switching DLDO (SS-DLDO), specially optimized for PWM thermo-optic tuning. Two state selectors, controlled by a PWM signal, are inserted into the SS-DLDO structure to control the connections and operational states of the DLDO asynchronously. This enables the speed of PWM tuning to be decoupled from the feedback loop of the DLDO. The proposed design is fabricated in a 65nm CMOS process with an active area of 0.00634 mm2. Measurement results show that the rising-edge settling time and falling-edge settling time of the PWM power output are 16.3 ns and 14 ns, respectively, which effectively reduces the limit of the edge settling time to the achievable PWM duty cycle range. Under a 2 MHz PWM frequency, this design can achieve PWM duty cycles ranging from 5.92% to 97.2%, corresponding to output power ranging from 1.47 mW to 24.12 mW.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1458-1462"},"PeriodicalIF":4.9,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145134918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-12DOI: 10.1109/TCSII.2025.3598216
Xinyue Cao;Ling Zhao;Yuanqing Xia;Hongjiu Yang
In this brief, hierarchical fusion estimation with feedback is researched in clustered sensor networks with leader and subordinate sensors. A local estimator is designed to obtain local estimates using feedback fusion estimates in each sensor. A two-layer fusion estimator is developed to achieve fusion estimates for improving estimation accuracy in each leader sensor. The first layer fusion estimator is proposed combining local estimates within the same cluster based on both current and past local estimation accuracy under inaccurate noise covariance matrices. The second layer fusion estimator is designed by fusing the first layer fusion estimates from all leader sensors. Validity of the hierarchical fusion estimation with feedback is shown based on a maneuvering target tracking system.
{"title":"Hierarchical Fusion Estimation With Feedback for Clustered Sensor Networks Subject to Leader and Subordinate Sensors","authors":"Xinyue Cao;Ling Zhao;Yuanqing Xia;Hongjiu Yang","doi":"10.1109/TCSII.2025.3598216","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3598216","url":null,"abstract":"In this brief, hierarchical fusion estimation with feedback is researched in clustered sensor networks with leader and subordinate sensors. A local estimator is designed to obtain local estimates using feedback fusion estimates in each sensor. A two-layer fusion estimator is developed to achieve fusion estimates for improving estimation accuracy in each leader sensor. The first layer fusion estimator is proposed combining local estimates within the same cluster based on both current and past local estimation accuracy under inaccurate noise covariance matrices. The second layer fusion estimator is designed by fusing the first layer fusion estimates from all leader sensors. Validity of the hierarchical fusion estimation with feedback is shown based on a maneuvering target tracking system.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1403-1407"},"PeriodicalIF":4.9,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-08DOI: 10.1109/TCSII.2025.3597263
Wei Xie;Toshio Eisaka
The main goal of this brief is to present a methodology to design multi-objective $mathrm{H}_{infty } $ /r -stability interval estimation for linear discrete-time systems affected by bounded, but unknown disturbances. Compared with $mathrm{H}_{infty } $ norm criterion that is used to reject the influence of external disturbances on the output under the worst scenario, multi-objective $mathrm{H}_{infty } $ /r-stability interval observer takes pole-placement into account, the poles of the system matrix of the observes are configured as close as possible to the origin. This is to ensure not only a relatively fast convergence characteristic but also the minimum interval width. Finally, an illustrative example of a DC servo motor highlights the performance of our methodology.
{"title":"Multi-Objective H∞/r-Stability Optimal Interval Estimation for Linear Discrete-Time Systems and Application to DC Servo Motor","authors":"Wei Xie;Toshio Eisaka","doi":"10.1109/TCSII.2025.3597263","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3597263","url":null,"abstract":"The main goal of this brief is to present a methodology to design multi-objective <inline-formula> <tex-math>$mathrm{H}_{infty } $ </tex-math></inline-formula>/r -stability interval estimation for linear discrete-time systems affected by bounded, but unknown disturbances. Compared with <inline-formula> <tex-math>$mathrm{H}_{infty } $ </tex-math></inline-formula> norm criterion that is used to reject the influence of external disturbances on the output under the worst scenario, multi-objective <inline-formula> <tex-math>$mathrm{H}_{infty } $ </tex-math></inline-formula>/r-stability interval observer takes pole-placement into account, the poles of the system matrix of the observes are configured as close as possible to the origin. This is to ensure not only a relatively fast convergence characteristic but also the minimum interval width. Finally, an illustrative example of a DC servo motor highlights the performance of our methodology.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1398-1402"},"PeriodicalIF":4.9,"publicationDate":"2025-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-07DOI: 10.1109/TCSII.2025.3596708
Bram Veraverbeke;Filip Tavernier
Dopant freeze-out severely increases the bulk resistance of cryogenic bulk CMOS transistors by up to $10{^{{6}}} {times }$ at 4.2K compared to room temperature. This brief describes, for the first time in the literature, how this increased bulk resistance introduces a memory effect in the latch of dynamic comparators, which leads to hysteresis. To measure this hysteresis reliably in the presence of noise, a statistical characterization procedure is developed. For a 40nm bulk CMOS strongARM comparator with an input-referred noise voltage of 348$mu $ VRMS, a hysteresis voltage >898$mu $ V is measured at 6K, substantially deteriorating the precision. Therefore, this brief introduces a triple tail comparator with capacitive over-neutralization to increase the preamplification gain, suppressing the hysteresis >$6{times }$ to only 141$mu $ V.
{"title":"A Cryo-CMOS Triple Tail Comparator With Capacitive Over-Neutralization to Suppress Freeze-Out Induced Hysteresis","authors":"Bram Veraverbeke;Filip Tavernier","doi":"10.1109/TCSII.2025.3596708","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3596708","url":null,"abstract":"Dopant freeze-out severely increases the bulk resistance of cryogenic bulk CMOS transistors by up to <inline-formula> <tex-math>$10{^{{6}}} {times }$ </tex-math></inline-formula> at 4.2K compared to room temperature. This brief describes, for the first time in the literature, how this increased bulk resistance introduces a memory effect in the latch of dynamic comparators, which leads to hysteresis. To measure this hysteresis reliably in the presence of noise, a statistical characterization procedure is developed. For a 40nm bulk CMOS strongARM comparator with an input-referred noise voltage of 348<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> VRMS, a hysteresis voltage >898<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> V is measured at 6K, substantially deteriorating the precision. Therefore, this brief introduces a triple tail comparator with capacitive over-neutralization to increase the preamplification gain, suppressing the hysteresis ><inline-formula> <tex-math>$6{times }$ </tex-math></inline-formula> to only 141<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> V.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1358-1362"},"PeriodicalIF":4.9,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief introduces an integrated configurable frequency-modulated continuous wave (FMCW) radar baseband SoC, which integrates a baseband accelerator in 40-nm CMOS technology. This brief exhibits notable advantages in terms of miniaturization, configurability, and real-time performance. To enhance the real-time performance of baseband signal processing, the baseband accelerator employs a pipeline architecture that incorporates specifically designed parallel computation structures for each submodule. Furthermore, this design enables the accelerator to support diverse application scenarios by offering configurable dimensions for fast Fourier transform (FFT), constant false alarm rate (CFAR), and digital beamforming (DBF), along with adjustable parameters for time-frequency domain processing. Board-level testing results indicate that the chip can accurately distinguish targets with varying distances, speeds, and angles. Operating at a system clock frequency of 200 MHz, the processor achieves a frame processing time of 2.79 ms and a power consumption of 492 mW, under the maximum CFAR window configuration and 256 targets.
{"title":"An Integrated Configurable FMCW Radar Baseband SoC in 40-nm CMOS","authors":"Peng Zhang;Bo Wang;Ning Zhang;Pengfei Diao;Qisong Wu;Dixian Zhao","doi":"10.1109/TCSII.2025.3596605","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3596605","url":null,"abstract":"This brief introduces an integrated configurable frequency-modulated continuous wave (FMCW) radar baseband SoC, which integrates a baseband accelerator in 40-nm CMOS technology. This brief exhibits notable advantages in terms of miniaturization, configurability, and real-time performance. To enhance the real-time performance of baseband signal processing, the baseband accelerator employs a pipeline architecture that incorporates specifically designed parallel computation structures for each submodule. Furthermore, this design enables the accelerator to support diverse application scenarios by offering configurable dimensions for fast Fourier transform (FFT), constant false alarm rate (CFAR), and digital beamforming (DBF), along with adjustable parameters for time-frequency domain processing. Board-level testing results indicate that the chip can accurately distinguish targets with varying distances, speeds, and angles. Operating at a system clock frequency of 200 MHz, the processor achieves a frame processing time of 2.79 ms and a power consumption of 492 mW, under the maximum CFAR window configuration and 256 targets.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1438-1442"},"PeriodicalIF":4.9,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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