Pub Date : 2024-10-11DOI: 10.1109/TCSII.2024.3478797
Xiaoyan Diao;Jun Xia;Jinlin Sun;Shihong Ding;Lu Liu
This brief presents a continuous practical terminal sliding mode (CPTSM) control method for precisely regulating the output voltage of boost converters, effectively addressing the converters’ nonlinear and nonminimum phase characteristics. The proposed CPTSM control method starts with the generalized super-twisting extended state observers to estimate the input voltage and load, thereby generating a reference current that adapts to real-time variations of the operating condition. Based on the exact feedback linearization technique, the CPTSM control strategy is developed. The benefits of the proposed strategy lie in its fast transient response and strong robustness. Furthermore, stringent theoretical analysis verifies the CPTSM control system. Finally, simulation and experimental results demonstrate the effectiveness and superiority of the proposed control scheme.
{"title":"Continuous Practical Terminal Sliding Mode Controller for Boost Converters: Design and Experimental Evaluation","authors":"Xiaoyan Diao;Jun Xia;Jinlin Sun;Shihong Ding;Lu Liu","doi":"10.1109/TCSII.2024.3478797","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3478797","url":null,"abstract":"This brief presents a continuous practical terminal sliding mode (CPTSM) control method for precisely regulating the output voltage of boost converters, effectively addressing the converters’ nonlinear and nonminimum phase characteristics. The proposed CPTSM control method starts with the generalized super-twisting extended state observers to estimate the input voltage and load, thereby generating a reference current that adapts to real-time variations of the operating condition. Based on the exact feedback linearization technique, the CPTSM control strategy is developed. The benefits of the proposed strategy lie in its fast transient response and strong robustness. Furthermore, stringent theoretical analysis verifies the CPTSM control system. Finally, simulation and experimental results demonstrate the effectiveness and superiority of the proposed control scheme.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"203-207"},"PeriodicalIF":4.0,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel background calibration technique for timing mismatch in time-interleaved ADCs (TI ADCs) with fast convergence speed is presented in this brief. The proposed calibration applies a customized neural network (NN) to extract the information of timing skews for compensation. Compared to the conventional background methods for calibrating timing mismatches without reference, this brief significantly increases the convergence speed with high accuracy. In comparison with prior NN-based calibration works, this brief could follow the error changes in the background and has stronger robustness, also without any risk of fidelity problem. A 12-bit 3GSps 4-channel TI ADC model with noise and jitter is simulated for verifying the effectiveness of this technique. Simulation results show that the proposed technique could improve the SNDR and SFDR by 7.41dB and 24.73dB respectively, with only 1536 samples for convergence. Off-chip validation with a 12-bit 3GSps 4-channel TI ADC also proves the effectiveness and practicality of this brief.
{"title":"A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs","authors":"Zhifei Lu;Boyuan Zhang;Yutao Peng;Xizhu Peng;He Tang;Jie Pu;Ling Qin;Mingqiang Guo","doi":"10.1109/TCSII.2024.3477463","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3477463","url":null,"abstract":"A novel background calibration technique for timing mismatch in time-interleaved ADCs (TI ADCs) with fast convergence speed is presented in this brief. The proposed calibration applies a customized neural network (NN) to extract the information of timing skews for compensation. Compared to the conventional background methods for calibrating timing mismatches without reference, this brief significantly increases the convergence speed with high accuracy. In comparison with prior NN-based calibration works, this brief could follow the error changes in the background and has stronger robustness, also without any risk of fidelity problem. A 12-bit 3GSps 4-channel TI ADC model with noise and jitter is simulated for verifying the effectiveness of this technique. Simulation results show that the proposed technique could improve the SNDR and SFDR by 7.41dB and 24.73dB respectively, with only 1536 samples for convergence. Off-chip validation with a 12-bit 3GSps 4-channel TI ADC also proves the effectiveness and practicality of this brief.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"48-52"},"PeriodicalIF":4.0,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/TCSII.2024.3474676
Guangyao Li;Hailong Zhang;Yafei Chen;Junchen Xie;Cheol-Hee Jo;Chunbo Zhu;Shumei Cui;Dong-Hee Kim
The inevitable misalignment of magnetic couplers presents a substantial challenge to the power transmission and efficiency of inductive power transfer (IPT) systems. In this brief, an integrated mutually compensated dual receiver (IMCDR) IPT system for automated guided vehicles with high-efficiency constant current (CC) charging over a large misalignment tolerance (MT) range is proposed. The dual-channel receiver comprises two solenoid coils perpendicularly wound to each other to capture the magnetic flux along the y- and z-axes generated by the transmitter. In this way, two mutual inductances with opposite changing trends are utilized to synthesize an equivalent mutual inductance $(M_{mathrm { eq}})$ over an MT range. Further, the proposed IMCDR structure was optimized using the finite element method to obtain the optimal receiver length and $M_{mathrm { eq}}$ fluctuation rate. Finally, a 535-W/85-kHz experimental prototype was conducted. Experimental results showed that the proposed IPT system can maintain the output current fluctuation rate within 5.82% with fixed duty/frequency condition when operating over a 172% MT range, and the system efficiency ranges from 88.42% to 90.67%.
{"title":"An Integrated Mutually Compensatory Dual Receiver for AGV Misalignment-Tolerant IPT Charging","authors":"Guangyao Li;Hailong Zhang;Yafei Chen;Junchen Xie;Cheol-Hee Jo;Chunbo Zhu;Shumei Cui;Dong-Hee Kim","doi":"10.1109/TCSII.2024.3474676","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3474676","url":null,"abstract":"The inevitable misalignment of magnetic couplers presents a substantial challenge to the power transmission and efficiency of inductive power transfer (IPT) systems. In this brief, an integrated mutually compensated dual receiver (IMCDR) IPT system for automated guided vehicles with high-efficiency constant current (CC) charging over a large misalignment tolerance (MT) range is proposed. The dual-channel receiver comprises two solenoid coils perpendicularly wound to each other to capture the magnetic flux along the y- and z-axes generated by the transmitter. In this way, two mutual inductances with opposite changing trends are utilized to synthesize an equivalent mutual inductance \u0000<inline-formula> <tex-math>$(M_{mathrm { eq}})$ </tex-math></inline-formula>\u0000 over an MT range. Further, the proposed IMCDR structure was optimized using the finite element method to obtain the optimal receiver length and \u0000<inline-formula> <tex-math>$M_{mathrm { eq}}$ </tex-math></inline-formula>\u0000 fluctuation rate. Finally, a 535-W/85-kHz experimental prototype was conducted. Experimental results showed that the proposed IPT system can maintain the output current fluctuation rate within 5.82% with fixed duty/frequency condition when operating over a 172% MT range, and the system efficiency ranges from 88.42% to 90.67%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"313-317"},"PeriodicalIF":4.0,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/TCSII.2024.3474700
Jiaxu Cong;Jingyu Wang;Bin Tong;Delong Shang
In the rapidly evolving landscape of the Internet of Things (IoT), efficient and low-power communication solutions with minimal I/O count are essential for the effective connectivity of a multitude of devices. This brief presents Spike Refresh Receiver-Transmitter (SRRT), a novel ultra-low power unidirectional single-wire inter-chip communication protocol designed specifically for IoT applications. The protocol distinguishes continuous identical data through spike refresh and ensures data reliability via stability detection. We conduct theoretical analysis of the SRRT and performed post-layout simulations using layouts generated by ICC. The results show that the SRRT achieves a power consumption of 0.0605mW, a performance of 200Mbps, an energy efficiency of 0.3025pJ/bit, and an area of 0.001508mm2. Additionally, the protocol is validated in a real-world environment using a PCB comprising two FPGAs.
{"title":"SRRT: An Ultra-Low-Power Unidirectional Single-Wire Inter-Chip Communication for IoT","authors":"Jiaxu Cong;Jingyu Wang;Bin Tong;Delong Shang","doi":"10.1109/TCSII.2024.3474700","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3474700","url":null,"abstract":"In the rapidly evolving landscape of the Internet of Things (IoT), efficient and low-power communication solutions with minimal I/O count are essential for the effective connectivity of a multitude of devices. This brief presents Spike Refresh Receiver-Transmitter (SRRT), a novel ultra-low power unidirectional single-wire inter-chip communication protocol designed specifically for IoT applications. The protocol distinguishes continuous identical data through spike refresh and ensures data reliability via stability detection. We conduct theoretical analysis of the SRRT and performed post-layout simulations using layouts generated by ICC. The results show that the SRRT achieves a power consumption of 0.0605mW, a performance of 200Mbps, an energy efficiency of 0.3025pJ/bit, and an area of 0.001508mm2. Additionally, the protocol is validated in a real-world environment using a PCB comprising two FPGAs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"128-132"},"PeriodicalIF":4.0,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-04DOI: 10.1109/TCSII.2024.3474018
Geonwoo Park;Ockgoo Lee;Donggu Im;Ilku Nam
An automatic frequency calibration robust to initial phase error and a phase-noise-enhanced ring oscillator are proposed for frequency synthesizers. The proposed automatic frequency calibration method can quickly determine the desired sub-band tuning curve for a voltage-controlled oscillator by detecting the overshoot voltage of the oscillator control voltage of the frequency synthesizer when an initial phase error occurs between the reference signal and the divided output signal from the oscillator, thereby reducing the locking time of the frequency synthesizer. The proposed ring oscillator uses a differential inverter type delay cell with an input AC-coupled current source for phase noise improvement and low power consumption. For verification, an integer-N frequency synthesizer with the proposed automatic frequency calibration and ring oscillator was fabricated using 65-nm CMOS technology. The implemented frequency synthesizer draws 2.5 mA from a 1-V supply voltage at a 1 GHz carrier frequency. It provides frequency calibration time of less than $3.6~mu $ s, phase noise of –105.5 dBc/Hz at 1 MHz offset frequency of 1 GHz carrier frequency, and figure-of-merit for integrated jitter from 1 kHz to 1 MHz of –231 dBc/Hz.
{"title":"A Frequency Synthesizer With Automatic Frequency Calibration Robust to Initial Phase Error and Phase-Noise Enhanced Ring Oscillator","authors":"Geonwoo Park;Ockgoo Lee;Donggu Im;Ilku Nam","doi":"10.1109/TCSII.2024.3474018","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3474018","url":null,"abstract":"An automatic frequency calibration robust to initial phase error and a phase-noise-enhanced ring oscillator are proposed for frequency synthesizers. The proposed automatic frequency calibration method can quickly determine the desired sub-band tuning curve for a voltage-controlled oscillator by detecting the overshoot voltage of the oscillator control voltage of the frequency synthesizer when an initial phase error occurs between the reference signal and the divided output signal from the oscillator, thereby reducing the locking time of the frequency synthesizer. The proposed ring oscillator uses a differential inverter type delay cell with an input AC-coupled current source for phase noise improvement and low power consumption. For verification, an integer-N frequency synthesizer with the proposed automatic frequency calibration and ring oscillator was fabricated using 65-nm CMOS technology. The implemented frequency synthesizer draws 2.5 mA from a 1-V supply voltage at a 1 GHz carrier frequency. It provides frequency calibration time of less than \u0000<inline-formula> <tex-math>$3.6~mu $ </tex-math></inline-formula>\u0000s, phase noise of –105.5 dBc/Hz at 1 MHz offset frequency of 1 GHz carrier frequency, and figure-of-merit for integrated jitter from 1 kHz to 1 MHz of –231 dBc/Hz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"43-47"},"PeriodicalIF":4.0,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There have been many attempts to emulate extended memristors as models of real-world devices using Graetz diode bridges with capacitive loads and similar techniques. In this brief, these systems are studied comprehensively as special cases of nonlinear resistive two-ports with reactance loads. The conditions that must be satisfied in order to transform a load into a generic memristor are formulated. It is shown that some hitherto published circuits may not automatically satisfy these conditions, so that in general they may not be extended memristors. The relevant circuit theorems are verified by laboratory experiments.
{"title":"Modeling and Emulation of Extended Memristors: Two-Port Approach Revisited","authors":"Dalibor Biolek;Zdeněk Biolek;Zdeněk Kolka;Viera Biolková;Zdeněk Kohl","doi":"10.1109/TCSII.2024.3471689","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3471689","url":null,"abstract":"There have been many attempts to emulate extended memristors as models of real-world devices using Graetz diode bridges with capacitive loads and similar techniques. In this brief, these systems are studied comprehensively as special cases of nonlinear resistive two-ports with reactance loads. The conditions that must be satisfied in order to transform a load into a generic memristor are formulated. It is shown that some hitherto published circuits may not automatically satisfy these conditions, so that in general they may not be extended memristors. The relevant circuit theorems are verified by laboratory experiments.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"298-302"},"PeriodicalIF":4.0,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/TCSII.2024.3470111
Jae-Yun Park;Jae-Won Nam
A qubit-control waveform generator utilizing a 4-channel time-interleaved $Delta Sigma $ DAC is presented. A digital-to-analog converter (DAC) at 4.3 GS/s with an oversampling rate of 8 is fabricated in 65 nm CMOS technology. To enhance the linearity of the DAC, harmonic cancellation is proposed. Time-interleaving is applied in a $Delta Sigma $ modulator to widen the bandwidth. A high operational speed is also achieved through an unrolling technique to the direct digital frequency synthesis (DDFS) digital core. To ensure robustness of the process-voltage-temperature (PVT) variations, temperature-insensitive bias is proposed, with implementation mainly based on digital circuits. The proposed $Delta Sigma $ DAC consumes 256.04 mW of power, and the core area is $0.11~mm^{2}$ . The signal-to-noise distortion ratio (SNDR) and the spurious free dynamic range (SFDR) after enabling harmonic cancellation are respectively 30.62 dB and 47.03 dB at 100 K temperature.
{"title":"A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control","authors":"Jae-Yun Park;Jae-Won Nam","doi":"10.1109/TCSII.2024.3470111","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3470111","url":null,"abstract":"A qubit-control waveform generator utilizing a 4-channel time-interleaved \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 DAC is presented. A digital-to-analog converter (DAC) at 4.3 GS/s with an oversampling rate of 8 is fabricated in 65 nm CMOS technology. To enhance the linearity of the DAC, harmonic cancellation is proposed. Time-interleaving is applied in a \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator to widen the bandwidth. A high operational speed is also achieved through an unrolling technique to the direct digital frequency synthesis (DDFS) digital core. To ensure robustness of the process-voltage-temperature (PVT) variations, temperature-insensitive bias is proposed, with implementation mainly based on digital circuits. The proposed \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 DAC consumes 256.04 mW of power, and the core area is \u0000<inline-formula> <tex-math>$0.11~mm^{2}$ </tex-math></inline-formula>\u0000. The signal-to-noise distortion ratio (SNDR) and the spurious free dynamic range (SFDR) after enabling harmonic cancellation are respectively 30.62 dB and 47.03 dB at 100 K temperature.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4663-4667"},"PeriodicalIF":4.0,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/TCSII.2024.3470833
Mookyoung Yoo;Hyeoktae Son;Kyounghwan Kim;Jihyang Wi;Gibae Nam;Minhyoek Son;Manhyoek Choi;Hyoungho Ko
This brief presents a ping-pong auto-zero (AZ) stabilized multipath fully differential amplifier with a digitally-assisted coarse automatic offset calibration loop. The low-frequency path (LFP) of the multipath amplifier is implemented using ping-pong AZ amplifiers. The continuous-time offset cancellation and the frequency compensation can be obtained with ping-pong AZ scheme. The digitally-assisted automatic offset calibration loops (AOCL) in the LFP and the HFP (high-frequency path) using successive approximation registers (SAR) binary search circuits and current-mode digital-to-analog converters (DAC) can effectively reduce the offsets under large process variations. The AOCL can prevent the output saturation of AZ LFP at zeroing phase, can allow the higher transconductance of the AZ LFP. The higher gain of the AZ LFP can attenuate the low frequency noise of HFP, and the lower overall input referred noise can be achieved. The circuit was fabricated using a 180 nm complementary metal-oxide-semiconductor (CMOS) process and draws $59.9~mu $ A at a supply voltage of 1.8V. The input referred noise is 19.8 nV/ $surd $ Hz. The power-up time is $2.3~mu $ s. The maximum input referred offsets before and after AOCL operation are reduced from $- 740~mu $ V to −276 nV. The unit gain-bandwidth is 3.042 MHz. The power supply rejection ratio (PSRR) and common mode rejection ratio (CMRR) are 111 dB, and 99 dB, respectively.
{"title":"Zero-Drift Fully Differential Amplifier With Ping-Pong Auto-Zero Stabilization and Digitally-Assisted Coarse Automatic Offset Calibration","authors":"Mookyoung Yoo;Hyeoktae Son;Kyounghwan Kim;Jihyang Wi;Gibae Nam;Minhyoek Son;Manhyoek Choi;Hyoungho Ko","doi":"10.1109/TCSII.2024.3470833","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3470833","url":null,"abstract":"This brief presents a ping-pong auto-zero (AZ) stabilized multipath fully differential amplifier with a digitally-assisted coarse automatic offset calibration loop. The low-frequency path (LFP) of the multipath amplifier is implemented using ping-pong AZ amplifiers. The continuous-time offset cancellation and the frequency compensation can be obtained with ping-pong AZ scheme. The digitally-assisted automatic offset calibration loops (AOCL) in the LFP and the HFP (high-frequency path) using successive approximation registers (SAR) binary search circuits and current-mode digital-to-analog converters (DAC) can effectively reduce the offsets under large process variations. The AOCL can prevent the output saturation of AZ LFP at zeroing phase, can allow the higher transconductance of the AZ LFP. The higher gain of the AZ LFP can attenuate the low frequency noise of HFP, and the lower overall input referred noise can be achieved. The circuit was fabricated using a 180 nm complementary metal-oxide-semiconductor (CMOS) process and draws \u0000<inline-formula> <tex-math>$59.9~mu $ </tex-math></inline-formula>\u0000 A at a supply voltage of 1.8V. The input referred noise is 19.8 nV/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000 Hz. The power-up time is \u0000<inline-formula> <tex-math>$2.3~mu $ </tex-math></inline-formula>\u0000 s. The maximum input referred offsets before and after AOCL operation are reduced from \u0000<inline-formula> <tex-math>$- 740~mu $ </tex-math></inline-formula>\u0000 V to −276 nV. The unit gain-bandwidth is 3.042 MHz. The power supply rejection ratio (PSRR) and common mode rejection ratio (CMRR) are 111 dB, and 99 dB, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"38-42"},"PeriodicalIF":4.0,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/TCSII.2024.3462213
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TCSII.2024.3462213","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3462213","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 10","pages":"4606-4606"},"PeriodicalIF":4.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695789","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142328417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dora, a low-latency Field-programmable gate array (FPGA) partial reconfiguration (PR) controller, is proposed in this brief to address the latency challenge encountered by traditional solutions in highly real-time reconfigurable systems. First, based on the constructed refined cost model, key factors for minimizing latency in Host-to-FPGA reconfiguration process are analyzed. Subsequently, utilizing the established producer-consumer model, the reconfiguration mechanism (scatter gather-streaming-based hybrid transmission) and training method (adaptive overclocking of the Internal Configuration Access Port, ICAP) in Dora aim to enhance production of configuration bitstream while achieving efficient consumption. Ultimately, experiments demonstrate that Dora outperforms existing solutions in pivotal aspects: (i) It slashes FPGA resource utilization by over 60% while attaining a reconfiguration rate close to the theoretical peak of 99.6%, (ii) it reduces latency to just 11.1 ms, representing only 2.6% of the latency of the standard Xilinx solution, (iii) additionally, its open-source nature fosters broader adoption and utilization among the research community.
{"title":"Dora: A Low-Latency Partial Reconfiguration Controller for Reconfigurable System","authors":"Guosheng Zhang;Lisong Shao;Hanqian Wu;Xiaotian Gu;Xinyi Zhang","doi":"10.1109/TCSII.2024.3468317","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3468317","url":null,"abstract":"Dora, a low-latency Field-programmable gate array (FPGA) partial reconfiguration (PR) controller, is proposed in this brief to address the latency challenge encountered by traditional solutions in highly real-time reconfigurable systems. First, based on the constructed refined cost model, key factors for minimizing latency in Host-to-FPGA reconfiguration process are analyzed. Subsequently, utilizing the established producer-consumer model, the reconfiguration mechanism (scatter gather-streaming-based hybrid transmission) and training method (adaptive overclocking of the Internal Configuration Access Port, ICAP) in Dora aim to enhance production of configuration bitstream while achieving efficient consumption. Ultimately, experiments demonstrate that Dora outperforms existing solutions in pivotal aspects: (i) It slashes FPGA resource utilization by over 60% while attaining a reconfiguration rate close to the theoretical peak of 99.6%, (ii) it reduces latency to just 11.1 ms, representing only 2.6% of the latency of the standard Xilinx solution, (iii) additionally, its open-source nature fosters broader adoption and utilization among the research community.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"268-272"},"PeriodicalIF":4.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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