This brief addresses the finite-time annular domain (FTAD) $H_{2}/H_{infty }$ filtering problem for linear stochastic Markovian jump systems (SMJSs) subject to Brownian motion and Poisson noise. By adopting the mode-dependent parameter approach and leveraging the reverse differential Gronwall inequality and the Itô-Levy formula, novel sufficient conditions ensuring the existence of such $H_{2}/H_{infty }$ filter are established. This condition is much less conservative, thus greatly extending the scope of solutions. Additionally, an algorithm is designed to determine the parameter ranges and show the relationship between $H_{2}$ and $H_{infty }$ performance metrics. Finally, a PWM-driven circuit is used to demonstrate the practicality of the proposed approach.
{"title":"Finite-Time Annular Domain H2/H∞ Filtering for Stochastic Markovian Jump Systems and Its Applications in PWM Circuits","authors":"Zhiguo Yan;Zhongxin Tong;Guolin Hu;Yunxia Song;Wenhai Qi;Jun Cheng","doi":"10.1109/TCSII.2025.3608010","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3608010","url":null,"abstract":"This brief addresses the finite-time annular domain (FTAD) <inline-formula> <tex-math>$H_{2}/H_{infty }$ </tex-math></inline-formula> filtering problem for linear stochastic Markovian jump systems (SMJSs) subject to Brownian motion and Poisson noise. By adopting the mode-dependent parameter approach and leveraging the reverse differential Gronwall inequality and the Itô-Levy formula, novel sufficient conditions ensuring the existence of such <inline-formula> <tex-math>$H_{2}/H_{infty }$ </tex-math></inline-formula> filter are established. This condition is much less conservative, thus greatly extending the scope of solutions. Additionally, an algorithm is designed to determine the parameter ranges and show the relationship between <inline-formula> <tex-math>$H_{2}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula> performance metrics. Finally, a PWM-driven circuit is used to demonstrate the practicality of the proposed approach.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1735-1739"},"PeriodicalIF":4.9,"publicationDate":"2025-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-09DOI: 10.1109/TCSII.2025.3607681
Nimrod Ginzberg;Emanuel Cohen
This work presents a new backoff efficiency enhancement technique for switched-capacitor power amplifiers (SCPA) that employs dynamic core size resizing enabled by a high-impedance (Hi-Z) control state. The SCPA unit cells’ size is the dynamically adjusted according to the instantaneous output power, which broadens the backoff efficiency peaking across a larger power backoff range and extend the saturated output power. The Hi-Z logic is designed so that disconnected capacitors do not remain floating. This is essential for ensuring correct capacitance ratios and impedance matching, and preventing distortion and reliability concerns due to voltage stresses and kickback effects. This concept was implemented in a voltage-mode Doherty SCPA prototype fabricated in 65 nm CMOS. The chip delivers 32% peak system efficiency (SE) at 25 dBm output power around 2.5 GHz and a 3 dB operational bandwidth of 1.7−2.8 GHz. Compared to a Class-B PA, SE improves by $1.3times $ and $1.83times $ at 3 dB and 7 dB backoff, respectively. It also achieves an error vector magnitude (EVM) of −37 dB at 14 dBm average output power for a 20 MHz OFDM Wi-Fi signal using piecewise digital predistortion.
{"title":"A Voltage-Mode I/Q Switched-Capacitor Doherty Power Amplifier With Dynamic Core Scaling for Enhanced Backoff Efficiency","authors":"Nimrod Ginzberg;Emanuel Cohen","doi":"10.1109/TCSII.2025.3607681","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3607681","url":null,"abstract":"This work presents a new backoff efficiency enhancement technique for switched-capacitor power amplifiers (SCPA) that employs dynamic core size resizing enabled by a high-impedance (Hi-Z) control state. The SCPA unit cells’ size is the dynamically adjusted according to the instantaneous output power, which broadens the backoff efficiency peaking across a larger power backoff range and extend the saturated output power. The Hi-Z logic is designed so that disconnected capacitors do not remain floating. This is essential for ensuring correct capacitance ratios and impedance matching, and preventing distortion and reliability concerns due to voltage stresses and kickback effects. This concept was implemented in a voltage-mode Doherty SCPA prototype fabricated in 65 nm CMOS. The chip delivers 32% peak system efficiency (SE) at 25 dBm output power around 2.5 GHz and a 3 dB operational bandwidth of 1.7−2.8 GHz. Compared to a Class-B PA, SE improves by <inline-formula> <tex-math>$1.3times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.83times $ </tex-math></inline-formula> at 3 dB and 7 dB backoff, respectively. It also achieves an error vector magnitude (EVM) of −37 dB at 14 dBm average output power for a 20 MHz OFDM Wi-Fi signal using piecewise digital predistortion.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1720-1724"},"PeriodicalIF":4.9,"publicationDate":"2025-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-08DOI: 10.1109/TCSII.2025.3606898
Yong Wu;Ziyang Luo;Bin Yang;Zhaotian Yan;Yang Chen;Ruikun Mai
For an inductive power transfer (IPT) system, stable power transfer is one of the most crucial abilities, but coupling variations can dramatically affect the system’s output. This brief proposes a reconfigurable detuned S-LCC compensated IPT system with two discrete frequencies to mitigate power fluctuations due to coupling variations. The original detuned S-LCC topology can operate in one stable region. With the change of the primary capacitor and frequency, the equivalent ac load can be altered, which will create a new stable region. Therefore, the expected coupling range of the detuned S-LCC topology can be extended. First, a detuned S-LCC IPT system with two discrete frequencies is presented, followed by an analysis of the working modes. Then, a detailed parameter design process and switching control are introduced. Finally, a 140-W prototype was constructed to verify the validity of the proposed method. The experimental results demonstrate that the output power fluctuation of the proposed IPT system is less than 5% and the lowest efficiency can be improved from 91.5%% to 94%, with the coupling coefficient varying from 0.27 to 0.63. The proposed method does not need complicated control or dedicated coil design, and it can implement stable power transfer significantly.
{"title":"A Reconfigurable Detuned S-LCC Compensated IPT System With Two Discrete Frequencies for Stable Power Against Coupling Variations","authors":"Yong Wu;Ziyang Luo;Bin Yang;Zhaotian Yan;Yang Chen;Ruikun Mai","doi":"10.1109/TCSII.2025.3606898","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3606898","url":null,"abstract":"For an inductive power transfer (IPT) system, stable power transfer is one of the most crucial abilities, but coupling variations can dramatically affect the system’s output. This brief proposes a reconfigurable detuned S-LCC compensated IPT system with two discrete frequencies to mitigate power fluctuations due to coupling variations. The original detuned S-LCC topology can operate in one stable region. With the change of the primary capacitor and frequency, the equivalent ac load can be altered, which will create a new stable region. Therefore, the expected coupling range of the detuned S-LCC topology can be extended. First, a detuned S-LCC IPT system with two discrete frequencies is presented, followed by an analysis of the working modes. Then, a detailed parameter design process and switching control are introduced. Finally, a 140-W prototype was constructed to verify the validity of the proposed method. The experimental results demonstrate that the output power fluctuation of the proposed IPT system is less than 5% and the lowest efficiency can be improved from 91.5%% to 94%, with the coupling coefficient varying from 0.27 to 0.63. The proposed method does not need complicated control or dedicated coil design, and it can implement stable power transfer significantly.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1795-1799"},"PeriodicalIF":4.9,"publicationDate":"2025-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-02DOI: 10.1109/TCSII.2025.3605161
Swagat Bhattacharyya
Envelope detectors in automatic gain control systems must achieve both low tracking latency and low output ripple for feedback stability. Conventional non-sampled envelope detectors intrinsically trade off latency and ripple. Maxima-sampling envelope detectors (MSEDs), which demodulate by sampling signal peaks, circumvent this latency-ripple trade-off, enabling control loops that remain stable over several frequency decades. However, MSED nonlinearity causes an intricate, previously uncharacterized interplay between input spectral properties and performance. This work analytically derives and numerically verifies input-dependent performance bounds for MSEDs. By formulating practical “rules-of-thumb” for mixed-signal circuit designers, we pave the way for the broader adoption of MSEDs.
{"title":"Performance Bounds for a Maxima-Sampling Envelope Detector","authors":"Swagat Bhattacharyya","doi":"10.1109/TCSII.2025.3605161","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3605161","url":null,"abstract":"Envelope detectors in automatic gain control systems must achieve both low tracking latency and low output ripple for feedback stability. Conventional non-sampled envelope detectors intrinsically trade off latency and ripple. Maxima-sampling envelope detectors (MSEDs), which demodulate by sampling signal peaks, circumvent this latency-ripple trade-off, enabling control loops that remain stable over several frequency decades. However, MSED nonlinearity causes an intricate, previously uncharacterized interplay between input spectral properties and performance. This work analytically derives and numerically verifies input-dependent performance bounds for MSEDs. By formulating practical “rules-of-thumb” for mixed-signal circuit designers, we pave the way for the broader adoption of MSEDs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1473-1477"},"PeriodicalIF":4.9,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145134914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The timestep-based inference process of spiking neural networks (SNNs) presents two challenges for neuromorphic chip design: 1) additional storage overhead for membrane potentials, and 2) significant power consumption resulting from repeated access to computational data. To address this challenge, this work proposes a timestep-parallel 4D neuromorphic computing array of size $N_{T}times N_{Z}times N_{X}times N_{Y}$ , simultaneously enabling parallel computing in temporal and spatial dimensions. The $N_{T}$ dimension supports timestep-parallel computing, the $N_{Z}$ dimension supports neuron-parallel computing, and the $N_{X}$ and $N_{Y}$ dimensions are used for synapse-parallel computing. The architecture facilitates flexible data reuse across different dimensions (with weights reuse along different timesteps and spikes reuse along different neurons), significantly reducing storage access. Meanwhile, it treats the membrane potential as a short-term computational variable that can be stored in a small buffer, thereby eliminating large-scale membrane potential storage overhead and access. The reduction in data access and storage costs is beneficial for lowering system power consumption and enhancing synaptic energy efficiency. Ultimately, the architecture is evaluated using a 28 nm process library and demonstrates a high computing power density of 1160 GSOP/s/mm2 and a high synaptic energy efficiency of 0.36 pJ/SOP, surpassing related state-of-the-art works. This work significantly reduces the hardware cost of neuromorphic computing and is expected to enhance the competitiveness of neuromorphic hardware in contemporary artificial intelligence applications.
{"title":"Timestep-Parallel 4D Neuromorphic Computing Array Enabling High Computing Power Density and High Energy Efficiency","authors":"Pujun Zhou;Changhui Xiao;Liwei Meng;Qi Yu;Ning Ning;Yang Liu;Shaogang Hu;Guanchao Qiao","doi":"10.1109/TCSII.2025.3603624","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3603624","url":null,"abstract":"The timestep-based inference process of spiking neural networks (SNNs) presents two challenges for neuromorphic chip design: 1) additional storage overhead for membrane potentials, and 2) significant power consumption resulting from repeated access to computational data. To address this challenge, this work proposes a timestep-parallel 4D neuromorphic computing array of size <inline-formula> <tex-math>$N_{T}times N_{Z}times N_{X}times N_{Y}$ </tex-math></inline-formula>, simultaneously enabling parallel computing in temporal and spatial dimensions. The <inline-formula> <tex-math>$N_{T}$ </tex-math></inline-formula> dimension supports timestep-parallel computing, the <inline-formula> <tex-math>$N_{Z}$ </tex-math></inline-formula> dimension supports neuron-parallel computing, and the <inline-formula> <tex-math>$N_{X}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$N_{Y}$ </tex-math></inline-formula> dimensions are used for synapse-parallel computing. The architecture facilitates flexible data reuse across different dimensions (with weights reuse along different timesteps and spikes reuse along different neurons), significantly reducing storage access. Meanwhile, it treats the membrane potential as a short-term computational variable that can be stored in a small buffer, thereby eliminating large-scale membrane potential storage overhead and access. The reduction in data access and storage costs is beneficial for lowering system power consumption and enhancing synaptic energy efficiency. Ultimately, the architecture is evaluated using a 28 nm process library and demonstrates a high computing power density of 1160 GSOP/s/mm2 and a high synaptic energy efficiency of 0.36 pJ/SOP, surpassing related state-of-the-art works. This work significantly reduces the hardware cost of neuromorphic computing and is expected to enhance the competitiveness of neuromorphic hardware in contemporary artificial intelligence applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1448-1452"},"PeriodicalIF":4.9,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-28DOI: 10.1109/TCSII.2025.3600132
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3600132","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3600132","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11143809","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-28DOI: 10.1109/TCSII.2025.3600134
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3600134","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3600134","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11143808","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micro-Electro-Mechanical Systems (MEMS) loudspeakers represent a promising solution to meet the growing demand for compact, portable consumer audio devices with integrated sound reproduction capabilities. In this context, the availability of accurate and computationally efficient Lumped-Element Models (LEMs) can greatly accelerate MEMS loudspeaker design and support the development of digital signal processing techniques aimed at enhancing audio performance. In this work, we propose a framework based on Automatic Differentiation (AD) to optimize the parameters of differentiable LEMs in a fully data-driven manner using standard gradient-based optimization methods. Specifically, we focus on tuning the parameters of an ad hoc linear equivalent circuit model for a commercially available MEMS loudspeaker intended for free-field applications.
{"title":"Gradient-Based Optimization of MEMS Loudspeaker Equivalent Circuit Models via Automatic Differentiation","authors":"Oliviero Massi;Alessandro Ilic Mezza;Riccardo Giampiccolo;Lelio Casale;Alberto Bernardini","doi":"10.1109/TCSII.2025.3603686","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3603686","url":null,"abstract":"Micro-Electro-Mechanical Systems (MEMS) loudspeakers represent a promising solution to meet the growing demand for compact, portable consumer audio devices with integrated sound reproduction capabilities. In this context, the availability of accurate and computationally efficient Lumped-Element Models (LEMs) can greatly accelerate MEMS loudspeaker design and support the development of digital signal processing techniques aimed at enhancing audio performance. In this work, we propose a framework based on Automatic Differentiation (AD) to optimize the parameters of differentiable LEMs in a fully data-driven manner using standard gradient-based optimization methods. Specifically, we focus on tuning the parameters of an ad hoc linear equivalent circuit model for a commercially available MEMS loudspeaker intended for free-field applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1468-1472"},"PeriodicalIF":4.9,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145134915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-27DOI: 10.1109/TCSII.2025.3603414
Wenrong Li;Haitao Li;Lingling Wu
The law of conservation is crucial to guarantee the robustness of gene expression and signal transduction processes in biological systems. This brief analyzes the feedback total-activity conservation of Boolean control networks (BCNs) based on the semi-tensor product of matrices. First, by constructing the conservative characteristic matrix, a matrix-based criterion is presented to verify the total-activity conservation of BCNs. Secondly, by establishing the control index set, all possible state feedback controllers are designed to achieve the total-activity conservation for BCNs. Finally, an example of lac operon in the Escherichia coli is given to illustrate the proposed results.
{"title":"Feedback Total-Activity Conservation of Boolean Control Networks","authors":"Wenrong Li;Haitao Li;Lingling Wu","doi":"10.1109/TCSII.2025.3603414","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3603414","url":null,"abstract":"The law of conservation is crucial to guarantee the robustness of gene expression and signal transduction processes in biological systems. This brief analyzes the feedback total-activity conservation of Boolean control networks (BCNs) based on the semi-tensor product of matrices. First, by constructing the conservative characteristic matrix, a matrix-based criterion is presented to verify the total-activity conservation of BCNs. Secondly, by establishing the control index set, all possible state feedback controllers are designed to achieve the total-activity conservation for BCNs. Finally, an example of lac operon in the Escherichia coli is given to illustrate the proposed results.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1428-1432"},"PeriodicalIF":4.9,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TCSII.2025.3603015
Cheng Zhao;Li Lun;Zhenhui Dai;Tingting Zhong;Yi Zhong;Yingying Cui;Xiaoxin Cui
The fusion of convolutional neural network (CNN) and spiking neural network (SNN) harnesses their complementary strengths in edge video tasks. However, ongoing challenges remain in the low compatibility between two neural networks and the shortage of storage resources. In this brief, we propose a reconfigurable digital compute-in-memory (RDCIM) architecture featuring 2:4 structured weight pruning, tailored for the efficient fusion of CNN and SNN. Specifically, differential frame convolution (DFC) is adopted in place of conventional convolution. Therefore, the RDCIM fusion accelerator can operate in either DFC mode or SNN mode based on the sparsity of activations. First of all, fine-grained 2:4 structured sparsity enables compressed weight storage, thereby doubling the throughput. Secondly, a novel bitwise in-memory Booth multiplier is implemented to support both 4-bit and 8-bit activations, offering flexible computation. Thirdly, the high sparsity inherent in both differential frames and input spikes allows for the concurrent support of three sparse optimization strategies: coarse-grained zero skipping, medium-grained bank gating, and fine-grained precharge gating. Implemented by TSMC 28nm technology, our proposed architecture achieves the peak energy efficiency of 42.02 TOPS/W for DFC and 0.02 pJ/SOP for SNN.
{"title":"A Reconfigurable Digital Compute-in-Memory Architecture With 2:4 Compressed Weight Storage for Highly Sparse Fusion Neural Network","authors":"Cheng Zhao;Li Lun;Zhenhui Dai;Tingting Zhong;Yi Zhong;Yingying Cui;Xiaoxin Cui","doi":"10.1109/TCSII.2025.3603015","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3603015","url":null,"abstract":"The fusion of convolutional neural network (CNN) and spiking neural network (SNN) harnesses their complementary strengths in edge video tasks. However, ongoing challenges remain in the low compatibility between two neural networks and the shortage of storage resources. In this brief, we propose a reconfigurable digital compute-in-memory (RDCIM) architecture featuring 2:4 structured weight pruning, tailored for the efficient fusion of CNN and SNN. Specifically, differential frame convolution (DFC) is adopted in place of conventional convolution. Therefore, the RDCIM fusion accelerator can operate in either DFC mode or SNN mode based on the sparsity of activations. First of all, fine-grained 2:4 structured sparsity enables compressed weight storage, thereby doubling the throughput. Secondly, a novel bitwise in-memory Booth multiplier is implemented to support both 4-bit and 8-bit activations, offering flexible computation. Thirdly, the high sparsity inherent in both differential frames and input spikes allows for the concurrent support of three sparse optimization strategies: coarse-grained zero skipping, medium-grained bank gating, and fine-grained precharge gating. Implemented by TSMC 28nm technology, our proposed architecture achieves the peak energy efficiency of 42.02 TOPS/W for DFC and 0.02 pJ/SOP for SNN.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1750-1754"},"PeriodicalIF":4.9,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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