The conventional models employ fundamental harmonic approximation for charge-controlled LLC resonant converter. However, when the switching frequency deviates from the resonant frequency, significant distortion occurs in the state variables, leading to degraded accuracy in the models. To address this issue, this brief proposes a novel small-signal modeling approach based on time-domain analysis. The proposed method first derives the simplified time-domain operating constraints for the converter. The simplified constraints relieve the computation burden and reduce the number of intermediate variables, making it more suitable for small-signal modeling. Next, the relationships between small-signal variables are derived from these constraints. Finally, a complete mathematical model of the charge-controlled LLC resonant converter is constructed. Experimental validation is performed on a 200V/1kW LLC resonant converter prototype. Both simulation and experimental results confirm the superior accuracy of the proposed model.
{"title":"Enhanced Small-Signal Model for Charge-Controlled LLC Resonant Converters Using Time-Domain Analysis","authors":"Wenzhe Chen;Kangli Liu;Hongqi Ding;Yichao Sun;Cheng Jin;Pengyu Wang;Jianfeng Zhao","doi":"10.1109/TCSII.2025.3596316","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3596316","url":null,"abstract":"The conventional models employ fundamental harmonic approximation for charge-controlled LLC resonant converter. However, when the switching frequency deviates from the resonant frequency, significant distortion occurs in the state variables, leading to degraded accuracy in the models. To address this issue, this brief proposes a novel small-signal modeling approach based on time-domain analysis. The proposed method first derives the simplified time-domain operating constraints for the converter. The simplified constraints relieve the computation burden and reduce the number of intermediate variables, making it more suitable for small-signal modeling. Next, the relationships between small-signal variables are derived from these constraints. Finally, a complete mathematical model of the charge-controlled LLC resonant converter is constructed. Experimental validation is performed on a 200V/1kW LLC resonant converter prototype. Both simulation and experimental results confirm the superior accuracy of the proposed model.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1453-1457"},"PeriodicalIF":4.9,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-05DOI: 10.1109/TCSII.2025.3595599
Joonseok Park;Jaeyong Lee;Changkun Park
In this brief, we design a CMOS-based dual-core voltage-controlled oscillator (VCO) to extend the frequency tuning range. To mitigate the increase in integrated circuit area caused by the LC tanks required for dual-core operation, a dual-primary transformer structure is proposed. The proposed transformer consists of two primary windings and one secondary winding. The primary winding corresponding to the core supporting lower frequencies is designed with two turns to secure sufficient inductance. Thanks to the proposed dual-primary transformer, a compact size is achieved despite the dual-core VCO configuration. To validate the effectiveness of the proposed structure, the VCO is fabricated using a 65-nm RFCMOS process. The fabricated VCO core, including the output buffer, occupies an area of $0.39times 0.11$ mm2. The measured frequency tuning range spans from 17.8 GHz to 26.9 GHz, with phase noise at 1-MHz offset and output power measured to be lower than −89.6 dBc/Hz and higher than −15.3 dBm, respectively.
{"title":"Design of Compact Size CMOS VCO Using Dual-Primary Transformer With Dual-Core for Wide Tuning-Range","authors":"Joonseok Park;Jaeyong Lee;Changkun Park","doi":"10.1109/TCSII.2025.3595599","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3595599","url":null,"abstract":"In this brief, we design a CMOS-based dual-core voltage-controlled oscillator (VCO) to extend the frequency tuning range. To mitigate the increase in integrated circuit area caused by the LC tanks required for dual-core operation, a dual-primary transformer structure is proposed. The proposed transformer consists of two primary windings and one secondary winding. The primary winding corresponding to the core supporting lower frequencies is designed with two turns to secure sufficient inductance. Thanks to the proposed dual-primary transformer, a compact size is achieved despite the dual-core VCO configuration. To validate the effectiveness of the proposed structure, the VCO is fabricated using a 65-nm RFCMOS process. The fabricated VCO core, including the output buffer, occupies an area of <inline-formula> <tex-math>$0.39times 0.11$ </tex-math></inline-formula> mm2. The measured frequency tuning range spans from 17.8 GHz to 26.9 GHz, with phase noise at 1-MHz offset and output power measured to be lower than −89.6 dBc/Hz and higher than −15.3 dBm, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1213-1217"},"PeriodicalIF":4.9,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this brief, an innovative adaptive event-triggered control approach is devised to solve the optimal control problems of power buffer systems in DC microgrids. The optimal control problem of power buffers is addressed via a decentralized framework to ensure mutual interconnection among subsystems. Additionally, the adaptive dynamic programming (ADP) method is integrated with an event-triggered mechanism to derive an approximate optimal control strategy, which can effectively reduce the communication overhead between different subsystems. Moreover, the stability of the interconnected system is proved and the Zeno behavior is rigorously excluded through theoretical analysis. The effectiveness of the proposed method is validated through a DC microgrid case study.
{"title":"Optimal Control of Active Load Interconnected System in DC Microgrid via an Adaptive Decentralized Event-Triggered Mechanism","authors":"Dongyuan Zhang;Hanguang Su;Huaguang Zhang;Jiayue Sun;Zemeng Mi;Yi Zong","doi":"10.1109/TCSII.2025.3595844","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3595844","url":null,"abstract":"In this brief, an innovative adaptive event-triggered control approach is devised to solve the optimal control problems of power buffer systems in DC microgrids. The optimal control problem of power buffers is addressed via a decentralized framework to ensure mutual interconnection among subsystems. Additionally, the adaptive dynamic programming (ADP) method is integrated with an event-triggered mechanism to derive an approximate optimal control strategy, which can effectively reduce the communication overhead between different subsystems. Moreover, the stability of the interconnected system is proved and the Zeno behavior is rigorously excluded through theoretical analysis. The effectiveness of the proposed method is validated through a DC microgrid case study.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1393-1397"},"PeriodicalIF":4.9,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/TCSII.2025.3594876
Ziliang Zhou;Min Tan
This brief presents a high-voltage charge pump with pseudo-continuous regulation using dynamic clock voltage scaling. We propose a small-signal model of the charge pump to facilitate co-simulation of the linear amplifier and the capacitive switching converter, and it shows good agreement with the time-domain ac simulation results. A novel lead compensation is proposed in the amplifier using current-mirror Miller compensation, which ensures loop stability without a large load capacitor at the charge pump’s output. The proposed regulated charge pump has been implemented in a 65-nm CMOS process, and the chip area is $280~{mu }$ m ${times } 300~{mu }$ m. Operating at a 2.5-V supply, it maintains < 21 mV ripple voltage at 9.6 V output for different load currents and pumping frequencies. The undershoot for the load transient current of 0 to $50~{mu }$ A with a 160-ns edge time is 58 mV with around $0.8~{mu }$ s recovery time.
{"title":"A High-Voltage Charge Pump With Pseudo-Continuous Output Regulation Using Dynamic Clock Voltage Scaling","authors":"Ziliang Zhou;Min Tan","doi":"10.1109/TCSII.2025.3594876","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594876","url":null,"abstract":"This brief presents a high-voltage charge pump with pseudo-continuous regulation using dynamic clock voltage scaling. We propose a small-signal model of the charge pump to facilitate co-simulation of the linear amplifier and the capacitive switching converter, and it shows good agreement with the time-domain ac simulation results. A novel lead compensation is proposed in the amplifier using current-mirror Miller compensation, which ensures loop stability without a large load capacitor at the charge pump’s output. The proposed regulated charge pump has been implemented in a 65-nm CMOS process, and the chip area is <inline-formula> <tex-math>$280~{mu }$ </tex-math></inline-formula>m <inline-formula> <tex-math>${times } 300~{mu }$ </tex-math></inline-formula>m. Operating at a 2.5-V supply, it maintains < 21 mV ripple voltage at 9.6 V output for different load currents and pumping frequencies. The undershoot for the load transient current of 0 to <inline-formula> <tex-math>$50~{mu }$ </tex-math></inline-formula>A with a 160-ns edge time is 58 mV with around <inline-formula> <tex-math>$0.8~{mu }$ </tex-math></inline-formula>s recovery time.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1323-1327"},"PeriodicalIF":4.9,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-31DOI: 10.1109/TCSII.2025.3594405
Ning Wang;Mengkai Cui;Muhammad Marwan;Yan Yang;Han Bao;Herbert Ho-Ching Iu;Quan Xu
This brief presents a simple one-step parallel fractal algorithm for automatic design of multi-fold hyperchaotic system from scroll/wing-type seed system. It is shown that the desired number of folds can be generated via a simple parametric control. Two representative application cases of four-dimensional and six-dimensional multi-fold no-equilibrium hyperchaotic systems are presented. For a double-wing seed attractor, the method will generate $2^{m}$ wings under each pair of m-fold transformation. In contrast with existing designs, the proposed algorithm is automatic and has wide applicability in generating various numbers of folds in multiple directions. Simulation studies and hardware implementations are conducted to verify the feasibility of the proposed algorithm.
{"title":"Automatic Design of Multi-Fold Hyperchaotic System Using Parallel Fractal Algorithm","authors":"Ning Wang;Mengkai Cui;Muhammad Marwan;Yan Yang;Han Bao;Herbert Ho-Ching Iu;Quan Xu","doi":"10.1109/TCSII.2025.3594405","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594405","url":null,"abstract":"This brief presents a simple one-step parallel fractal algorithm for automatic design of multi-fold hyperchaotic system from scroll/wing-type seed system. It is shown that the desired number of folds can be generated via a simple parametric control. Two representative application cases of four-dimensional and six-dimensional multi-fold no-equilibrium hyperchaotic systems are presented. For a double-wing seed attractor, the method will generate <inline-formula> <tex-math>$2^{m}$ </tex-math></inline-formula> wings under each pair of m-fold transformation. In contrast with existing designs, the proposed algorithm is automatic and has wide applicability in generating various numbers of folds in multiple directions. Simulation studies and hardware implementations are conducted to verify the feasibility of the proposed algorithm.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1313-1317"},"PeriodicalIF":4.9,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-31DOI: 10.1109/TCSII.2025.3589810
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3589810","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3589810","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106323","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents an NRZ/PAM4 rapid-on/off baud-rate clock and data recovery (CDR) for mobile interfaces, featuring power-efficient bandwidth scaling. To minimize power overhead due to large turn-on time, a pulse-based rapid clock recovery method is proposed. This method estimates and immediately compensates for initial phase error based on a pre-trained look-up table, significantly reducing the CDR’s turn-on time. In addition, a background PAM4 eye-climbing algorithm (ECA) addresses the sub-optimal lock point issue of conventional baud-rate phase detectors by adjusting the lock point to maximize the vertical eye margin (VEM). The prototype receiver fabricated in a 28 nm CMOS supports data rates from 2.5 to 48Gb/s, accommodating both legacy and next-generation mobile interfaces. It achieves an energy efficiency of 1.43 pJ/b at 48 Gb/s while demonstrating a fast turn-on time of 16.6 ns, enabling superior energy efficiency across various effective data rates. Moreover, the PAM4 ECA increases VEM of the PAM4 middle eye by 18 mV, ensuring error-free operation.
{"title":"A 2.5-48 Gb/s 16.6 ns Turn-On Time NRZ/PAM4 Pulse-Based Rapid-On/Off Baud-Rate CDR for Mobile Interfaces","authors":"Jihee Kim;Yunhee Lee;Hyun-Seok Choi;Yoona Lee;Sanghee Lee;Woo-Seok Choi","doi":"10.1109/TCSII.2025.3594475","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594475","url":null,"abstract":"This brief presents an NRZ/PAM4 rapid-on/off baud-rate clock and data recovery (CDR) for mobile interfaces, featuring power-efficient bandwidth scaling. To minimize power overhead due to large turn-on time, a pulse-based rapid clock recovery method is proposed. This method estimates and immediately compensates for initial phase error based on a pre-trained look-up table, significantly reducing the CDR’s turn-on time. In addition, a background PAM4 eye-climbing algorithm (ECA) addresses the sub-optimal lock point issue of conventional baud-rate phase detectors by adjusting the lock point to maximize the vertical eye margin (VEM). The prototype receiver fabricated in a 28 nm CMOS supports data rates from 2.5 to 48Gb/s, accommodating both legacy and next-generation mobile interfaces. It achieves an energy efficiency of 1.43 pJ/b at 48 Gb/s while demonstrating a fast turn-on time of 16.6 ns, enabling superior energy efficiency across various effective data rates. Moreover, the PAM4 ECA increases VEM of the PAM4 middle eye by 18 mV, ensuring error-free operation.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1193-1197"},"PeriodicalIF":4.9,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-30DOI: 10.1109/TCSII.2025.3594199
Kyoungseok Song;Donggun Lee;Geunhaeng Lee;Yonghui Li;Tae Wook Kim
This brief presents an impulse radio-ultrawideband (IR-UWB) transmitter (Tx) that achieves high energy efficiency and data rate through a power-gating (PG) technique and hybrid modulation scheme. PG minimizes static power consumption by activating the digitally controlled oscillator (DCO) only during transmission. A hybrid modulation scheme combines frequency- shift keying (FSK) with digitalized multi pulse position modulation (D-MPPM) and pulse width modulation (PWM) to increase modulation order. Implemented in 6.5-8.5 GHz, the proposed PG-DCO Tx achieves a data rate of 2.54 Gbps with an energy efficiency of 1.22 pJ/bit, approaching the 1 pJ/bit energy-efficiency barrier for UWB transmitters.
{"title":"A 2.54 Gbps, 1.22 pJ/Bit, IR-UWB Transmitter With a Power-Gating Technique","authors":"Kyoungseok Song;Donggun Lee;Geunhaeng Lee;Yonghui Li;Tae Wook Kim","doi":"10.1109/TCSII.2025.3594199","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594199","url":null,"abstract":"This brief presents an impulse radio-ultrawideband (IR-UWB) transmitter (Tx) that achieves high energy efficiency and data rate through a power-gating (PG) technique and hybrid modulation scheme. PG minimizes static power consumption by activating the digitally controlled oscillator (DCO) only during transmission. A hybrid modulation scheme combines frequency- shift keying (FSK) with digitalized multi pulse position modulation (D-MPPM) and pulse width modulation (PWM) to increase modulation order. Implemented in 6.5-8.5 GHz, the proposed PG-DCO Tx achieves a data rate of 2.54 Gbps with an energy efficiency of 1.22 pJ/bit, approaching the 1 pJ/bit energy-efficiency barrier for UWB transmitters.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1208-1212"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-30DOI: 10.1109/TCSII.2025.3594027
Zonglin Ye;Hongyang Zhang;Yuxuan Sun;Xinlin Geng;Qian Xie;Shiheng Yang;Zheng Wang
A calibration-free fractional-N synthesizer is presented with octave tuning capability and low fractional spurs, which is fabricated using a 65-nm bulk CMOS process. The synthesizer is based on the harmonic-mixing (HM) architecture, featuring a unity gain for the quantization error transfer to achieve low fractional spur without any calibration. To support octave-tuning, a ring-oscilator(RO)-based first stage is utilized to save area with negligible jitter deterioration. Moreover, a variable sub-sampling ratio technique is employed to relax the tuning range requirement for the RO. The measurements demonstrate an octave-tuning synthesizer with −80.7 dBc fractional spur, 71.7% tuning range and −254.6 dB FoMT.
{"title":"A 6.8-14.4GHz Calibration-Free Fractional-N RO-Based Harmonic-Mixing Frequency Synthesizer Achieving −80.7dBc Fractional Spur","authors":"Zonglin Ye;Hongyang Zhang;Yuxuan Sun;Xinlin Geng;Qian Xie;Shiheng Yang;Zheng Wang","doi":"10.1109/TCSII.2025.3594027","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594027","url":null,"abstract":"A calibration-free fractional-N synthesizer is presented with octave tuning capability and low fractional spurs, which is fabricated using a 65-nm bulk CMOS process. The synthesizer is based on the harmonic-mixing (HM) architecture, featuring a unity gain for the quantization error transfer to achieve low fractional spur without any calibration. To support octave-tuning, a ring-oscilator(RO)-based first stage is utilized to save area with negligible jitter deterioration. Moreover, a variable sub-sampling ratio technique is employed to relax the tuning range requirement for the RO. The measurements demonstrate an octave-tuning synthesizer with −80.7 dBc fractional spur, 71.7% tuning range and −254.6 dB FoMT.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1183-1187"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-30DOI: 10.1109/TCSII.2025.3593898
Young-Ju Oh;Chan-Ho Lee;Jeong-Hun Kim;Hyeonho Park;Dowon Jeong;Sung-Wan Hong
This brief proposes a pseudo two-stage two-phase (P2S-2P) buck converter that enhances power efficiency by reducing current in the high-voltage (HV) domain, which has large parasitic components. In contrast, the low-voltage (LV) domain, which has small parasitic components, supplies the majority of the output current (IO) through two inductors that automatically balance their currents. The proposed converter achieves a peak efficiency of 91.7% at an input voltage (VIN) of 48V, an output voltage (VO) of 1V, and the IO of 1.5A. The chip was fabricated using a 180-nm BCD process.
{"title":"A 91.7% Peak-Efficiency 48V-to-1V Pseudo Two-Stage Two-Phase Hybrid Buck Converter","authors":"Young-Ju Oh;Chan-Ho Lee;Jeong-Hun Kim;Hyeonho Park;Dowon Jeong;Sung-Wan Hong","doi":"10.1109/TCSII.2025.3593898","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593898","url":null,"abstract":"This brief proposes a pseudo two-stage two-phase (P2S-2P) buck converter that enhances power efficiency by reducing current in the high-voltage (HV) domain, which has large parasitic components. In contrast, the low-voltage (LV) domain, which has small parasitic components, supplies the majority of the output current (IO) through two inductors that automatically balance their currents. The proposed converter achieves a peak efficiency of 91.7% at an input voltage (VIN) of 48V, an output voltage (VO) of 1V, and the IO of 1.5A. The chip was fabricated using a 180-nm BCD process.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1318-1322"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：