In this brief, we propose a high-precision built-in phase noise measurement (PNM) circuit based on a $Delta Sigma $ time-to-digital converter (TDC) and a pseudo-delay-locked loop (DLL). The designed $Delta Sigma $ TDC uses a hybrid continuous-time (CT) discrete-time (DT) loop filter. The first integrator consists of a phase frequency detector (PFD), a charge pump (CP), and an operational transconductance amplifier (OTA)-based integrator operating as a CT filter. The OTA-based integrator ensures a constant output current, improving linearity. Other loop filters employ a switched capacitor integrator as a DT filter. The proposed architecture processes time-domain signals and has the advantage of containing both CT and DT loop filters. This architecture is less sensitive to coefficient variations compared to CT $Delta Sigma $ . Pseudo-DLL provides a precise reference delay. The proposed PNM circuit is fabricated in the 28 nm CMOS process, occupies an area of 0.113 mm2, and consumes 11.61 mW with a 1 V power supply while running at a clock rate of 250 MHz. The rms jitter from 100 kHz to 2 MHz measured by an external instrument and PNM are 1.77 and 1.8137 ps, respectively, while the corresponding error is less than 3%. The proposed PNM circuit can achieve approximately 2 ps from 100 kHz to 4 MHz at the optimum noise transfer function (NTF) zero location.
{"title":"High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications","authors":"Jihun Choi;Sangwook Na;Hojin Kim;Hyungdong Roh;Youngjae Cho;Michael Choi;Min-Seong Choo;Jeongjin Roh","doi":"10.1109/TCSII.2024.3435434","DOIUrl":"10.1109/TCSII.2024.3435434","url":null,"abstract":"In this brief, we propose a high-precision built-in phase noise measurement (PNM) circuit based on a \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 time-to-digital converter (TDC) and a pseudo-delay-locked loop (DLL). The designed \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 TDC uses a hybrid continuous-time (CT) discrete-time (DT) loop filter. The first integrator consists of a phase frequency detector (PFD), a charge pump (CP), and an operational transconductance amplifier (OTA)-based integrator operating as a CT filter. The OTA-based integrator ensures a constant output current, improving linearity. Other loop filters employ a switched capacitor integrator as a DT filter. The proposed architecture processes time-domain signals and has the advantage of containing both CT and DT loop filters. This architecture is less sensitive to coefficient variations compared to CT \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000. Pseudo-DLL provides a precise reference delay. The proposed PNM circuit is fabricated in the 28 nm CMOS process, occupies an area of 0.113 mm2, and consumes 11.61 mW with a 1 V power supply while running at a clock rate of 250 MHz. The rms jitter from 100 kHz to 2 MHz measured by an external instrument and PNM are 1.77 and 1.8137 ps, respectively, while the corresponding error is less than 3%. The proposed PNM circuit can achieve approximately 2 ps from 100 kHz to 4 MHz at the optimum noise transfer function (NTF) zero location.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4613-4617"},"PeriodicalIF":4.0,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141866001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this brief, a novel continuous-mode asymmetrical Doherty power amplifier (CM-ADPA) is proposed. It is illustrated that by applying complex impedance at the power combining node, the continuous-mode impedance condition can be obtained for the main amplifier at both saturation and output power back-off (OBO) to obtain broadband high-efficiency performance. To further expand the bandwidth, an LC-ladder-based lumped Wilkinson divider and impedance inverter are employed for wideband power division and phase alignment between sub-amplifiers, respectively. To validate the proposed topology, a CM-ADPA monolithic microwave integrated circuit (MMIC) is implemented with a highly compact die size of $2.2times 1$ .8 mm2. The fabricated MMIC obtains a 4.4-5.6 GHz bandwidth. Within the operating band, the DPA exhibits a saturation output power of 40.7-41.0 dBm, a saturated drain efficiency (DE) of 53.7%-59.4%, and a DE of 34.0%-43.8% at 8-dB OBO. Under a 100-MHz orthogonal frequency division multiplexing (OFDM) signal, the CM-ADPA also demonstrates good linearity and efficiency.
{"title":"Design of a Fully Integrated Wideband Continuous-Mode Asymmetrical Doherty Power Amplifier in GaN-on-SiC HEMT Technology","authors":"Jingyuan Zhang;Renlong Han;Falin Liu;Xu Yan;Yongxin Guo","doi":"10.1109/TCSII.2024.3434572","DOIUrl":"10.1109/TCSII.2024.3434572","url":null,"abstract":"In this brief, a novel continuous-mode asymmetrical Doherty power amplifier (CM-ADPA) is proposed. It is illustrated that by applying complex impedance at the power combining node, the continuous-mode impedance condition can be obtained for the main amplifier at both saturation and output power back-off (OBO) to obtain broadband high-efficiency performance. To further expand the bandwidth, an LC-ladder-based lumped Wilkinson divider and impedance inverter are employed for wideband power division and phase alignment between sub-amplifiers, respectively. To validate the proposed topology, a CM-ADPA monolithic microwave integrated circuit (MMIC) is implemented with a highly compact die size of \u0000<inline-formula> <tex-math>$2.2times 1$ </tex-math></inline-formula>\u0000.8 mm2. The fabricated MMIC obtains a 4.4-5.6 GHz bandwidth. Within the operating band, the DPA exhibits a saturation output power of 40.7-41.0 dBm, a saturated drain efficiency (DE) of 53.7%-59.4%, and a DE of 34.0%-43.8% at 8-dB OBO. Under a 100-MHz orthogonal frequency division multiplexing (OFDM) signal, the CM-ADPA also demonstrates good linearity and efficiency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4879-4883"},"PeriodicalIF":4.0,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141866111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-29DOI: 10.1109/TCSII.2024.3435475
Qiang Jia;Peipei Zhou;Xiaowen Bi;Shuiming Cai
This brief proposes a novel event-based pinning strategy for reaching synchronization of a typical class of delayed memristive neural network (MNN) under a master-slave framework. By initially injecting the pinning signal into the neuron with maximal synchrony error, the control is then switched between the neurons according to certain well-designed triggering condition. By incorporating the Lyapunov function method with some Halanay-type inequality, it is proved that such a design suffices to synchronize two MNNs with an exponential rate. It is worth to mention that the restriction of diffusive coupling for conventional pinning control schemes is unnecessary herein, and the gain used here keeps fixed which can thus avoid certain drawback of existing pinning strategies for synchronizing MNNs. A numerical example is finally given to demonstrate the feasibility and performance of the proposed design.
{"title":"Event-Based Pinning Strategy for Synchronizing Memristive Neural Networks With Delays","authors":"Qiang Jia;Peipei Zhou;Xiaowen Bi;Shuiming Cai","doi":"10.1109/TCSII.2024.3435475","DOIUrl":"10.1109/TCSII.2024.3435475","url":null,"abstract":"This brief proposes a novel event-based pinning strategy for reaching synchronization of a typical class of delayed memristive neural network (MNN) under a master-slave framework. By initially injecting the pinning signal into the neuron with maximal synchrony error, the control is then switched between the neurons according to certain well-designed triggering condition. By incorporating the Lyapunov function method with some Halanay-type inequality, it is proved that such a design suffices to synchronize two MNNs with an exponential rate. It is worth to mention that the restriction of diffusive coupling for conventional pinning control schemes is unnecessary herein, and the gain used here keeps fixed which can thus avoid certain drawback of existing pinning strategies for synchronizing MNNs. A numerical example is finally given to demonstrate the feasibility and performance of the proposed design.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5019-5023"},"PeriodicalIF":4.0,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141865960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-25DOI: 10.1109/TCSII.2024.3433477
Andrea Bevilacqua;Andrea Mazzanti
This brief rigorously investigates circuit techniques that aim at increasing the common-mode rejection ratio (CMRR) in a transformer-based doubly-tuned balun network. The presented analytical results are able to predict and quantify the CMRR for various circuit solutions employed in the literature. Moreover, they are able to predict the conditions under which such solutions are not effective. Simulations performed on use cases of practical interest validate the developed theory.
{"title":"Analysis of CMRR in Doubly-Tuned Transformer Baluns","authors":"Andrea Bevilacqua;Andrea Mazzanti","doi":"10.1109/TCSII.2024.3433477","DOIUrl":"10.1109/TCSII.2024.3433477","url":null,"abstract":"This brief rigorously investigates circuit techniques that aim at increasing the common-mode rejection ratio (CMRR) in a transformer-based doubly-tuned balun network. The presented analytical results are able to predict and quantify the CMRR for various circuit solutions employed in the literature. Moreover, they are able to predict the conditions under which such solutions are not effective. Simulations performed on use cases of practical interest validate the developed theory.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4874-4878"},"PeriodicalIF":4.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a NOR-structured physically unclonable function (PUF) tailored for low-cost Internet of Things (IoT) applications. The proposed NOR-structured PUF utilizes a single minimum-sized differential NMOS pair, capitalizing on threshold-voltage mismatch as the entropy source. Fabricated in 65nm CMOS, the basic PUF cell is a $58F^{2}$ differential NMOS pair, demonstrating a raw bit error rate (BER) of 0.31%. To further enhance the stability and achieve an ultra-low BER, we introduce an area-efficient redundancy strategy. By incorporating 4x redundancy cells ( $266F^{2}$ in total), the prototype chip achieves an ultra-low BER (zero error in 20M bits), over a wide temperature range (−20 to 125°C) and supply voltage variations (0.8 to 1.2V). The core energy consumption is only 63fJ/bit, offering a low-cost and highly stable solution for IoT applications.
{"title":"A 266F2 Ultra Stable Differential NOR-Structured Physically Unclonable Function With < 6×10-9 Bit Error Rate Through Efficient Redundancy Strategy","authors":"Haoyi Zhang;Jiahao Song;Haoyang Luo;Xiyuan Tang;Yuan Wang;Runsheng Wang;Ru Huang","doi":"10.1109/TCSII.2024.3433543","DOIUrl":"10.1109/TCSII.2024.3433543","url":null,"abstract":"This brief presents a NOR-structured physically unclonable function (PUF) tailored for low-cost Internet of Things (IoT) applications. The proposed NOR-structured PUF utilizes a single minimum-sized differential NMOS pair, capitalizing on threshold-voltage mismatch as the entropy source. Fabricated in 65nm CMOS, the basic PUF cell is a \u0000<inline-formula> <tex-math>$58F^{2}$ </tex-math></inline-formula>\u0000 differential NMOS pair, demonstrating a raw bit error rate (BER) of 0.31%. To further enhance the stability and achieve an ultra-low BER, we introduce an area-efficient redundancy strategy. By incorporating 4x redundancy cells (\u0000<inline-formula> <tex-math>$266F^{2}$ </tex-math></inline-formula>\u0000 in total), the prototype chip achieves an ultra-low BER (zero error in 20M bits), over a wide temperature range (−20 to 125°C) and supply voltage variations (0.8 to 1.2V). The core energy consumption is only 63fJ/bit, offering a low-cost and highly stable solution for IoT applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4979-4983"},"PeriodicalIF":4.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-25DOI: 10.1109/TCSII.2024.3433430
Sanjeev Ranjan;Somanath Majhi
This brief addresses the attitude stabilization problem of unmanned aerial vehicles (UAVs) like quadrotors with uncertain inertia, external disturbances, and actuator faults simultaneously in predefined time. The adaptive predefined-time sliding mode control (SMC) incorporated with a radial basis function neural network (RBFNN) is designed to track the desired trajectory and estimate the uncertainty of the system effectively to enhance the control performance. The proposed control strategy utilizes the sliding manifold, which ensures state convergence in a predefined time. The settling time of the presented control scheme can be arbitrarily chosen in advance compared to the traditional fixed-time and finite-time control strategies. The boundedness of the complete system is verified using Lyapunov stability theory. Finally, comparative results are presented to demonstrate the effectiveness of the proposed control scheme.
{"title":"Adaptive Neural Predefined-Time Attitude Control of an Uncertain Quadrotor UAV With Actuator Fault","authors":"Sanjeev Ranjan;Somanath Majhi","doi":"10.1109/TCSII.2024.3433430","DOIUrl":"10.1109/TCSII.2024.3433430","url":null,"abstract":"This brief addresses the attitude stabilization problem of unmanned aerial vehicles (UAVs) like quadrotors with uncertain inertia, external disturbances, and actuator faults simultaneously in predefined time. The adaptive predefined-time sliding mode control (SMC) incorporated with a radial basis function neural network (RBFNN) is designed to track the desired trajectory and estimate the uncertainty of the system effectively to enhance the control performance. The proposed control strategy utilizes the sliding manifold, which ensures state convergence in a predefined time. The settling time of the presented control scheme can be arbitrarily chosen in advance compared to the traditional fixed-time and finite-time control strategies. The boundedness of the complete system is verified using Lyapunov stability theory. Finally, comparative results are presented to demonstrate the effectiveness of the proposed control scheme.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4939-4943"},"PeriodicalIF":4.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-23DOI: 10.1109/TCSII.2024.3432621
Zhiying Xia;Zhiqun Li;Bofan Chen;Xiaowei Wang
An X-band active digital step attenuator (DSA) with a novel phase error minimization technique for phased-array applications is presented in this brief. Based on the analysis of the phase variation characteristic during gain tuning in the conventional current-steering variable gain amplifier (VGA), an inductive phase compensation unit with an opposite insertion phase response is developed herein, achieving an effective phase error reduction. The proposed active DSA is fabricated in SMIC 40-nm CMOS process, occupying a core area of 0.27 mm2. The measurement results exhibit an attenuation tuning range of 20 dB with 0.5 dB steps, while the root-mean-square (rms) gain error and rms phase error within 8–12 GHz are better than 0.34 dB and 1.85°, respectively. At the minimum attenuation state, the peak gain is −1.3 dB and the gain variation is less than 0.3 dB. In addition, the input 1 dB compression point (IP1dB) varies from 2.4 to 3.1 dBm while the power consumption is 13.6 mW.
{"title":"An X-Band Active Digital Step Attenuator With Complementary Phase Variation Compensation","authors":"Zhiying Xia;Zhiqun Li;Bofan Chen;Xiaowei Wang","doi":"10.1109/TCSII.2024.3432621","DOIUrl":"10.1109/TCSII.2024.3432621","url":null,"abstract":"An X-band active digital step attenuator (DSA) with a novel phase error minimization technique for phased-array applications is presented in this brief. Based on the analysis of the phase variation characteristic during gain tuning in the conventional current-steering variable gain amplifier (VGA), an inductive phase compensation unit with an opposite insertion phase response is developed herein, achieving an effective phase error reduction. The proposed active DSA is fabricated in SMIC 40-nm CMOS process, occupying a core area of 0.27 mm2. The measurement results exhibit an attenuation tuning range of 20 dB with 0.5 dB steps, while the root-mean-square (rms) gain error and rms phase error within 8–12 GHz are better than 0.34 dB and 1.85°, respectively. At the minimum attenuation state, the peak gain is −1.3 dB and the gain variation is less than 0.3 dB. In addition, the input 1 dB compression point (IP1dB) varies from 2.4 to 3.1 dBm while the power consumption is 13.6 mW.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4834-4838"},"PeriodicalIF":4.0,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-22DOI: 10.1109/TCSII.2024.3432528
Youming Zhang;Fengyi Huang;Xusheng Tang;Zhennan Wei;Yunqi Cao;Junjie Li;Zhengyang Li
This brief presents a high accuracy high linearity K-band 4-channel phased array receiver for satellite communication (SATCOM). Structural improvement and parameter optimization have been carried out to enhance the phase and gain control precision. The presented receiver employs a novel $L-C$ compensation and variable resistance technique in the quadrature all-pass filter (QAF) for phase shifter (PS) to reduce the phase error. Neutralization capacitance and redundancy control bit are adopted in the attenuator (ATT) to reduce the gain error. A 3-stage low noise amplifier (LNA) has been optimized to provide high gain, high input-referred 1-dB gain compression point and low noise. The receiver achieves a 360° phase shifting range with a 6-bit resolution and a 31.5 dB attenuation range with 0.5 dB step. The measured root mean square (RMS) phase error and gain error are 0.78° – 1.22° and 0.14–0.32 dB, respectively, over the frequency of 17 GHz to 23 GHz. Each channel achieves a measured gain of 23 dB, an input-referred 1-dB gain compression point (IP1dB) of −29.8 dBm at the maximum gain, and a low noise figure (NF) of 3.4–3.9 dB. The 4-channel receiver is implemented in 40-nm CMOS process and occupies a chip area of 3.85 mm2.
{"title":"0.78–1.22° RMS Phase Error, 0.14–0.32 dB RMS Gain Error, K-Band 4-Channel Phased Array Receiver IC for Satcom on the Move (SOTM)","authors":"Youming Zhang;Fengyi Huang;Xusheng Tang;Zhennan Wei;Yunqi Cao;Junjie Li;Zhengyang Li","doi":"10.1109/TCSII.2024.3432528","DOIUrl":"10.1109/TCSII.2024.3432528","url":null,"abstract":"This brief presents a high accuracy high linearity K-band 4-channel phased array receiver for satellite communication (SATCOM). Structural improvement and parameter optimization have been carried out to enhance the phase and gain control precision. The presented receiver employs a novel \u0000<inline-formula> <tex-math>$L-C$ </tex-math></inline-formula>\u0000 compensation and variable resistance technique in the quadrature all-pass filter (QAF) for phase shifter (PS) to reduce the phase error. Neutralization capacitance and redundancy control bit are adopted in the attenuator (ATT) to reduce the gain error. A 3-stage low noise amplifier (LNA) has been optimized to provide high gain, high input-referred 1-dB gain compression point and low noise. The receiver achieves a 360° phase shifting range with a 6-bit resolution and a 31.5 dB attenuation range with 0.5 dB step. The measured root mean square (RMS) phase error and gain error are 0.78° – 1.22° and 0.14–0.32 dB, respectively, over the frequency of 17 GHz to 23 GHz. Each channel achieves a measured gain of 23 dB, an input-referred 1-dB gain compression point (IP1dB) of −29.8 dBm at the maximum gain, and a low noise figure (NF) of 3.4–3.9 dB. The 4-channel receiver is implemented in 40-nm CMOS process and occupies a chip area of 3.85 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4869-4873"},"PeriodicalIF":4.0,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A range of quantum-, optical- and CMOS-based approaches have been explored to solve Nondeterministic polynomial-time hard (NP-hard) combinatorial optimization problems (COPs), of which we consider ring oscillator (ROSC) coupled Ising machine to be highly prospective. This brief proposed a scalable ROSC-based Ising machine with capacity coupling and phase drift eliminator. The coupling module consisting of two MOSCAPs and several switch transistors allows for nine coupling strengths, which can be arbitrarily configured into different weight resolutions, and shows resilience to capacitance variations. Phase drift eliminator was designed to alleviate the effect of intrinsic noise within the ROSC array, which ensures accurate readout of the spin state. The area of the readout circuit is only 32% of the previous phase-sampling circuit. We also proposed a progressive annealing method inspired by quantum adiabatic annealing, which is easy to perform on ROSC-based Ising machines and does not require additional random number generators. After applying the progressive annealing method, accuracy can be achieved up to 98% for randomly generated contentious problems.
{"title":"A 1024-Spin Scalable Ising Machine With Capacitive Coupling and Progressive Annealing Method for Combination Optimization Problems","authors":"Yixuan Liu;Zhongze Han;Qiqiao Wu;Honghu Yang;Yue Cao;Yongkang Han;Haijun Jiang;Xiaoyong Xue;Jianguo Yang;Xiaoyang Zeng","doi":"10.1109/TCSII.2024.3432799","DOIUrl":"10.1109/TCSII.2024.3432799","url":null,"abstract":"A range of quantum-, optical- and CMOS-based approaches have been explored to solve Nondeterministic polynomial-time hard (NP-hard) combinatorial optimization problems (COPs), of which we consider ring oscillator (ROSC) coupled Ising machine to be highly prospective. This brief proposed a scalable ROSC-based Ising machine with capacity coupling and phase drift eliminator. The coupling module consisting of two MOSCAPs and several switch transistors allows for nine coupling strengths, which can be arbitrarily configured into different weight resolutions, and shows resilience to capacitance variations. Phase drift eliminator was designed to alleviate the effect of intrinsic noise within the ROSC array, which ensures accurate readout of the spin state. The area of the readout circuit is only 32% of the previous phase-sampling circuit. We also proposed a progressive annealing method inspired by quantum adiabatic annealing, which is easy to perform on ROSC-based Ising machines and does not require additional random number generators. After applying the progressive annealing method, accuracy can be achieved up to 98% for randomly generated contentious problems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5009-5013"},"PeriodicalIF":4.0,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-18DOI: 10.1109/TCSII.2024.3430954
Yue Geng;Xiao Hu;Zhongfeng Wang
Homomorphic encryption (HE) has recently become a promising approach to guarantee the privacy security in cloud computing. Number theoretic transform (NTT) can be used to accelerate the polynomial multiplication in HE, but is usually considered the performance bottleneck of HE schemes. This brief introduces GS-MDC, a high-speed and area-efficient NTT design combining multi-path delay commutator (MDC) architecture and GS butterfly units (GS-BUs). Exploiting the characteristics of GS-BU, a novel permute-in-computation (PiC) technique is proposed to reduce total computing cycles. GS-MDC is also designed to be reconfigurable for both NTT and INTT. Moreover, we put forward a hybrid storage method for twiddle factors to promote memory utilization efficiency. Experimental results on FPGA show that our design can achieve higher throughput and area efficiency compared with previous works.
{"title":"GS-MDC: High-Speed and Area-Efficient Number Theoretic Transform Design","authors":"Yue Geng;Xiao Hu;Zhongfeng Wang","doi":"10.1109/TCSII.2024.3430954","DOIUrl":"10.1109/TCSII.2024.3430954","url":null,"abstract":"Homomorphic encryption (HE) has recently become a promising approach to guarantee the privacy security in cloud computing. Number theoretic transform (NTT) can be used to accelerate the polynomial multiplication in HE, but is usually considered the performance bottleneck of HE schemes. This brief introduces GS-MDC, a high-speed and area-efficient NTT design combining multi-path delay commutator (MDC) architecture and GS butterfly units (GS-BUs). Exploiting the characteristics of GS-BU, a novel permute-in-computation (PiC) technique is proposed to reduce total computing cycles. GS-MDC is also designed to be reconfigurable for both NTT and INTT. Moreover, we put forward a hybrid storage method for twiddle factors to promote memory utilization efficiency. Experimental results on FPGA show that our design can achieve higher throughput and area efficiency compared with previous works.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4974-4978"},"PeriodicalIF":4.0,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141738734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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