Pub Date : 2024-09-17DOI: 10.1109/tcsii.2024.3462557
Nannan Li, Hanrui Zhang, Bin Liu, Lei Pei, Jinfu Wang, Huanhuan Qi, Jie Zhang, Xiaofei Wang, Hong Zhang
{"title":"A 10-bit 500-MS/s Pipelined SAR ADC With Nonlinearity-Compensated Open-loop Amplifier and Parallel Conversion Through Comparator Reusing","authors":"Nannan Li, Hanrui Zhang, Bin Liu, Lei Pei, Jinfu Wang, Huanhuan Qi, Jie Zhang, Xiaofei Wang, Hong Zhang","doi":"10.1109/tcsii.2024.3462557","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3462557","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"26 1","pages":""},"PeriodicalIF":4.4,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142268061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-16DOI: 10.1109/TCSII.2024.3460809
Shixing Li;Chenyi Wang;Zhongzhen Tong;Chao Wang;Bi Wang;Zhaohao Wang
As process nodes shrink to deep nanometer scales, the heightened sensitivity of digital circuits to radiation and the dramatic rise in leakage power have become pressing concerns. Magnetic tunnel junction (MTJ) possesses intrinsic radiation resistance and nonvolatility and can be integrated with CMOS processes. Therefore, designing MTJ-based radiation-hardened nonvolatile storage elements is a promising solution to address these issues. In this brief, we propose a novel MTJ-based radiation-hardened, speed and power optimized nonvolatile (RH-SPO) latch and compares it with existing designs to evaluate its performance. Using a 28 nm CMOS process, simulation results confirm that the proposed RH-SPO latch offers moderate radiation resistance and high robustness performance with backup and restore operations. Additionally, compared to state-of-the-art design, named M-8C, it can save up to 50% in area overhead, reduce transmission-restore power consumption and restore time by 98% and 75%, respectively.
{"title":"A Novel Radiation-Hardened, Speed and Power Optimized Nonvolatile Latch for Aerospace Applications","authors":"Shixing Li;Chenyi Wang;Zhongzhen Tong;Chao Wang;Bi Wang;Zhaohao Wang","doi":"10.1109/TCSII.2024.3460809","DOIUrl":"10.1109/TCSII.2024.3460809","url":null,"abstract":"As process nodes shrink to deep nanometer scales, the heightened sensitivity of digital circuits to radiation and the dramatic rise in leakage power have become pressing concerns. Magnetic tunnel junction (MTJ) possesses intrinsic radiation resistance and nonvolatility and can be integrated with CMOS processes. Therefore, designing MTJ-based radiation-hardened nonvolatile storage elements is a promising solution to address these issues. In this brief, we propose a novel MTJ-based radiation-hardened, speed and power optimized nonvolatile (RH-SPO) latch and compares it with existing designs to evaluate its performance. Using a 28 nm CMOS process, simulation results confirm that the proposed RH-SPO latch offers moderate radiation resistance and high robustness performance with backup and restore operations. Additionally, compared to state-of-the-art design, named M-8C, it can save up to 50% in area overhead, reduce transmission-restore power consumption and restore time by 98% and 75%, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"178-182"},"PeriodicalIF":4.0,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142267837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-16DOI: 10.1109/TCSII.2024.3461338
Han Yang;Lin Huang;Xiangwei Zhang;Yuqi Wang;Qiankun Zhao;Ying Hou;Xiaosong Wang;Yu Liu
This brief presents an energy-efficient continuous-time incremental delta-sigma modulator (CT IDSM), where the first integrator employs a fourth-order feedforward-compensated amplifier based on an AC-coupled OTA-stacking amplifier (AC-OSA) and utilizes a charge neutralization reset scheme (CNRS). Extending the AC-OSA to incremental structures significantly improves the energy efficiency of the ADC. The core innovation is the use of CNRS for periodic resets, addressing common-mode (CM) disturbances and incomplete differential-mode (DM) signal resets caused by the conventional shorted integration capacitor scheme. Additionally, to enhance area and power efficiency when using high-tap FIR DACs in CT IDSMs, we propose an excess-loop-delay compensation (ELDC) FIR DAC suitable for single-bit (SB) architectures. A third-order single-loop SB CT IDSM with an eight-tap FIR DAC is fabricated in a 65nm CMOS process and achieves SNDR, SNR, and DR values of 81.5dB, 81.8dB, and 85dB, respectively at a Nyquist conversion rate of 200kS/s. The core area is 0.227mm2, and the ADC consumes $275{mu }$ W. The Schreier (SNDR) figure-of-merit (FoM) is 167.1dB.
{"title":"A 275 μ W 81.5 dB-SNDR and 200 kS/s CT IDSM With an AC-OSA-Based Integrator Using CNRS and FIR DACs","authors":"Han Yang;Lin Huang;Xiangwei Zhang;Yuqi Wang;Qiankun Zhao;Ying Hou;Xiaosong Wang;Yu Liu","doi":"10.1109/TCSII.2024.3461338","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3461338","url":null,"abstract":"This brief presents an energy-efficient continuous-time incremental delta-sigma modulator (CT IDSM), where the first integrator employs a fourth-order feedforward-compensated amplifier based on an AC-coupled OTA-stacking amplifier (AC-OSA) and utilizes a charge neutralization reset scheme (CNRS). Extending the AC-OSA to incremental structures significantly improves the energy efficiency of the ADC. The core innovation is the use of CNRS for periodic resets, addressing common-mode (CM) disturbances and incomplete differential-mode (DM) signal resets caused by the conventional shorted integration capacitor scheme. Additionally, to enhance area and power efficiency when using high-tap FIR DACs in CT IDSMs, we propose an excess-loop-delay compensation (ELDC) FIR DAC suitable for single-bit (SB) architectures. A third-order single-loop SB CT IDSM with an eight-tap FIR DAC is fabricated in a 65nm CMOS process and achieves SNDR, SNR, and DR values of 81.5dB, 81.8dB, and 85dB, respectively at a Nyquist conversion rate of 200kS/s. The core area is 0.227mm2, and the ADC consumes \u0000<inline-formula> <tex-math>$275{mu }$ </tex-math></inline-formula>\u0000W. The Schreier (SNDR) figure-of-merit (FoM) is 167.1dB.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"23-27"},"PeriodicalIF":4.0,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-13DOI: 10.1109/TCSII.2024.3460171
Kang-Li Xu;Zhen Li;Peter Benner
Based on Riemannian geometry of Grassmann manifolds and discrete Laguerre polynomials, we propose a parametric interpolation parallel MOR method for discrete-time parametric systems. First, a block discrete Fourier transform-based (BDFT) parallel strategy is presented to construct the local basis matrices, which achieves two level acceleration by parallelization. Further, using the retractions and vector transports on Grassmann manifolds, the basis matrix for a new parameter is obtained by interpolating the local bases on the tangent spaces at the different reference points. Finally, a numerical example is used to demonstrate the efficiency of our method.
{"title":"Parametric Interpolation Model Order Reduction on Grassmann Manifolds by Parallelization","authors":"Kang-Li Xu;Zhen Li;Peter Benner","doi":"10.1109/TCSII.2024.3460171","DOIUrl":"10.1109/TCSII.2024.3460171","url":null,"abstract":"Based on Riemannian geometry of Grassmann manifolds and discrete Laguerre polynomials, we propose a parametric interpolation parallel MOR method for discrete-time parametric systems. First, a block discrete Fourier transform-based (BDFT) parallel strategy is presented to construct the local basis matrices, which achieves two level acceleration by parallelization. Further, using the retractions and vector transports on Grassmann manifolds, the basis matrix for a new parameter is obtained by interpolating the local bases on the tangent spaces at the different reference points. Finally, a numerical example is used to demonstrate the efficiency of our method.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"198-202"},"PeriodicalIF":4.0,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142267839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-13DOI: 10.1109/TCSII.2024.3460072
Mehran Ghahramani;Hamed Hoznian;Amir Nikpaik
This brief proposes a structure to enhance the bandwidth of type-I sub-sampling phase-locked loops (SSPLL) without compromising the loop stability. A voltage-controlled delay line (VCDL) is employed at the output of the voltage-controlled oscillator (VCO) to readjust the phase of the VCO. The delay of this VCDL is controlled based on the instantaneous phase of the VCO, extracted at the output of the phase detector. Using theoretical analysis and simulations, it is proved that the bandwidth of the VCO phase noise to the output phase noise transfer function can increase up to $ {0.4f_{text {REF}}}$ while maintaining phase margin. This enhanced bandwidth improves the VCO phase noise filtering strength of the PLL, leading to a superior jitter performance. The phase-domain model reveals a significant reduction in integrated jitter, compared to conventional type-I and type-II SSPLL, respectively. Furthermore, it is shown that the jitter reduction capability in the proposed loop remains robust against temperature and process variations.
{"title":"A Bandwidth Extension Technique for Improving Jitter in Ring-VCO-Based Sub-Sampling PLLs","authors":"Mehran Ghahramani;Hamed Hoznian;Amir Nikpaik","doi":"10.1109/TCSII.2024.3460072","DOIUrl":"10.1109/TCSII.2024.3460072","url":null,"abstract":"This brief proposes a structure to enhance the bandwidth of type-I sub-sampling phase-locked loops (SSPLL) without compromising the loop stability. A voltage-controlled delay line (VCDL) is employed at the output of the voltage-controlled oscillator (VCO) to readjust the phase of the VCO. The delay of this VCDL is controlled based on the instantaneous phase of the VCO, extracted at the output of the phase detector. Using theoretical analysis and simulations, it is proved that the bandwidth of the VCO phase noise to the output phase noise transfer function can increase up to \u0000<inline-formula> <tex-math>$ {0.4f_{text {REF}}}$ </tex-math></inline-formula>\u0000 while maintaining phase margin. This enhanced bandwidth improves the VCO phase noise filtering strength of the PLL, leading to a superior jitter performance. The phase-domain model reveals a significant reduction in integrated jitter, compared to conventional type-I and type-II SSPLL, respectively. Furthermore, it is shown that the jitter reduction capability in the proposed loop remains robust against temperature and process variations.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"123-127"},"PeriodicalIF":4.0,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142267838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gate-all-around carbon nanotube field-effect-transistors (GAA-CNTFETs) and voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) are expected to realize significant savings in energy consumption and computing delay compared to the existing silicon-based FinFETs. This brief proposes an in-MRAM computing macro based on a newly developed complementary-sensing time-based readout circuit (CSTRC) to accelerate binary neural networks (BNNs). An 8 kb MRAM was simulated using both GAA-CNTFET/VGSOT-MTJ and 14 nm FinFET/VGSOT-MTJ technologies to validate the effectiveness of the proposed design. The proposed CSTRC can achieve read operations and binary multiply-and-accumulate (BMAC) without additional peripheral circuits and achieve a notable decrease in the read bit error rate and column-level conditional row error rate by 1–5 and 1–13 orders of magnitude, respectively, compared to those reported previously. Moreover, under the GAA-CNTFET/VGSOT-MTJ process, the read energy consumption and delay were reduced by 59.1–78.9% and 23.9–29.7%, respectively; the BMAC energy efficiency and throughput were 10231 1-b TOPS/W and 1.8 TOPS, respectively increased by 2.9 and 1.27 times at 0.8 V supply voltage when comparing to its 14-nm FinFET /VGSOT-MTJ counterparts.
{"title":"In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET","authors":"Zhongzhen Tong;Sifan Sun;Kaili Zhang;Chenghang Li;Daming Zhou;Zhaohao Wang;Xiaoyang Lin;Weisheng Zhao","doi":"10.1109/TCSII.2024.3460169","DOIUrl":"10.1109/TCSII.2024.3460169","url":null,"abstract":"Gate-all-around carbon nanotube field-effect-transistors (GAA-CNTFETs) and voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) are expected to realize significant savings in energy consumption and computing delay compared to the existing silicon-based FinFETs. This brief proposes an in-MRAM computing macro based on a newly developed complementary-sensing time-based readout circuit (CSTRC) to accelerate binary neural networks (BNNs). An 8 kb MRAM was simulated using both GAA-CNTFET/VGSOT-MTJ and 14 nm FinFET/VGSOT-MTJ technologies to validate the effectiveness of the proposed design. The proposed CSTRC can achieve read operations and binary multiply-and-accumulate (BMAC) without additional peripheral circuits and achieve a notable decrease in the read bit error rate and column-level conditional row error rate by 1–5 and 1–13 orders of magnitude, respectively, compared to those reported previously. Moreover, under the GAA-CNTFET/VGSOT-MTJ process, the read energy consumption and delay were reduced by 59.1–78.9% and 23.9–29.7%, respectively; the BMAC energy efficiency and throughput were 10231 1-b TOPS/W and 1.8 TOPS, respectively increased by 2.9 and 1.27 times at 0.8 V supply voltage when comparing to its 14-nm FinFET /VGSOT-MTJ counterparts.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"173-177"},"PeriodicalIF":4.0,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142267840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-12DOI: 10.1109/TCSII.2024.3458975
Yani Li;Zonghui Li;Libo Qian;Xiudeng Wang;Zhangming Zhu
This brief proposes a low quiescent current fast transient low-dropout regulator (LDO). The pass field-effect transistor (FET) in the LDO is segmented into three sections to cope with different loads. Under no-load mode, the smallest-sized pass transistor is directly driven by the error amplifier (EA) for low quiescent current. At light- and heavy- load modes, the medium and largest sized pass FETs are respectively switched on by different strength buffers for fast transient response. The proposed LDO is implemented in a $0.18~mu $ m BCD process with an active area of 0.0875 mm2. The LDO consumes a quiescent current of 25 nA at no-load condition, with an input voltage range of 1.5 V-5.5 V and an output voltage range of 1.2 V-5 V. The measured transient output voltage is 28 mV when load current is switched from 0 mA to 200 mA in 100 ns with $1~mu $ F load capacitance. The recovery time is about $1~mu $ s. Compared to reported counterparts, the proposed LDO shows an excellent figure-of-merit (FOM).
{"title":"A Low Quiescent Current Fast Transient LDO Regulator With Segmented Pass Transistors","authors":"Yani Li;Zonghui Li;Libo Qian;Xiudeng Wang;Zhangming Zhu","doi":"10.1109/TCSII.2024.3458975","DOIUrl":"10.1109/TCSII.2024.3458975","url":null,"abstract":"This brief proposes a low quiescent current fast transient low-dropout regulator (LDO). The pass field-effect transistor (FET) in the LDO is segmented into three sections to cope with different loads. Under no-load mode, the smallest-sized pass transistor is directly driven by the error amplifier (EA) for low quiescent current. At light- and heavy- load modes, the medium and largest sized pass FETs are respectively switched on by different strength buffers for fast transient response. The proposed LDO is implemented in a \u0000<inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>\u0000m BCD process with an active area of 0.0875 mm2. The LDO consumes a quiescent current of 25 nA at no-load condition, with an input voltage range of 1.5 V-5.5 V and an output voltage range of 1.2 V-5 V. The measured transient output voltage is 28 mV when load current is switched from 0 mA to 200 mA in 100 ns with \u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000 F load capacitance. The recovery time is about \u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000s. Compared to reported counterparts, the proposed LDO shows an excellent figure-of-merit (FOM).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"13-17"},"PeriodicalIF":4.0,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-12DOI: 10.1109/TCSII.2024.3459091
Ahmed S. Elwakil;Anis Allagui;Mohamed B. Elamien;Costas Psychalinos;Brent Maundy
We derive closed form expressions for the input impedance of two-dimensional (2-D) infinite ladder-tree and tree-ladder networks using the combination of results for the input impedance of an infinite 1-D ladder network and an infinite 1-D tree network. We show that the effect of the number of branches in the tree network can always be absorbed via impedance scaling resulting in a universal formula derived in this brief. The meaningful number of branches of the tree network is shown to be either two branches; i.e., a binary tree, or four branches; i.e., a quaternary tree. Special cases of component choices are investigated, and both circuit simulations and experimental results are provided to validate the theory.
{"title":"Closed-Form Expressions for the Input Impedance of Some 2-D Fractal Circuit Networks","authors":"Ahmed S. Elwakil;Anis Allagui;Mohamed B. Elamien;Costas Psychalinos;Brent Maundy","doi":"10.1109/TCSII.2024.3459091","DOIUrl":"10.1109/TCSII.2024.3459091","url":null,"abstract":"We derive closed form expressions for the input impedance of two-dimensional (2-D) infinite ladder-tree and tree-ladder networks using the combination of results for the input impedance of an infinite 1-D ladder network and an infinite 1-D tree network. We show that the effect of the number of branches in the tree network can always be absorbed via impedance scaling resulting in a universal formula derived in this brief. The meaningful number of branches of the tree network is shown to be either two branches; i.e., a binary tree, or four branches; i.e., a quaternary tree. Special cases of component choices are investigated, and both circuit simulations and experimental results are provided to validate the theory.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"18-22"},"PeriodicalIF":4.0,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Integer polynomial multiplication has been frequently used in post-quantum cryptography and fully homomorphic encryption systems. Particularly, there exists a special polynomial multiplication, where the polynomial degree can be a power of two and the coefficients of the two input polynomials are unequal-sized (difficult to deploy fast algorithm for implementation efficiency). Following this direction, in this brief, we propose a novel hardware-implemented Lightweight and Timing-Efficient (LTE) integer polynomial multiplication design framework. We proposed two new algorithms for efficient implementation of the targeted polynomial multiplication. Accordingly, we presented two hardware accelerators with the help of several new hardware design techniques. The final implementation showcases the proposed accelerators’ superior performance, e.g., the proposed Accelerator-I $(v=512)$ has 44.7% less equivalent area-delay product (EADP) than the state-of-the-art design for $n=4,096$ , while the proposed Accelerator-II has at least 38.7% less ADP than the competing designs for $n=1,024$ . The proposed strategy is highly efficient and can be extended for other usage.
{"title":"LTE: Lightweight and Timing-Efficient Unequal-Sized Polynomial Multiplication Accelerators","authors":"Yazheng Tu;Tianyou Bao;Pengzhou He;Leonel Sousa;Jiafeng Xie","doi":"10.1109/TCSII.2024.3458871","DOIUrl":"10.1109/TCSII.2024.3458871","url":null,"abstract":"Integer polynomial multiplication has been frequently used in post-quantum cryptography and fully homomorphic encryption systems. Particularly, there exists a special polynomial multiplication, where the polynomial degree can be a power of two and the coefficients of the two input polynomials are unequal-sized (difficult to deploy fast algorithm for implementation efficiency). Following this direction, in this brief, we propose a novel hardware-implemented Lightweight and Timing-Efficient (LTE) integer polynomial multiplication design framework. We proposed two new algorithms for efficient implementation of the targeted polynomial multiplication. Accordingly, we presented two hardware accelerators with the help of several new hardware design techniques. The final implementation showcases the proposed accelerators’ superior performance, e.g., the proposed Accelerator-I \u0000<inline-formula> <tex-math>$(v=512)$ </tex-math></inline-formula>\u0000 has 44.7% less equivalent area-delay product (EADP) than the state-of-the-art design for \u0000<inline-formula> <tex-math>$n=4,096$ </tex-math></inline-formula>\u0000, while the proposed Accelerator-II has at least 38.7% less ADP than the competing designs for \u0000<inline-formula> <tex-math>$n=1,024$ </tex-math></inline-formula>\u0000. The proposed strategy is highly efficient and can be extended for other usage.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"253-257"},"PeriodicalIF":4.0,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-10DOI: 10.1109/TCSII.2024.3457494
Jianfei Wang;Jia Hou;Fahong Zhang;Yishuo Meng;Yang Su;Chen Yang
In this brief, an improved and efficient Winograd-based Large Integer Multiplication using least-positive form named WLIM is proposed, which can reduce 28.61% to 33.33% of the number of multiplications compared to least-positive form direct multiplication. By exploiting the cyclic parallelism of the improved algorithm, an Efficient and Parallelism-Scalable Large Integer Multiplier architecture named EPSM is proposed, which has two levels of adjustable parallelism. EPSM is implemented on Xilinx Virtex-7 VC709 Board, Zynq UltraScale+ XZCU19EG Device, and Alveo U250 Card, by using Vivado. Compared with the related works, EPSM can achieve a performance improvement of $1.29times sim ~20.99times $ . In terms of area efficiency, EPSM can achieve $3.54times sim ~41.41times $ area-time product (ATP) improvements.
{"title":"An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm","authors":"Jianfei Wang;Jia Hou;Fahong Zhang;Yishuo Meng;Yang Su;Chen Yang","doi":"10.1109/TCSII.2024.3457494","DOIUrl":"10.1109/TCSII.2024.3457494","url":null,"abstract":"In this brief, an improved and efficient Winograd-based Large Integer Multiplication using least-positive form named WLIM is proposed, which can reduce 28.61% to 33.33% of the number of multiplications compared to least-positive form direct multiplication. By exploiting the cyclic parallelism of the improved algorithm, an Efficient and Parallelism-Scalable Large Integer Multiplier architecture named EPSM is proposed, which has two levels of adjustable parallelism. EPSM is implemented on Xilinx Virtex-7 VC709 Board, Zynq UltraScale+ XZCU19EG Device, and Alveo U250 Card, by using Vivado. Compared with the related works, EPSM can achieve a performance improvement of \u0000<inline-formula> <tex-math>$1.29times sim ~20.99times $ </tex-math></inline-formula>\u0000. In terms of area efficiency, EPSM can achieve \u0000<inline-formula> <tex-math>$3.54times sim ~41.41times $ </tex-math></inline-formula>\u0000 area-time product (ATP) improvements.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"248-252"},"PeriodicalIF":4.0,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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