Pub Date : 2024-10-23DOI: 10.1109/TCSII.2024.3485493
Akash Dev Roshan;Prithwijit Guha;Gaurav Trivedi
The sigmoid and $hyperbolic tangent~(tanh)$ functions are widely recognized as the most commonly employed nonlinear activation functions in artificial neural networks. These functions incorporate exponential terms to introduce nonlinearity, which imposes significant challenges when realized on hardware. This brief presents a novel approach for the hardware implementation of sigmoid and tanh functions, leveraging a regression tree and linear regression. The proposed method divides their nonlinear region into small segments using a regression tree. These segments are further approximated using a linear regression technique, the line of best fit. Experimental results demonstrate the average errors of $4times 10^{-4}$ and $9times 10^{-4}$ of sigmoid and tanh functions compared to exact functions. The above functions produce 24.52% and 35.71% less average error than the best contemporary method when implemented on the hardware. Additionally, the hardware implementations of sigmoid and tanh functions are more area, power and delay efficient, showcasing the effectiveness of this method compared to other state-of-the-art designs.
{"title":"Hardware-Optimized Regression Tree-Based Sigmoid and Tanh Functions for Machine Learning Applications","authors":"Akash Dev Roshan;Prithwijit Guha;Gaurav Trivedi","doi":"10.1109/TCSII.2024.3485493","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485493","url":null,"abstract":"The sigmoid and \u0000<inline-formula> <tex-math>$hyperbolic tangent~(tanh)$ </tex-math></inline-formula>\u0000 functions are widely recognized as the most commonly employed nonlinear activation functions in artificial neural networks. These functions incorporate exponential terms to introduce nonlinearity, which imposes significant challenges when realized on hardware. This brief presents a novel approach for the hardware implementation of sigmoid and tanh functions, leveraging a regression tree and linear regression. The proposed method divides their nonlinear region into small segments using a regression tree. These segments are further approximated using a linear regression technique, the line of best fit. Experimental results demonstrate the average errors of \u0000<inline-formula> <tex-math>$4times 10^{-4}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$9times 10^{-4}$ </tex-math></inline-formula>\u0000 of sigmoid and tanh functions compared to exact functions. The above functions produce 24.52% and 35.71% less average error than the best contemporary method when implemented on the hardware. Additionally, the hardware implementations of sigmoid and tanh functions are more area, power and delay efficient, showcasing the effectiveness of this method compared to other state-of-the-art designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"283-287"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief proposes a temperature-compensated Ku-band eight-element four-beam phased-array receiver with low attenuation and relative phase variations. By properly adjusting the gate voltage of the switch MOSFETs in the 6-bit step attenuator, the resistance of MOSFETs can remain constant with temperature variation. Furthermore, the attenuation and relative phase errors caused by ambient temperature variations can be effectively decreased to meet the requirements of phased-array systems. To verify the proposed method, an eight-element 10.7–12.7 GHz phased-array receiver is designed and fabricated using a 130-nm silicon-germanium (SiGe) BiCMOS process. With the help of minimized attenuation and phase variations, the phased-array receiver exhibits a root-mean-square (RMS) attenuation error less than 0.71 dB and a RMS relative phase error less than 2.7° from −40°C to 85°C at 10.7-12.7 GHz. Meanwhile, the measured noise figure (NF) and single-channel gain are 1.1-2.5 dB and 21.2-27.8 dB, respectively.
{"title":"A Temperature-Compensated Ku-Band Four-Beam Phased-Array Receiver With Low Attenuation and Relative Phase Variations","authors":"Shi Chao Jin;Jiaxing Sun;Zhuoheng Xie;Bo Huang;Dunge Liu;Yuqian Yang;Chenyu Mei;Jun Huang;Chenyu Wang;Xiulong Wu;Yu Jian Cheng","doi":"10.1109/TCSII.2024.3485476","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485476","url":null,"abstract":"This brief proposes a temperature-compensated Ku-band eight-element four-beam phased-array receiver with low attenuation and relative phase variations. By properly adjusting the gate voltage of the switch MOSFETs in the 6-bit step attenuator, the resistance of MOSFETs can remain constant with temperature variation. Furthermore, the attenuation and relative phase errors caused by ambient temperature variations can be effectively decreased to meet the requirements of phased-array systems. To verify the proposed method, an eight-element 10.7–12.7 GHz phased-array receiver is designed and fabricated using a 130-nm silicon-germanium (SiGe) BiCMOS process. With the help of minimized attenuation and phase variations, the phased-array receiver exhibits a root-mean-square (RMS) attenuation error less than 0.71 dB and a RMS relative phase error less than 2.7° from −40°C to 85°C at 10.7-12.7 GHz. Meanwhile, the measured noise figure (NF) and single-channel gain are 1.1-2.5 dB and 21.2-27.8 dB, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"83-87"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Spiking neural network (SNN) based mixed-signal neuromorphic hardware gives high benefit in terms of speed and energy efficiency compared to conventional computing platform, thanks to its energy efficient data processing nature. However, on-chip realization of Poisson spike train to represent spike-encoded data has not yet fully achieved. Furthermore, the analog circuit components in mixed-signal neuromorphic hardwares are prone to variations which might lead to accuracy drop in SNN applications. In this brief, we demonstrated robust noise induced spike pulse generator for on-chip realization of Poisson spike train. The stochastic sigmoid neuron developed in our work exhibits better robustness than LIF neurons towards diverse RRAM device variation factors: 1) Random Telegraph Noise (RTN), 2) Stuck-At-Faults (SAFs) and 3) Endurance failures, guaranteeing robust SNN application.
{"title":"All Stochastic-Spiking Neural Network (AS-SNN): Noise Induced Spike Pulse Generator for Input and Output Neurons With Resistive Synaptic Array","authors":"Honggu Kim;Yerim An;Minchul Kim;Gyeong-Chan Heo;Yong Shim","doi":"10.1109/TCSII.2024.3485178","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485178","url":null,"abstract":"Spiking neural network (SNN) based mixed-signal neuromorphic hardware gives high benefit in terms of speed and energy efficiency compared to conventional computing platform, thanks to its energy efficient data processing nature. However, on-chip realization of Poisson spike train to represent spike-encoded data has not yet fully achieved. Furthermore, the analog circuit components in mixed-signal neuromorphic hardwares are prone to variations which might lead to accuracy drop in SNN applications. In this brief, we demonstrated robust noise induced spike pulse generator for on-chip realization of Poisson spike train. The stochastic sigmoid neuron developed in our work exhibits better robustness than LIF neurons towards diverse RRAM device variation factors: 1) Random Telegraph Noise (RTN), 2) Stuck-At-Faults (SAFs) and 3) Endurance failures, guaranteeing robust SNN application.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"78-82"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-22DOI: 10.1109/TCSII.2024.3473488
Zongxiang Wang;Jixin Chen;Debin Hou;Peigen Zhou;Zhe Chen;Long Wang;Xiaojie Xu;Wei Hong
{"title":"Erratum to “A 1–27 GHz SiGe Low Noise Amplifier With 27-dB Peak Gain and 2.85±1. 45 dB NF”","authors":"Zongxiang Wang;Jixin Chen;Debin Hou;Peigen Zhou;Zhe Chen;Long Wang;Xiaojie Xu;Wei Hong","doi":"10.1109/TCSII.2024.3473488","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3473488","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"353-353"},"PeriodicalIF":4.0,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10729228","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-22DOI: 10.1109/TCSII.2024.3484453
Chaolai Da;Fang Li;Lifang Wang;Chengxuan Tao;Shufan Li;Ming Nie
A novel pulse synchronization scheme is proposed in this brief based on simultaneous wireless power and data transfer (SWPDT) technology to address the pulse synchronization issue of the undersea bidirectional wireless power transfer (BWPT) system due to the special characteristics of the undersea environment. Accurate pulse synchronization can be implemented by adapting the software to the existing SWPDT system based on the DDQ coil. Furthermore, this brief proposes a phase lock scheme that can eliminate the issue of pulse false triggering, which is caused by the interference of the BWPT channel to the data channel. A prototype with an output power of 1 kW and a data rate of 1 Mb/s demonstrates the feasibility of the pulse synchronization scheme proposed in this brief. The work of this brief extends the application of SWPDT technology and also presents a new solution for pulse synchronization in the BWPT system.
{"title":"Pulse Synchronization Scheme for Undersea BWPT System Based on Simultaneous Wireless Power and Data Transfer Technology","authors":"Chaolai Da;Fang Li;Lifang Wang;Chengxuan Tao;Shufan Li;Ming Nie","doi":"10.1109/TCSII.2024.3484453","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3484453","url":null,"abstract":"A novel pulse synchronization scheme is proposed in this brief based on simultaneous wireless power and data transfer (SWPDT) technology to address the pulse synchronization issue of the undersea bidirectional wireless power transfer (BWPT) system due to the special characteristics of the undersea environment. Accurate pulse synchronization can be implemented by adapting the software to the existing SWPDT system based on the DDQ coil. Furthermore, this brief proposes a phase lock scheme that can eliminate the issue of pulse false triggering, which is caused by the interference of the BWPT channel to the data channel. A prototype with an output power of 1 kW and a data rate of 1 Mb/s demonstrates the feasibility of the pulse synchronization scheme proposed in this brief. The work of this brief extends the application of SWPDT technology and also presents a new solution for pulse synchronization in the BWPT system.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"333-337"},"PeriodicalIF":4.0,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A peak-valley current-mode (PVCM) Buck converter is presented to extend the duty cycle range. Compared with traditional single inductor current-controlled converters, the PVCM Buck converter employs both the peak inductor current (PIC) and the valley inductor current (VIC) to precisely regulate the output voltage. Additionally, the converter features a voltage-controlled delay circuit, to enable active adjustment of operating frequency and to extend the duty cycle range. The proposed converter is implemented using a $0.18mu $ m BCD process. Experimental results demonstrate that the prototype achieves the 3% to 95% duty cycle range with a peak efficiency of 92%.
{"title":"A Peak-Valley Current-Mode Buck Converter With 3% to 95% Duty Cycle","authors":"Zhong Zhao;Ping Luo;Zhiyuan Zhang;Jiahang Fan;Bo Zhang;Xiaowen Chen","doi":"10.1109/TCSII.2024.3484449","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3484449","url":null,"abstract":"A peak-valley current-mode (PVCM) Buck converter is presented to extend the duty cycle range. Compared with traditional single inductor current-controlled converters, the PVCM Buck converter employs both the peak inductor current (PIC) and the valley inductor current (VIC) to precisely regulate the output voltage. Additionally, the converter features a voltage-controlled delay circuit, to enable active adjustment of operating frequency and to extend the duty cycle range. The proposed converter is implemented using a \u0000<inline-formula> <tex-math>$0.18mu $ </tex-math></inline-formula>\u0000m BCD process. Experimental results demonstrate that the prototype achieves the 3% to 95% duty cycle range with a peak efficiency of 92%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"328-332"},"PeriodicalIF":4.0,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief introduces a novel adaptive optimal output-feedback controller for permanent magnet synchronous motor (PMSM) systems, eliminating the need for prior knowledge of system dynamics, numerous integral window functions, or unmeasurable states and load torque. Initially, we design an adaptive optimal output-feedback controller by constructing internal states. Then, a policy iteration algorithm based on adaptive dynamic programming approximates the optimal output-feedback gain using only input and trajectory tracking error information. Notably, this method does not require the minimal polynomial of an exosystem or the solution of regulator equations, facilitating the overall design of the feedforward-feedback controller. The effectiveness of the proposed learning algorithm is validated on a PMSM system.
{"title":"Optimal Output-Feedback Controller Design Using Adaptive Dynamic Programming: A Permanent Magnet Synchronous Motor Application","authors":"Zhongyang Wang;Huiru Ye;Youqing Wang;Yukun Shi;Li Liang","doi":"10.1109/TCSII.2024.3483909","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3483909","url":null,"abstract":"This brief introduces a novel adaptive optimal output-feedback controller for permanent magnet synchronous motor (PMSM) systems, eliminating the need for prior knowledge of system dynamics, numerous integral window functions, or unmeasurable states and load torque. Initially, we design an adaptive optimal output-feedback controller by constructing internal states. Then, a policy iteration algorithm based on adaptive dynamic programming approximates the optimal output-feedback gain using only input and trajectory tracking error information. Notably, this method does not require the minimal polynomial of an exosystem or the solution of regulator equations, facilitating the overall design of the feedforward-feedback controller. The effectiveness of the proposed learning algorithm is validated on a PMSM system.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"208-212"},"PeriodicalIF":4.0,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The number of IoT devices has grown significantly in recent years, and edge computing in IoT is considered a new and growing trend in the technology industry. While cryptography is widely used to enhance the security of IoT devices, it also carries limitations such as resource constraints or latency. Therefore, lightweight cryptography (LWC) balances commensurate resource usage and maintaining security while minimizing system costs. The ASCON stands out among the LWC algorithms as a potential target for implementation and cryptoanalysis. It provides authenticated encryption with associated data (AEAD) and hashing functionalities in many variants, aiming for various applications. In this brief, we present an implementation of Ascon cryptography as a peripheral of a RISC-V System-on-a-Chip (SoC). The ASCON crypto core occupies 1,424 LUTs in FPGA and 17.4 kGE in 180nm CMOS technology while achieving 417 Gbits/J energy efficiency at a supply voltage of 1.0V and frequency of 2 MHz.
{"title":"ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications","authors":"Khai-Duy Nguyen;Tuan-Kiet Dang;Binh Kieu-Do-Nguyen;Duc-Hung Le;Cong-Kha Pham;Trong-Thuc Hoang","doi":"10.1109/TCSII.2024.3483214","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3483214","url":null,"abstract":"The number of IoT devices has grown significantly in recent years, and edge computing in IoT is considered a new and growing trend in the technology industry. While cryptography is widely used to enhance the security of IoT devices, it also carries limitations such as resource constraints or latency. Therefore, lightweight cryptography (LWC) balances commensurate resource usage and maintaining security while minimizing system costs. The ASCON stands out among the LWC algorithms as a potential target for implementation and cryptoanalysis. It provides authenticated encryption with associated data (AEAD) and hashing functionalities in many variants, aiming for various applications. In this brief, we present an implementation of Ascon cryptography as a peripheral of a RISC-V System-on-a-Chip (SoC). The ASCON crypto core occupies 1,424 LUTs in FPGA and 17.4 kGE in 180nm CMOS technology while achieving 417 Gbits/J energy efficiency at a supply voltage of 1.0V and frequency of 2 MHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"278-282"},"PeriodicalIF":4.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-18DOI: 10.1109/TCSII.2024.3483575
Guangyu Yan;Wei Han;Chang Liu;Bowang Zhang;Meixuan Li
This brief presents a novel simultaneous wireless power and data transfer (SWPDT) system that combines inductive and capacitive couplings, featuring full-duplex communication with high data transfer rates. Specifically, the power and forward data are transferred through inductive coupling respectively by means of the DD coils and Q coils, while the backward data is transferred through capacitive coupling by means of the stray capacitances. Because of the decoupling characteristic of the DDQ coil structure and the use of two coupling types, the interferences among the power, forward data, and backward data are relatively low. By integrating the two coupling types, a comprehensive circuit model of full-duplex data transfer is established and analyzed. Finally, a 145-W prototype is actualized with 91.4% power transfer efficiency. The forward and backward data transfer rates are 150 kbps and 600 kbps, respectively, demonstrating the feasibility of the proposed system.
{"title":"A Simultaneous Wireless Power and Full-Duplex Data Transfer System Using a Mix of Inductive and Capacitive Couplings","authors":"Guangyu Yan;Wei Han;Chang Liu;Bowang Zhang;Meixuan Li","doi":"10.1109/TCSII.2024.3483575","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3483575","url":null,"abstract":"This brief presents a novel simultaneous wireless power and data transfer (SWPDT) system that combines inductive and capacitive couplings, featuring full-duplex communication with high data transfer rates. Specifically, the power and forward data are transferred through inductive coupling respectively by means of the DD coils and Q coils, while the backward data is transferred through capacitive coupling by means of the stray capacitances. Because of the decoupling characteristic of the DDQ coil structure and the use of two coupling types, the interferences among the power, forward data, and backward data are relatively low. By integrating the two coupling types, a comprehensive circuit model of full-duplex data transfer is established and analyzed. Finally, a 145-W prototype is actualized with 91.4% power transfer efficiency. The forward and backward data transfer rates are 150 kbps and 600 kbps, respectively, demonstrating the feasibility of the proposed system.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"323-327"},"PeriodicalIF":4.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a wideband continuous-rate reference-less ring-oscillator-based PAM4 CDR. Our proposed frequency-detection-gain-enhanced phase/frequency detector (GE-PFD), in which only two logic gates are added to the Alexander bang-bang phase detector, significantly speeds up the frequency acquisition process of our CDR with wide capture range by controlling an auxiliary charge pump (A-CP). This technique eliminates separate FD or extra clock phases in prior PFDs, thus saving power. Fabricated in a 40-nm CMOS process, our CDR prototype achieves 6-64-Gb/s data rate range, 19.8-Gb/s/ $mu $ s acquisition speed, and <10–12 bit error rate with a PRBS-31 input stream. The energy efficiency is 0.41-pJ/bit, in which only 0.02 pJ/bit is contributed by the extra logic gates of the FDGE-PFD and A-CP.
{"title":"A 6–64-Gb/s 0.41-pJ/Bit Reference-Less PAM4 CDR Using a Frequency-Detection-Gain-Enhanced PFD Achieving 19.8-Gb/s/μs Acquisition Speed","authors":"Liyan Feng;Tuo Li;Xiaofeng Zou;Xiaoming Xiong;Zhao Zhang","doi":"10.1109/TCSII.2024.3481436","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3481436","url":null,"abstract":"This brief presents a wideband continuous-rate reference-less ring-oscillator-based PAM4 CDR. Our proposed frequency-detection-gain-enhanced phase/frequency detector (GE-PFD), in which only two logic gates are added to the Alexander bang-bang phase detector, significantly speeds up the frequency acquisition process of our CDR with wide capture range by controlling an auxiliary charge pump (A-CP). This technique eliminates separate FD or extra clock phases in prior PFDs, thus saving power. Fabricated in a 40-nm CMOS process, our CDR prototype achieves 6-64-Gb/s data rate range, 19.8-Gb/s/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000s acquisition speed, and <10–12 bit error rate with a PRBS-31 input stream. The energy efficiency is 0.41-pJ/bit, in which only 0.02 pJ/bit is contributed by the extra logic gates of the FDGE-PFD and A-CP.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"68-72"},"PeriodicalIF":4.0,"publicationDate":"2024-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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