This brief presents a D-band active bidirectional vector-modulation phase shifter (PS) based on a phase inverter embedded variable gain amplifier (PI-VGA). A Lange coupler and self-shielded Marchand baluns are utilized for IQ signal generation and combination, achieving bidirectional low-loss impedance matching. The switchless bidirectional PI-VGA incorporates compensation networks for parasitic reduction and intrinsic gain enhancement, enabling amplitude modulation and quadrant selection. The PS supports 5-bit 360° bidirectional phase shifting over 112-145 GHz. The measured minimum insertion losses are 7.5 dB and 9.5 dB for forward and reverse operations, with RMS gain errors of 0.09 dB. The measured minimum RMS phase errors for both directions are 0.91° and 0.86°. The measured input 1-dB compression point amounts to 8 dBm and the core area of the PS is only 0.256 mm2, with an average power consumption of 81 mW under 3.3 V power supply. To the best of the authors’ knowledge, this is the first reported D-band active bidirectional PS, and the PS is suitable for terahertz time-division duplexing (TDD) phased arrays, offering a compact size and reduced insertion loss.
{"title":"A D-Band 5-bit SiGe Active Bidirectional Phase Shifter Achieving 0.09-dB RMS Gain Error and 0.86° RMS Phase Error","authors":"Lingzheng Kong;Jixin Chen;Peigen Zhou;Zhihua Wang;Chang Shu;Dawei Tang;Rui Zhou;Jirui Li;Qianqi Meng;Pinpin Yan;Wei Hong","doi":"10.1109/TCSII.2025.3614490","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3614490","url":null,"abstract":"This brief presents a D-band active bidirectional vector-modulation phase shifter (PS) based on a phase inverter embedded variable gain amplifier (PI-VGA). A Lange coupler and self-shielded Marchand baluns are utilized for IQ signal generation and combination, achieving bidirectional low-loss impedance matching. The switchless bidirectional PI-VGA incorporates compensation networks for parasitic reduction and intrinsic gain enhancement, enabling amplitude modulation and quadrant selection. The PS supports 5-bit 360° bidirectional phase shifting over 112-145 GHz. The measured minimum insertion losses are 7.5 dB and 9.5 dB for forward and reverse operations, with RMS gain errors of 0.09 dB. The measured minimum RMS phase errors for both directions are 0.91° and 0.86°. The measured input 1-dB compression point amounts to 8 dBm and the core area of the PS is only 0.256 mm<sup>2</sup>, with an average power consumption of 81 mW under 3.3 V power supply. To the best of the authors’ knowledge, this is the first reported D-band active bidirectional PS, and the PS is suitable for terahertz time-division duplexing (TDD) phased arrays, offering a compact size and reduced insertion loss.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1725-1729"},"PeriodicalIF":4.9,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-25DOI: 10.1109/TCSII.2025.3607550
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3607550","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3607550","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11180174","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145134916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-25DOI: 10.1109/TCSII.2025.3607552
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3607552","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3607552","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11180173","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-24DOI: 10.1109/TCSII.2025.3613399
Tong Li;Honglan Jiang;Zhou Wang;Qin Wang;Jianfei Jiang;Zhigang Mao
This brief presents novel optimizations of the extraction and packing modules in posit arithmetic units. In the extraction module, a customized leading zero/one anticipator (LZA/LOA) is integrated with the incrementer to parallelize the 2’s complement operation and leading zero/one detection, which in turn reduces the critical path delay. The packing module is streamlined by merging two operations into a single incrementer step, leading to more compact hardware. To further improve the power efficiency, the output signals of the extraction module are synchronized using latches, effectively suppressing glitch propagation. Based on the proposed extraction and packing modules, 8-bit and 16-bit posit multipliers are implemented in TSMC 45 nm technology. Post-layout results show that the proposed posit multipliers achieve up to 46.14%–52.18% reduction in power–delay product (PDP) compared with state-of-the-art designs.
{"title":"Efficient Extraction and Packing Modules for Posit Multipliers","authors":"Tong Li;Honglan Jiang;Zhou Wang;Qin Wang;Jianfei Jiang;Zhigang Mao","doi":"10.1109/TCSII.2025.3613399","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3613399","url":null,"abstract":"This brief presents novel optimizations of the extraction and packing modules in posit arithmetic units. In the extraction module, a customized leading zero/one anticipator (LZA/LOA) is integrated with the incrementer to parallelize the 2’s complement operation and leading zero/one detection, which in turn reduces the critical path delay. The packing module is streamlined by merging two operations into a single incrementer step, leading to more compact hardware. To further improve the power efficiency, the output signals of the extraction module are synchronized using latches, effectively suppressing glitch propagation. Based on the proposed extraction and packing modules, 8-bit and 16-bit posit multipliers are implemented in TSMC 45 nm technology. Post-layout results show that the proposed posit multipliers achieve up to 46.14%–52.18% reduction in power–delay product (PDP) compared with state-of-the-art designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1765-1769"},"PeriodicalIF":4.9,"publicationDate":"2025-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-22DOI: 10.1109/TCSII.2025.3613137
Hyunjun Park;Minsu Kim;Woojoong Jung;Junho Song;Sung-Min Yoo;Jun-Hyeok Yang;Michael Choi;Jongshin Shin;Hyung-Min Lee
This brief presents a supply voltage ($V_{mathbf {IN}}$ ) dynamic split to overcome practical limitations of multi-level (ML) buck converters. The ML buck converters using flying capacitors ($C_{mathbf {F}}$ ) suffer from both $C_{mathbf {F}}$ voltage ($V_{mathbf {CF}}$ ) imbalance and random switching at near dead-zone conversion ratio (CR $= V_{mathbf {OUT}}$ /$V_{mathbf {IN}}$ ). The proposed 3-level buck converter with input capacitor ($C_{mathbf {IN}}$ ) dynamic reuse adopts $V_{mathbf {IN}}$ half-split balancing (VHSB) for loop-free rapid $V_{mathbf {CF}}$ balancing. In addition, $V_{mathbf {IN}}$ quarter-split transition (VQST) is applied to prevent irregular output voltage ($V_{mathbf {OUT}}$ ) ripples and acoustic noise due to random switching at near dead-zone CR. Fabricated in 28nm, the chip provides high $I_{mathbf {LOAD}}$ of 1.2A for $V_{mathbf {IN}}$ up to 3.6V using only 1.8V low-voltage transistors. Moreover, the converter achieves an excellent peak efficiency of 95.2%.
{"title":"A Reconfigurable 3-Level Buck Converter With Supply Voltage Dynamic Split for Loop-Free Rapid VCF-Balancing and Dead-Zone Seamless Transition","authors":"Hyunjun Park;Minsu Kim;Woojoong Jung;Junho Song;Sung-Min Yoo;Jun-Hyeok Yang;Michael Choi;Jongshin Shin;Hyung-Min Lee","doi":"10.1109/TCSII.2025.3613137","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3613137","url":null,"abstract":"This brief presents a supply voltage (<inline-formula> <tex-math>$V_{mathbf {IN}}$ </tex-math></inline-formula>) dynamic split to overcome practical limitations of multi-level (ML) buck converters. The ML buck converters using flying capacitors (<inline-formula> <tex-math>$C_{mathbf {F}}$ </tex-math></inline-formula>) suffer from both <inline-formula> <tex-math>$C_{mathbf {F}}$ </tex-math></inline-formula> voltage (<inline-formula> <tex-math>$V_{mathbf {CF}}$ </tex-math></inline-formula>) imbalance and random switching at near dead-zone conversion ratio (CR <inline-formula> <tex-math>$= V_{mathbf {OUT}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$V_{mathbf {IN}}$ </tex-math></inline-formula>). The proposed 3-level buck converter with input capacitor (<inline-formula> <tex-math>$C_{mathbf {IN}}$ </tex-math></inline-formula>) dynamic reuse adopts <inline-formula> <tex-math>$V_{mathbf {IN}}$ </tex-math></inline-formula> half-split balancing (VHSB) for loop-free rapid <inline-formula> <tex-math>$V_{mathbf {CF}}$ </tex-math></inline-formula> balancing. In addition, <inline-formula> <tex-math>$V_{mathbf {IN}}$ </tex-math></inline-formula> quarter-split transition (VQST) is applied to prevent irregular output voltage (<inline-formula> <tex-math>$V_{mathbf {OUT}}$ </tex-math></inline-formula>) ripples and acoustic noise due to random switching at near dead-zone CR. Fabricated in 28nm, the chip provides high <inline-formula> <tex-math>$I_{mathbf {LOAD}}$ </tex-math></inline-formula> of 1.2A for <inline-formula> <tex-math>$V_{mathbf {IN}}$ </tex-math></inline-formula> up to 3.6V using only 1.8V low-voltage transistors. Moreover, the converter achieves an excellent peak efficiency of 95.2%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1805-1809"},"PeriodicalIF":4.9,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-22DOI: 10.1109/TCSII.2025.3612703
Wenjie Li;Yongting Deng;Jia Fu;Haiyang Cao;Yuxin Kang;Chuanlong Zhai;Xiufeng Liu;Gaolin Wang
To enhance the position estimation accuracy of permanent magnet synchronous motor (PMSM) speed-sensorless control, a simplified hybrid adaptive kalman filter (SHAKF) with fading-triggered resonance (FTR) is proposed in this brief. By simplifying the iterative calculation of forgetting factor and noise covariance matrix, the computational burden is effectively reduced. Through the FTR mechanism, the steady-state error compensation without compromising stability is achieved. The stability and convergence are rigorously analyzed. Finally, the experimental results validate the superiority of the proposed sensorless control strategy in steady-state accuracy, dynamic speed response, and computational efficiency.
{"title":"Simplified Hybrid Adaptive Kalman Filter With Fading-Triggered Resonance Mechanism for PMSM Speed-Sensorless Control","authors":"Wenjie Li;Yongting Deng;Jia Fu;Haiyang Cao;Yuxin Kang;Chuanlong Zhai;Xiufeng Liu;Gaolin Wang","doi":"10.1109/TCSII.2025.3612703","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3612703","url":null,"abstract":"To enhance the position estimation accuracy of permanent magnet synchronous motor (PMSM) speed-sensorless control, a simplified hybrid adaptive kalman filter (SHAKF) with fading-triggered resonance (FTR) is proposed in this brief. By simplifying the iterative calculation of forgetting factor and noise covariance matrix, the computational burden is effectively reduced. Through the FTR mechanism, the steady-state error compensation without compromising stability is achieved. The stability and convergence are rigorously analyzed. Finally, the experimental results validate the superiority of the proposed sensorless control strategy in steady-state accuracy, dynamic speed response, and computational efficiency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1740-1744"},"PeriodicalIF":4.9,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Voxel-based point cloud neural networks have gained significant attention for 3D semantic segmentation due to their effectiveness in processing point clouds. However, the high computational overhead of processing large-scale point clouds and the inherent irregularity of these point clouds hinder the fast and energy-efficient acceleration of segmentation. This brief presents a 3D semantic segmentation accelerator with an offset-wise weight quantization technique that drastically reduces computational complexity. The proposed design introduces a unified voxel search unit that efficiently processes various types of operations needed to capture spatial relationships among irregularly stored voxels. In addition, a dual-mode computing engine combined with a novel workload allocation technique enables highly parallel processing and maximizes processing core utilization. Fabricated in a 28-nm CMOS technology, the proposed processor achieves 10.24 TOPS/W energy efficiency, outperforming prior art.
{"title":"An Energy-Efficient 3D Semantic Segmentation Processor With Offset-Wise Weight Quantization","authors":"Beomseok Kim;Sunwoo Lee;Byeungseok Yoo;Dongsuk Jeon","doi":"10.1109/TCSII.2025.3611960","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3611960","url":null,"abstract":"Voxel-based point cloud neural networks have gained significant attention for 3D semantic segmentation due to their effectiveness in processing point clouds. However, the high computational overhead of processing large-scale point clouds and the inherent irregularity of these point clouds hinder the fast and energy-efficient acceleration of segmentation. This brief presents a 3D semantic segmentation accelerator with an offset-wise weight quantization technique that drastically reduces computational complexity. The proposed design introduces a unified voxel search unit that efficiently processes various types of operations needed to capture spatial relationships among irregularly stored voxels. In addition, a dual-mode computing engine combined with a novel workload allocation technique enables highly parallel processing and maximizes processing core utilization. Fabricated in a 28-nm CMOS technology, the proposed processor achieves 10.24 TOPS/W energy efficiency, outperforming prior art.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1760-1764"},"PeriodicalIF":4.9,"publicationDate":"2025-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11173709","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-17DOI: 10.1109/TCSII.2025.3611107
Fanny Spagnolo;Pasquale Corsonello;Stefania Perri
Polymorphic gates are logic hardware components designed to have reconfigurable functionalities and perform context-dependent operations. These gates were often implemented using emerging technologies with intrinsic properties that can be exploited to alter the logical operation, such as Reconfigurable Field-Effect Transistors (RFETs). However, the majority of the proposed topologies still remain rooted in conventional design paradigms, thus only partially exploiting the benefits of such advanced devices. In this Brief, we present a universal polymorphic topology purposely conceived for RFETs that can be configured to implement any combination of 2-input logic functions and their inversions, by simply acting on external configuration signals. When realized using a 14nm process technology, the proposed gate, configured as NAND-XNOR-XOR-AND, shows a delay of 19ps and dissipates ~1.8fJ, which is nearly the same as that required by a simple XNOR gate realized using RFETs. At the parity of logic functionality, the proposed scheme leads to a reduction in delay and energy dissipation of up to 64% and 57.9%, respectively, compared to conventional approaches.
{"title":"Design of Energy Efficient RFET-Based Polymorphic Logic Gates","authors":"Fanny Spagnolo;Pasquale Corsonello;Stefania Perri","doi":"10.1109/TCSII.2025.3611107","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3611107","url":null,"abstract":"Polymorphic gates are logic hardware components designed to have reconfigurable functionalities and perform context-dependent operations. These gates were often implemented using emerging technologies with intrinsic properties that can be exploited to alter the logical operation, such as Reconfigurable Field-Effect Transistors (RFETs). However, the majority of the proposed topologies still remain rooted in conventional design paradigms, thus only partially exploiting the benefits of such advanced devices. In this Brief, we present a universal polymorphic topology purposely conceived for RFETs that can be configured to implement any combination of 2-input logic functions and their inversions, by simply acting on external configuration signals. When realized using a 14nm process technology, the proposed gate, configured as NAND-XNOR-XOR-AND, shows a delay of 19ps and dissipates ~1.8fJ, which is nearly the same as that required by a simple XNOR gate realized using RFETs. At the parity of logic functionality, the proposed scheme leads to a reduction in delay and energy dissipation of up to 64% and 57.9%, respectively, compared to conventional approaches.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1755-1759"},"PeriodicalIF":4.9,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11168833","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-17DOI: 10.1109/TCSII.2025.3610891
Yeu-Torng Yau
This brief presents a compact, single-stage hybrid power filter for AC/DC or DC/DC converters that simultaneously suppresses DM and CM noise currents through a passive current cancellation method. By integrating both DM and CM filtering functions into a single filter topology, the proposed design reduces the number of magnetic windings and simplifies construction compared to conventional multi-stage filters. Composed entirely of passive components, it avoids the complexity that active circuits usually entail, offering a reliable and efficient solution for industrial applications.
{"title":"Hybrid Power Filter for Differential-Mode and Common-Mode Noise Currents","authors":"Yeu-Torng Yau","doi":"10.1109/TCSII.2025.3610891","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3610891","url":null,"abstract":"This brief presents a compact, single-stage hybrid power filter for AC/DC or DC/DC converters that simultaneously suppresses DM and CM noise currents through a passive current cancellation method. By integrating both DM and CM filtering functions into a single filter topology, the proposed design reduces the number of magnetic windings and simplifies construction compared to conventional multi-stage filters. Composed entirely of passive components, it avoids the complexity that active circuits usually entail, offering a reliable and efficient solution for industrial applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1800-1804"},"PeriodicalIF":4.9,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-10DOI: 10.1109/TCSII.2025.3608185
Wei Yu;Yunfei Zheng;Shiyuan Wang
The nonlinear and time-varying characteristics of internal electronic circuits in battery systems pose challenges to the practical application of traditional state-of-charge (SOC) estimation methods. To address these challenges, we first propose a novel variational inference neural network (VINN), which combines deep neural networks with variational inference to enable accurate SOC estimation solely based on measured current, voltage, and temperature. Specifically, the proposed VINN employs an encoder to infer a latent SOC distribution from measurement inputs, and a decoder is used to reconstruct the inputs for computing the evidence lower bound (ELBO), which guides the network optimization. Meanwhile, a physics-informed loss is introduced by using Coulomb counting to derive the prior of SOC, ensuring consistency with the battery’s circuit behavior. Finally, experiments on realistic Panasonic 18650PF dataset demonstrate that VINN achieves superior estimation accuracy and generalization performance under both supervised and unsupervised settings compared to state-of-the-art methods.
{"title":"Data-Driven State-of-Charge Estimation for Lithium-Ion Batteries Using Variational Inference","authors":"Wei Yu;Yunfei Zheng;Shiyuan Wang","doi":"10.1109/TCSII.2025.3608185","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3608185","url":null,"abstract":"The nonlinear and time-varying characteristics of internal electronic circuits in battery systems pose challenges to the practical application of traditional state-of-charge (SOC) estimation methods. To address these challenges, we first propose a novel variational inference neural network (VINN), which combines deep neural networks with variational inference to enable accurate SOC estimation solely based on measured current, voltage, and temperature. Specifically, the proposed VINN employs an encoder to infer a latent SOC distribution from measurement inputs, and a decoder is used to reconstruct the inputs for computing the evidence lower bound (ELBO), which guides the network optimization. Meanwhile, a physics-informed loss is introduced by using Coulomb counting to derive the prior of SOC, ensuring consistency with the battery’s circuit behavior. Finally, experiments on realistic Panasonic 18650PF dataset demonstrate that VINN achieves superior estimation accuracy and generalization performance under both supervised and unsupervised settings compared to state-of-the-art methods.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1810-1814"},"PeriodicalIF":4.9,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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