Pub Date : 2025-09-29DOI: 10.1109/TCSII.2025.3615737
L. Hemanth Krishna;B. Srinivasu;K. Sridharan
Arithmetic units in multivalued logic have been extensively researched in the last decade in the context of emerging nanodevices. While considerable work has been done on adder and multiplier designs, the focus has been on handling unsigned numbers. In this brief, we first present an algorithm for multiplication of a pair of signed ternary numbers represented in three’s complement format. The algorithm leads to partial product digits which are all positive. Using a special class of operators in ternary logic, we then present a hardware-efficient realization of the algorithm that leads to low multiplexer count. The special operators also contribute to power reduction. Technology assessment using Carbon Nanotube FET (CNTFET) reveals that the proposed multiplier achieves substantial reduction in power-delay product (PDP) over the best existing design. In particular, the savings in PDP for $6times 6$ and $36times 36$ multipliers are 32% and 38% respectively.
{"title":"Low Complexity Three’s Complement Parallel Multiplier Using Special Operators of Ternary Logic","authors":"L. Hemanth Krishna;B. Srinivasu;K. Sridharan","doi":"10.1109/TCSII.2025.3615737","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3615737","url":null,"abstract":"Arithmetic units in multivalued logic have been extensively researched in the last decade in the context of emerging nanodevices. While considerable work has been done on adder and multiplier designs, the focus has been on handling unsigned numbers. In this brief, we first present an algorithm for multiplication of a pair of <italic>signed ternary numbers represented in three’s complement format</i>. The algorithm leads to partial product digits which are all positive. Using a special class of operators in ternary logic, we then present a hardware-efficient realization of the algorithm that leads to low multiplexer count. The special operators also contribute to power reduction. Technology assessment using Carbon Nanotube FET (CNTFET) reveals that the proposed multiplier achieves substantial reduction in power-delay product (PDP) over the best existing design. In particular, the savings in PDP for <inline-formula> <tex-math>$6times 6$ </tex-math></inline-formula> and <inline-formula> <tex-math>$36times 36$ </tex-math></inline-formula> multipliers are 32% and 38% respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1775-1779"},"PeriodicalIF":4.9,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-26DOI: 10.1109/TCSII.2025.3614711
Yalin Zhang;Zhongxin Liu;Zengqiang Chen
Secondary control and the State-of-Charge (SoC) balance control are important control objectives for battery energy storage systems (BESSs). In this brief, a communication weight allocation method based on the centrality of eigenvectors is designed for a connected and directed graph, which results in the adjacency matrix having a given leading eigenvector. Subsequently, a distributed secondary voltage controller and an SoC balance controller are designed for droop-controlled BESSs to achieve voltage leader-following multiconsensus and SoC balance, respectively. It is worth mentioning that under the designed voltage secondary control scheme, only a single leader is needed to achieve voltage multiconsensus control. In addition, the capacity information/droop coefficient does not need to be transmitted in the communication network to achieve power sharing according to capacity and SoC balance. For SoC balance control, the control gain is also well analyzed to ensure stability. The relevant simulations verify the effectiveness of the designed scheme.
{"title":"Distributed Multiconsensus Cooperative Control of Droop-Controlled BESSs Based on Centrality of Eigenvectors","authors":"Yalin Zhang;Zhongxin Liu;Zengqiang Chen","doi":"10.1109/TCSII.2025.3614711","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3614711","url":null,"abstract":"Secondary control and the State-of-Charge (SoC) balance control are important control objectives for battery energy storage systems (BESSs). In this brief, a communication weight allocation method based on the centrality of eigenvectors is designed for a connected and directed graph, which results in the adjacency matrix having a given leading eigenvector. Subsequently, a distributed secondary voltage controller and an SoC balance controller are designed for droop-controlled BESSs to achieve voltage leader-following multiconsensus and SoC balance, respectively. It is worth mentioning that under the designed voltage secondary control scheme, only a single leader is needed to achieve voltage multiconsensus control. In addition, the capacity information/droop coefficient does not need to be transmitted in the communication network to achieve power sharing according to capacity and SoC balance. For SoC balance control, the control gain is also well analyzed to ensure stability. The relevant simulations verify the effectiveness of the designed scheme.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1745-1749"},"PeriodicalIF":4.9,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a D-band active bidirectional vector-modulation phase shifter (PS) based on a phase inverter embedded variable gain amplifier (PI-VGA). A Lange coupler and self-shielded Marchand baluns are utilized for IQ signal generation and combination, achieving bidirectional low-loss impedance matching. The switchless bidirectional PI-VGA incorporates compensation networks for parasitic reduction and intrinsic gain enhancement, enabling amplitude modulation and quadrant selection. The PS supports 5-bit 360° bidirectional phase shifting over 112-145 GHz. The measured minimum insertion losses are 7.5 dB and 9.5 dB for forward and reverse operations, with RMS gain errors of 0.09 dB. The measured minimum RMS phase errors for both directions are 0.91° and 0.86°. The measured input 1-dB compression point amounts to 8 dBm and the core area of the PS is only 0.256 mm2, with an average power consumption of 81 mW under 3.3 V power supply. To the best of the authors’ knowledge, this is the first reported D-band active bidirectional PS, and the PS is suitable for terahertz time-division duplexing (TDD) phased arrays, offering a compact size and reduced insertion loss.
{"title":"A D-Band 5-bit SiGe Active Bidirectional Phase Shifter Achieving 0.09-dB RMS Gain Error and 0.86° RMS Phase Error","authors":"Lingzheng Kong;Jixin Chen;Peigen Zhou;Zhihua Wang;Chang Shu;Dawei Tang;Rui Zhou;Jirui Li;Qianqi Meng;Pinpin Yan;Wei Hong","doi":"10.1109/TCSII.2025.3614490","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3614490","url":null,"abstract":"This brief presents a D-band active bidirectional vector-modulation phase shifter (PS) based on a phase inverter embedded variable gain amplifier (PI-VGA). A Lange coupler and self-shielded Marchand baluns are utilized for IQ signal generation and combination, achieving bidirectional low-loss impedance matching. The switchless bidirectional PI-VGA incorporates compensation networks for parasitic reduction and intrinsic gain enhancement, enabling amplitude modulation and quadrant selection. The PS supports 5-bit 360° bidirectional phase shifting over 112-145 GHz. The measured minimum insertion losses are 7.5 dB and 9.5 dB for forward and reverse operations, with RMS gain errors of 0.09 dB. The measured minimum RMS phase errors for both directions are 0.91° and 0.86°. The measured input 1-dB compression point amounts to 8 dBm and the core area of the PS is only 0.256 mm<sup>2</sup>, with an average power consumption of 81 mW under 3.3 V power supply. To the best of the authors’ knowledge, this is the first reported D-band active bidirectional PS, and the PS is suitable for terahertz time-division duplexing (TDD) phased arrays, offering a compact size and reduced insertion loss.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1725-1729"},"PeriodicalIF":4.9,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-25DOI: 10.1109/TCSII.2025.3607550
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3607550","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3607550","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11180174","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145134916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-25DOI: 10.1109/TCSII.2025.3607552
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3607552","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3607552","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11180173","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-24DOI: 10.1109/TCSII.2025.3613399
Tong Li;Honglan Jiang;Zhou Wang;Qin Wang;Jianfei Jiang;Zhigang Mao
This brief presents novel optimizations of the extraction and packing modules in posit arithmetic units. In the extraction module, a customized leading zero/one anticipator (LZA/LOA) is integrated with the incrementer to parallelize the 2’s complement operation and leading zero/one detection, which in turn reduces the critical path delay. The packing module is streamlined by merging two operations into a single incrementer step, leading to more compact hardware. To further improve the power efficiency, the output signals of the extraction module are synchronized using latches, effectively suppressing glitch propagation. Based on the proposed extraction and packing modules, 8-bit and 16-bit posit multipliers are implemented in TSMC 45 nm technology. Post-layout results show that the proposed posit multipliers achieve up to 46.14%–52.18% reduction in power–delay product (PDP) compared with state-of-the-art designs.
{"title":"Efficient Extraction and Packing Modules for Posit Multipliers","authors":"Tong Li;Honglan Jiang;Zhou Wang;Qin Wang;Jianfei Jiang;Zhigang Mao","doi":"10.1109/TCSII.2025.3613399","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3613399","url":null,"abstract":"This brief presents novel optimizations of the extraction and packing modules in posit arithmetic units. In the extraction module, a customized leading zero/one anticipator (LZA/LOA) is integrated with the incrementer to parallelize the 2’s complement operation and leading zero/one detection, which in turn reduces the critical path delay. The packing module is streamlined by merging two operations into a single incrementer step, leading to more compact hardware. To further improve the power efficiency, the output signals of the extraction module are synchronized using latches, effectively suppressing glitch propagation. Based on the proposed extraction and packing modules, 8-bit and 16-bit posit multipliers are implemented in TSMC 45 nm technology. Post-layout results show that the proposed posit multipliers achieve up to 46.14%–52.18% reduction in power–delay product (PDP) compared with state-of-the-art designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1765-1769"},"PeriodicalIF":4.9,"publicationDate":"2025-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-22DOI: 10.1109/TCSII.2025.3613137
Hyunjun Park;Minsu Kim;Woojoong Jung;Junho Song;Sung-Min Yoo;Jun-Hyeok Yang;Michael Choi;Jongshin Shin;Hyung-Min Lee
This brief presents a supply voltage ($V_{mathbf {IN}}$ ) dynamic split to overcome practical limitations of multi-level (ML) buck converters. The ML buck converters using flying capacitors ($C_{mathbf {F}}$ ) suffer from both $C_{mathbf {F}}$ voltage ($V_{mathbf {CF}}$ ) imbalance and random switching at near dead-zone conversion ratio (CR $= V_{mathbf {OUT}}$ /$V_{mathbf {IN}}$ ). The proposed 3-level buck converter with input capacitor ($C_{mathbf {IN}}$ ) dynamic reuse adopts $V_{mathbf {IN}}$ half-split balancing (VHSB) for loop-free rapid $V_{mathbf {CF}}$ balancing. In addition, $V_{mathbf {IN}}$ quarter-split transition (VQST) is applied to prevent irregular output voltage ($V_{mathbf {OUT}}$ ) ripples and acoustic noise due to random switching at near dead-zone CR. Fabricated in 28nm, the chip provides high $I_{mathbf {LOAD}}$ of 1.2A for $V_{mathbf {IN}}$ up to 3.6V using only 1.8V low-voltage transistors. Moreover, the converter achieves an excellent peak efficiency of 95.2%.
{"title":"A Reconfigurable 3-Level Buck Converter With Supply Voltage Dynamic Split for Loop-Free Rapid VCF-Balancing and Dead-Zone Seamless Transition","authors":"Hyunjun Park;Minsu Kim;Woojoong Jung;Junho Song;Sung-Min Yoo;Jun-Hyeok Yang;Michael Choi;Jongshin Shin;Hyung-Min Lee","doi":"10.1109/TCSII.2025.3613137","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3613137","url":null,"abstract":"This brief presents a supply voltage (<inline-formula> <tex-math>$V_{mathbf {IN}}$ </tex-math></inline-formula>) dynamic split to overcome practical limitations of multi-level (ML) buck converters. The ML buck converters using flying capacitors (<inline-formula> <tex-math>$C_{mathbf {F}}$ </tex-math></inline-formula>) suffer from both <inline-formula> <tex-math>$C_{mathbf {F}}$ </tex-math></inline-formula> voltage (<inline-formula> <tex-math>$V_{mathbf {CF}}$ </tex-math></inline-formula>) imbalance and random switching at near dead-zone conversion ratio (CR <inline-formula> <tex-math>$= V_{mathbf {OUT}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$V_{mathbf {IN}}$ </tex-math></inline-formula>). The proposed 3-level buck converter with input capacitor (<inline-formula> <tex-math>$C_{mathbf {IN}}$ </tex-math></inline-formula>) dynamic reuse adopts <inline-formula> <tex-math>$V_{mathbf {IN}}$ </tex-math></inline-formula> half-split balancing (VHSB) for loop-free rapid <inline-formula> <tex-math>$V_{mathbf {CF}}$ </tex-math></inline-formula> balancing. In addition, <inline-formula> <tex-math>$V_{mathbf {IN}}$ </tex-math></inline-formula> quarter-split transition (VQST) is applied to prevent irregular output voltage (<inline-formula> <tex-math>$V_{mathbf {OUT}}$ </tex-math></inline-formula>) ripples and acoustic noise due to random switching at near dead-zone CR. Fabricated in 28nm, the chip provides high <inline-formula> <tex-math>$I_{mathbf {LOAD}}$ </tex-math></inline-formula> of 1.2A for <inline-formula> <tex-math>$V_{mathbf {IN}}$ </tex-math></inline-formula> up to 3.6V using only 1.8V low-voltage transistors. Moreover, the converter achieves an excellent peak efficiency of 95.2%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1805-1809"},"PeriodicalIF":4.9,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-22DOI: 10.1109/TCSII.2025.3612703
Wenjie Li;Yongting Deng;Jia Fu;Haiyang Cao;Yuxin Kang;Chuanlong Zhai;Xiufeng Liu;Gaolin Wang
To enhance the position estimation accuracy of permanent magnet synchronous motor (PMSM) speed-sensorless control, a simplified hybrid adaptive kalman filter (SHAKF) with fading-triggered resonance (FTR) is proposed in this brief. By simplifying the iterative calculation of forgetting factor and noise covariance matrix, the computational burden is effectively reduced. Through the FTR mechanism, the steady-state error compensation without compromising stability is achieved. The stability and convergence are rigorously analyzed. Finally, the experimental results validate the superiority of the proposed sensorless control strategy in steady-state accuracy, dynamic speed response, and computational efficiency.
{"title":"Simplified Hybrid Adaptive Kalman Filter With Fading-Triggered Resonance Mechanism for PMSM Speed-Sensorless Control","authors":"Wenjie Li;Yongting Deng;Jia Fu;Haiyang Cao;Yuxin Kang;Chuanlong Zhai;Xiufeng Liu;Gaolin Wang","doi":"10.1109/TCSII.2025.3612703","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3612703","url":null,"abstract":"To enhance the position estimation accuracy of permanent magnet synchronous motor (PMSM) speed-sensorless control, a simplified hybrid adaptive kalman filter (SHAKF) with fading-triggered resonance (FTR) is proposed in this brief. By simplifying the iterative calculation of forgetting factor and noise covariance matrix, the computational burden is effectively reduced. Through the FTR mechanism, the steady-state error compensation without compromising stability is achieved. The stability and convergence are rigorously analyzed. Finally, the experimental results validate the superiority of the proposed sensorless control strategy in steady-state accuracy, dynamic speed response, and computational efficiency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1740-1744"},"PeriodicalIF":4.9,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Voxel-based point cloud neural networks have gained significant attention for 3D semantic segmentation due to their effectiveness in processing point clouds. However, the high computational overhead of processing large-scale point clouds and the inherent irregularity of these point clouds hinder the fast and energy-efficient acceleration of segmentation. This brief presents a 3D semantic segmentation accelerator with an offset-wise weight quantization technique that drastically reduces computational complexity. The proposed design introduces a unified voxel search unit that efficiently processes various types of operations needed to capture spatial relationships among irregularly stored voxels. In addition, a dual-mode computing engine combined with a novel workload allocation technique enables highly parallel processing and maximizes processing core utilization. Fabricated in a 28-nm CMOS technology, the proposed processor achieves 10.24 TOPS/W energy efficiency, outperforming prior art.
{"title":"An Energy-Efficient 3D Semantic Segmentation Processor With Offset-Wise Weight Quantization","authors":"Beomseok Kim;Sunwoo Lee;Byeungseok Yoo;Dongsuk Jeon","doi":"10.1109/TCSII.2025.3611960","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3611960","url":null,"abstract":"Voxel-based point cloud neural networks have gained significant attention for 3D semantic segmentation due to their effectiveness in processing point clouds. However, the high computational overhead of processing large-scale point clouds and the inherent irregularity of these point clouds hinder the fast and energy-efficient acceleration of segmentation. This brief presents a 3D semantic segmentation accelerator with an offset-wise weight quantization technique that drastically reduces computational complexity. The proposed design introduces a unified voxel search unit that efficiently processes various types of operations needed to capture spatial relationships among irregularly stored voxels. In addition, a dual-mode computing engine combined with a novel workload allocation technique enables highly parallel processing and maximizes processing core utilization. Fabricated in a 28-nm CMOS technology, the proposed processor achieves 10.24 TOPS/W energy efficiency, outperforming prior art.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1760-1764"},"PeriodicalIF":4.9,"publicationDate":"2025-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11173709","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-17DOI: 10.1109/TCSII.2025.3611107
Fanny Spagnolo;Pasquale Corsonello;Stefania Perri
Polymorphic gates are logic hardware components designed to have reconfigurable functionalities and perform context-dependent operations. These gates were often implemented using emerging technologies with intrinsic properties that can be exploited to alter the logical operation, such as Reconfigurable Field-Effect Transistors (RFETs). However, the majority of the proposed topologies still remain rooted in conventional design paradigms, thus only partially exploiting the benefits of such advanced devices. In this Brief, we present a universal polymorphic topology purposely conceived for RFETs that can be configured to implement any combination of 2-input logic functions and their inversions, by simply acting on external configuration signals. When realized using a 14nm process technology, the proposed gate, configured as NAND-XNOR-XOR-AND, shows a delay of 19ps and dissipates ~1.8fJ, which is nearly the same as that required by a simple XNOR gate realized using RFETs. At the parity of logic functionality, the proposed scheme leads to a reduction in delay and energy dissipation of up to 64% and 57.9%, respectively, compared to conventional approaches.
{"title":"Design of Energy Efficient RFET-Based Polymorphic Logic Gates","authors":"Fanny Spagnolo;Pasquale Corsonello;Stefania Perri","doi":"10.1109/TCSII.2025.3611107","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3611107","url":null,"abstract":"Polymorphic gates are logic hardware components designed to have reconfigurable functionalities and perform context-dependent operations. These gates were often implemented using emerging technologies with intrinsic properties that can be exploited to alter the logical operation, such as Reconfigurable Field-Effect Transistors (RFETs). However, the majority of the proposed topologies still remain rooted in conventional design paradigms, thus only partially exploiting the benefits of such advanced devices. In this Brief, we present a universal polymorphic topology purposely conceived for RFETs that can be configured to implement any combination of 2-input logic functions and their inversions, by simply acting on external configuration signals. When realized using a 14nm process technology, the proposed gate, configured as NAND-XNOR-XOR-AND, shows a delay of 19ps and dissipates ~1.8fJ, which is nearly the same as that required by a simple XNOR gate realized using RFETs. At the parity of logic functionality, the proposed scheme leads to a reduction in delay and energy dissipation of up to 64% and 57.9%, respectively, compared to conventional approaches.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1755-1759"},"PeriodicalIF":4.9,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11168833","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145456011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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