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IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

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Dissipativity-Based Bumpless Transfer Control for Switched Positive Systems 基于差分性的开关正向系统无缓冲传输控制
IF 4.4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
IEEE Transactions on Circuits and Systems II: Express Briefs
Pub Date : 2024-08-13 DOI: 10.1109/tcsii.2024.3442864
Ying Zhao, Zhe Feng, Peng Wang
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引用次数: 0
An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery 具有可配置开关网络的 N/PBTI 隔离式 BTI 监视器以及针对内存外围工艺变化的校准功能
IF 4.4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
IEEE Transactions on Circuits and Systems II: Express Briefs
Pub Date : 2024-08-12 DOI: 10.1109/tcsii.2024.3442215
Shin-Hyun Jeong, Yong-Un Jeong, Suhwan Kim
{"title":"An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery","authors":"Shin-Hyun Jeong, Yong-Un Jeong, Suhwan Kim","doi":"10.1109/tcsii.2024.3442215","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3442215","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":null,"pages":null},"PeriodicalIF":4.4,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3×12-Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS 采用串音消除技术的 28 纳米 CMOS 3×12-Gb/s 1.26-pJ/b 单端 PAM-3 发射器
IF 4.4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
IEEE Transactions on Circuits and Systems II: Express Briefs
Pub Date : 2024-08-12 DOI: 10.1109/tcsii.2024.3442200
Dongwoo Kang, Han-Gon Ko, Kwanseo Park
{"title":"A 3×12-Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS","authors":"Dongwoo Kang, Han-Gon Ko, Kwanseo Park","doi":"10.1109/tcsii.2024.3442200","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3442200","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":null,"pages":null},"PeriodicalIF":4.4,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Configurable ML-KEM/Kyber Key-Encapsulation Hardware Accelerator Architecture 可配置的 ML-KEM/Kyber 密钥封装硬件加速器架构
IF 4.4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
IEEE Transactions on Circuits and Systems II: Express Briefs
Pub Date : 2024-08-12 DOI: 10.1109/tcsii.2024.3442228
Hyunseon Kim, Haesung Jung, Ardianto Satriawan, Hanho Lee
{"title":"A Configurable ML-KEM/Kyber Key-Encapsulation Hardware Accelerator Architecture","authors":"Hyunseon Kim, Haesung Jung, Ardianto Satriawan, Hanho Lee","doi":"10.1109/tcsii.2024.3442228","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3442228","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":null,"pages":null},"PeriodicalIF":4.4,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance of Leader-Follower Coherence for Selecting Leaders Using Node Centrality Indices 使用节点中心性指数选择领导者时领导者与追随者一致性的表现
IF 4.4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
IEEE Transactions on Circuits and Systems II: Express Briefs
Pub Date : 2024-08-09 DOI: 10.1109/tcsii.2024.3441529
Qing Zhang, Weigang Sun, Yongxiang Xia
{"title":"Performance of Leader-Follower Coherence for Selecting Leaders Using Node Centrality Indices","authors":"Qing Zhang, Weigang Sun, Yongxiang Xia","doi":"10.1109/tcsii.2024.3441529","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3441529","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":null,"pages":null},"PeriodicalIF":4.4,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141932455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3 x 16 Gb/s Compact Single-Ended PAM4 Transmitters With Inverter-Based Crosstalk Compensation for Memory Interfaces 3 x 16 Gb/秒紧凑型单端 PAM4 发射器，带基于变频器的串音补偿，用于存储器接口
IF 4.4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
IEEE Transactions on Circuits and Systems II: Express Briefs
Pub Date : 2024-08-08 DOI: 10.1109/tcsii.2024.3440999
Changjae Moon, Iksu Jang, Sungmin Lim, Yaejoon Huh, Byungsub Kim
{"title":"3 x 16 Gb/s Compact Single-Ended PAM4 Transmitters With Inverter-Based Crosstalk Compensation for Memory Interfaces","authors":"Changjae Moon, Iksu Jang, Sungmin Lim, Yaejoon Huh, Byungsub Kim","doi":"10.1109/tcsii.2024.3440999","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3440999","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":null,"pages":null},"PeriodicalIF":4.4,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141932457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS 采用 28-nm CMOS 的 102-Gb/s/lane 1.4-Vppd 线性范围 PAM-8 接收机前端，具有多路径连续时间线性均衡功能
IF 4.4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
IEEE Transactions on Circuits and Systems II: Express Briefs
Pub Date : 2024-08-08 DOI: 10.1109/tcsii.2024.3441060
Sangwan Lee, Hyeongmin Seo, Seungwoo Son, Sunoh Yeom, Jaeduk Han
{"title":"A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS","authors":"Sangwan Lee, Hyeongmin Seo, Seungwoo Son, Sunoh Yeom, Jaeduk Han","doi":"10.1109/tcsii.2024.3441060","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3441060","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":null,"pages":null},"PeriodicalIF":4.4,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141932477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
BiNPU: A 33.0 MOP/s/LUT Binary Neural Network Inference Processor Showing 88.26% CIFAR10 Accuracy With 1.9 Mbit On-Chip Parameters in a 28 nm FPGA BiNPU：33.0 MOP/s/LUT 二进制神经网络推理处理器，在 28 nm FPGA 中实现 88.26% 的 CIFAR10 精确度和 1.9 Mbit 片上参数
IF 4.4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
IEEE Transactions on Circuits and Systems II: Express Briefs
Pub Date : 2024-08-08 DOI: 10.1109/tcsii.2024.3440965
Gil-Ho Kwak, Tae-Hwan Kim
{"title":"BiNPU: A 33.0 MOP/s/LUT Binary Neural Network Inference Processor Showing 88.26% CIFAR10 Accuracy With 1.9 Mbit On-Chip Parameters in a 28 nm FPGA","authors":"Gil-Ho Kwak, Tae-Hwan Kim","doi":"10.1109/tcsii.2024.3440965","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3440965","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":null,"pages":null},"PeriodicalIF":4.4,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141932456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.09-pJ/b/dB 28-Gb/s Digital CDR With ISI-Resistant Phase Detector 带抗 ISI 相位检测器的 0.09-pJ/b/dB 28-Gb/s 数字 CDR
IF 4.4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
IEEE Transactions on Circuits and Systems II: Express Briefs
Pub Date : 2024-08-07 DOI: 10.1109/tcsii.2024.3440584
Suil Kang, Dongwoo Kang, Sinho Lee, Minkyo Shim, Seungha Roh, Sunjin Choi, Kwanseo Park
{"title":"A 0.09-pJ/b/dB 28-Gb/s Digital CDR With ISI-Resistant Phase Detector","authors":"Suil Kang, Dongwoo Kang, Sinho Lee, Minkyo Shim, Seungha Roh, Sunjin Choi, Kwanseo Park","doi":"10.1109/tcsii.2024.3440584","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3440584","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":null,"pages":null},"PeriodicalIF":4.4,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141932458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Memristor-Emulating-Integrate-and-Fire Neuron-Based Fully Neuromorphic Framework for Pattern Recognition 基于 Memristor-Emulating-Integrate-Fire神经元的全神经形态模式识别框架
IF 4.4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
IEEE Transactions on Circuits and Systems II: Express Briefs
Pub Date : 2024-08-07 DOI: 10.1109/tcsii.2024.3439687
Prashant Kumar, Rajeev Kumar Ranjan, Sung-Mo Kang
{"title":"Memristor-Emulating-Integrate-and-Fire Neuron-Based Fully Neuromorphic Framework for Pattern Recognition","authors":"Prashant Kumar, Rajeev Kumar Ranjan, Sung-Mo Kang","doi":"10.1109/tcsii.2024.3439687","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3439687","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":null,"pages":null},"PeriodicalIF":4.4,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141932459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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