Pub Date : 2024-11-25DOI: 10.1109/TCSII.2024.3505153
Jing Xie;Han Su;Dong Yang;Ben Niu
This brief concentrates on the problem of $H_{infty }$ anti-disturbance bumpless transfer control (ADBTC) of switched affine systems (SASs) with multiple types of disturbances. The $H_{infty }$ ADBTC strategy is put forward to achieve the bumpless transfer (BT) performance and the anti-disturbance performance, simultaneously. First, a more general switched affine disturbance observer is designed to estimate the external disturbances generated from the external SASs. Secondly, a novel BT performance constraint containing the system state, the disturbance observer state, and the affine terms is proposed to suppress the control bumps. Thirdly, a switched anti-disturbance BT controller and a state-dependent switching law are constructed. Then a solvable condition for the $H_{infty }$ ADBTC problem of SASs is derived. Finally, the proposed control scheme is validated by an example of a circuit model.
{"title":"H∞ Anti-Disturbance Bumpless Transfer Control for Switched Affine Systems With Its Application to a Circuit Model","authors":"Jing Xie;Han Su;Dong Yang;Ben Niu","doi":"10.1109/TCSII.2024.3505153","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3505153","url":null,"abstract":"This brief concentrates on the problem of \u0000<inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula>\u0000 anti-disturbance bumpless transfer control (ADBTC) of switched affine systems (SASs) with multiple types of disturbances. The \u0000<inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula>\u0000 ADBTC strategy is put forward to achieve the bumpless transfer (BT) performance and the anti-disturbance performance, simultaneously. First, a more general switched affine disturbance observer is designed to estimate the external disturbances generated from the external SASs. Secondly, a novel BT performance constraint containing the system state, the disturbance observer state, and the affine terms is proposed to suppress the control bumps. Thirdly, a switched anti-disturbance BT controller and a state-dependent switching law are constructed. Then a solvable condition for the \u0000<inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula>\u0000 ADBTC problem of SASs is derived. Finally, the proposed control scheme is validated by an example of a circuit model.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"238-242"},"PeriodicalIF":4.0,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TCSII.2024.3501113
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TCSII.2024.3501113","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3501113","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5069-5069"},"PeriodicalIF":4.0,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767257","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142757828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TCSII.2024.3490937
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3490937","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3490937","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767254","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142757820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-21DOI: 10.1109/TCSII.2024.3503771
Luhua Lin;Bowen Wang;Woogeun Rhee;Zhihua Wang
This brief describes an ultra-wideband (UWB) transceiver architecture that employs a frequency-hopping code-division multiple-access (FH-CDMA) scheme for secure multi-sensor connectivity with up to 18-channel capacity. By using distinct frequency-hopping (FH) patterns based on m-sequence, quantitative analysis and simulation results show that the FH-CDMA UWB system can support up to 18 users simultaneously sharing the same transmission band. The duty cycle control of a carrier signal for each FH cycle enables the transmitter to perform baseband clock synchronization with nano-second resolution. A prototype 7.5-GHz UWB transceiver is implemented in 65-nm CMOS. With the FH enabled, the transmitter meets the UWB spectrum mask. The receiver achieves a sensitivity of –91 dBm at 25 kb/s and exhibits <1-dB degradation when three users transmit signals simultaneously.
{"title":"A 7.5-GHz Frequency-Hopping CDMA UWB Transceiver for Secure Multi-Sensor Connectivity","authors":"Luhua Lin;Bowen Wang;Woogeun Rhee;Zhihua Wang","doi":"10.1109/TCSII.2024.3503771","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3503771","url":null,"abstract":"This brief describes an ultra-wideband (UWB) transceiver architecture that employs a frequency-hopping code-division multiple-access (FH-CDMA) scheme for secure multi-sensor connectivity with up to 18-channel capacity. By using distinct frequency-hopping (FH) patterns based on m-sequence, quantitative analysis and simulation results show that the FH-CDMA UWB system can support up to 18 users simultaneously sharing the same transmission band. The duty cycle control of a carrier signal for each FH cycle enables the transmitter to perform baseband clock synchronization with nano-second resolution. A prototype 7.5-GHz UWB transceiver is implemented in 65-nm CMOS. With the FH enabled, the transmitter meets the UWB spectrum mask. The receiver achieves a sensitivity of –91 dBm at 25 kb/s and exhibits <1-dB degradation when three users transmit signals simultaneously.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"163-167"},"PeriodicalIF":4.0,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-21DOI: 10.1109/TCSII.2024.3503659
Lijuan Wang;Yizhu Shen;Yun Qian;Yifan Ding;Sanming Hu
This brief proposes a low noise amplifier (LNA) with high gain at 220 GHz in bulk CMOS process. A $G_{max }$ -core is employed to simultaneously realize noise and power matching as well as provide high gain. A segmented design methodology for LNAs in terahertz band is employed to trade-off gain and noise. Incorporating the $G_{max }$ -core with design methodology, a 220 GHz LNA is designed with balanced noise and gain performance. Fabricated using 40nm bulk CMOS process, measurement results reveal a minimum noise figure of 9.7 dB, a maximum gain of 24.8 dB between 214-225 GHz, and a saturated output power of −0.58 dBm at 220 GHz, while consuming only 36.9 mW. The LNA occupies a compact total area of 0.2 mm2, with a core area of 0.047 mm2. To the best of the authors’ knowledge, this represents the lowest noise figure achieved by LNA above 200 GHz using bulk CMOS technology.
{"title":"A 220-GHz LNA With 9.7-dB Noise Figure and 24.6-dB Gain in 40-nm Bulk CMOS","authors":"Lijuan Wang;Yizhu Shen;Yun Qian;Yifan Ding;Sanming Hu","doi":"10.1109/TCSII.2024.3503659","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3503659","url":null,"abstract":"This brief proposes a low noise amplifier (LNA) with high gain at 220 GHz in bulk CMOS process. A \u0000<inline-formula> <tex-math>$G_{max }$ </tex-math></inline-formula>\u0000-core is employed to simultaneously realize noise and power matching as well as provide high gain. A segmented design methodology for LNAs in terahertz band is employed to trade-off gain and noise. Incorporating the \u0000<inline-formula> <tex-math>$G_{max }$ </tex-math></inline-formula>\u0000-core with design methodology, a 220 GHz LNA is designed with balanced noise and gain performance. Fabricated using 40nm bulk CMOS process, measurement results reveal a minimum noise figure of 9.7 dB, a maximum gain of 24.8 dB between 214-225 GHz, and a saturated output power of −0.58 dBm at 220 GHz, while consuming only 36.9 mW. The LNA occupies a compact total area of 0.2 mm2, with a core area of 0.047 mm2. To the best of the authors’ knowledge, this represents the lowest noise figure achieved by LNA above 200 GHz using bulk CMOS technology.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"113-117"},"PeriodicalIF":4.0,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-20DOI: 10.1109/TCSII.2024.3503363
Marie Andrä;Arkadiusz Dawiec;Rafal Kleczek;Piotr Kmon;Claude Menneglier;Fabienne Orsini;Piotr Otfinowski;Pawel Grybos
A new single photon-counting ASIC prototype called UFERI (Ultra-Fast Energy Resolved Imager) with a matrix of $42times 42$ pixels of $75~mu $ m pitch is developed by the Detector Group of the SOLEIL synchrotron and the Microelectronics Group from AGH University of Krakow, in preparation for the upcoming upgrade of the SOLEIL synchrotron to a fourth-generation facility. The detector is dedicated to pseudo-Laue diffraction applications in intense, pink beams at photon energies between 5 to 30 keV. With its three thresholds and very small offset spread from pixel to pixel of about 1.1 mV, UFERI can discriminate three energy levels while its short dead time ensures a high count rate capability of up to 6 Mcounts/s/pix (10% count rate loss). To keep both, a low noise and a high count rate operation, a front-end amplifier’s feedback capacitor discharge technique is implemented on-chip, enabling high-speed chip operation with an Equivalent Noise Charge (ENC) of 86 e- rms. The UFERI chip can operate with detector signals of both polarities (holes and electrons) and consumes $42~mu $ W/pixel. In this publication, we present a description of the ASIC’s architecture as well as characterization results. The energy calibration, threshold dispersion, gain spread, as well as noise and count rate performance of the UFERI prototype are presented.
{"title":"UFERI—Ultra-Fast Energy Resolved Imager for Next Generation Synchrotron Experiments","authors":"Marie Andrä;Arkadiusz Dawiec;Rafal Kleczek;Piotr Kmon;Claude Menneglier;Fabienne Orsini;Piotr Otfinowski;Pawel Grybos","doi":"10.1109/TCSII.2024.3503363","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3503363","url":null,"abstract":"A new single photon-counting ASIC prototype called UFERI (Ultra-Fast Energy Resolved Imager) with a matrix of \u0000<inline-formula> <tex-math>$42times 42$ </tex-math></inline-formula>\u0000 pixels of \u0000<inline-formula> <tex-math>$75~mu $ </tex-math></inline-formula>\u0000m pitch is developed by the Detector Group of the SOLEIL synchrotron and the Microelectronics Group from AGH University of Krakow, in preparation for the upcoming upgrade of the SOLEIL synchrotron to a fourth-generation facility. The detector is dedicated to pseudo-Laue diffraction applications in intense, pink beams at photon energies between 5 to 30 keV. With its three thresholds and very small offset spread from pixel to pixel of about 1.1 mV, UFERI can discriminate three energy levels while its short dead time ensures a high count rate capability of up to 6 Mcounts/s/pix (10% count rate loss). To keep both, a low noise and a high count rate operation, a front-end amplifier’s feedback capacitor discharge technique is implemented on-chip, enabling high-speed chip operation with an Equivalent Noise Charge (ENC) of 86 e- rms. The UFERI chip can operate with detector signals of both polarities (holes and electrons) and consumes \u0000<inline-formula> <tex-math>$42~mu $ </tex-math></inline-formula>\u0000W/pixel. In this publication, we present a description of the ASIC’s architecture as well as characterization results. The energy calibration, threshold dispersion, gain spread, as well as noise and count rate performance of the UFERI prototype are presented.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"108-112"},"PeriodicalIF":4.0,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10758659","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a high-voltage RF source for trapped-ion quantum computing. It consists of an external transformer and a driver implemented on a single chip. The use of a transformer significantly reduces on-chip current driving requirements to 32mA while delivering a 620-VPP to the output. The proposed architecture also achieves a 20dB improvement in SFDR compared to the previous work. This brief includes a guide for the optimal transformer design that can maximize the output voltage with the minimum power consumption. The proposed design scheme provides a miniaturized implementation of the RF source and makes it promising for scalable quantum computing with multiple RF sources.
{"title":"A 600-V Peak-to-Peak 65-dBc RF Signal Source for Trapped-Ion Quantum Computing","authors":"Seongchan Bae;Myunghun Kim;Junhee Cho;Moonjoo Lee;Jae-Yoon Sim","doi":"10.1109/TCSII.2024.3502802","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3502802","url":null,"abstract":"This brief presents a high-voltage RF source for trapped-ion quantum computing. It consists of an external transformer and a driver implemented on a single chip. The use of a transformer significantly reduces on-chip current driving requirements to 32mA while delivering a 620-VPP to the output. The proposed architecture also achieves a 20dB improvement in SFDR compared to the previous work. This brief includes a guide for the optimal transformer design that can maximize the output voltage with the minimum power consumption. The proposed design scheme provides a miniaturized implementation of the RF source and makes it promising for scalable quantum computing with multiple RF sources.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"103-107"},"PeriodicalIF":4.0,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a 200 MS/s 12 bits cryogenic CMOS (cryo-CMOS) current steering (CS) digital to analog converter (DAC) designed to operate from 300K down to 4 K. The DAC is designed and simulated using a 110nm cryo-CMOS SPICE model, achieving practical performance at 4K. Mismatch in transistor threshold voltage, carrier mobility and layout at cryogenic temperature can lead to unpredictability and incorrect bias voltage, so an off-chip resistor current mirror structure was adopted for the bias circuit. Due to the flexible configuration of the off-chip resistance value and the PMOS current source, this bias structure has certain advantages in overcoming the extended cryogenic nonlinear and mismatch effects to get the correct bias voltage at 4K. This DAC is implemented in a 110nm CMOS process, with a core area <�$0.21{mm}^{2}$ . With 9mA full-scale output current, this DAC consumes less than 22mW at 4K. The SFDR achieves 57.94dB, 48.59dB, and 35.33dB at 4.76MHz, 43.67MHz, and 93.47MHz frequency of full swing output, respectively, at 200MS/s and 4K, and the differential and integral nonlinearity are 0.79 LSB and 3.81 LSB, respectively, at 4K.
{"title":"A 200-MS/s 12-b Cryo-CMOS CS DAC for Quantum Computing","authors":"Changchun Zhou;Xuexi He;Bolun Zeng;Jun Xu;Chao Luo;Guoping Guo","doi":"10.1109/TCSII.2024.3502462","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3502462","url":null,"abstract":"This brief presents a 200 MS/s 12 bits cryogenic CMOS (cryo-CMOS) current steering (CS) digital to analog converter (DAC) designed to operate from 300K down to 4 K. The DAC is designed and simulated using a 110nm cryo-CMOS SPICE model, achieving practical performance at 4K. Mismatch in transistor threshold voltage, carrier mobility and layout at cryogenic temperature can lead to unpredictability and incorrect bias voltage, so an off-chip resistor current mirror structure was adopted for the bias circuit. Due to the flexible configuration of the off-chip resistance value and the PMOS current source, this bias structure has certain advantages in overcoming the extended cryogenic nonlinear and mismatch effects to get the correct bias voltage at 4K. This DAC is implemented in a 110nm CMOS process, with a core area <\u0000<inline-formula> <tex-math>$0.21{mm}^{2}$ </tex-math></inline-formula>\u0000. With 9mA full-scale output current, this DAC consumes less than 22mW at 4K. The SFDR achieves 57.94dB, 48.59dB, and 35.33dB at 4.76MHz, 43.67MHz, and 93.47MHz frequency of full swing output, respectively, at 200MS/s and 4K, and the differential and integral nonlinearity are 0.79 LSB and 3.81 LSB, respectively, at 4K.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"98-102"},"PeriodicalIF":4.0,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In compact and cost-constrained IoT low-power applications, the ultra-low-voltage (ULV) on-chip frequency-locked loop (FLL) offers a potential alternative to crystal oscillators while providing high energy efficiency. Compared to open-loop oscillators, the proposed FLL reuses the time-domain amplifier (TDA) as a temperature sensor, allowing the sleep timer to be calibrated with the use of a look-up table (LUT) to further enhance temperature accuracy. A redesigned OTA-accelerated second-order loop filter (LF) addresses the issue of excessive locking time in such low-frequency FLLs. Fabricated in 65-nm CMOS process, the prototype integrated circuit (IC) achieves a temperature coefficient (TC) of 41.7 ppm/°C with calibration based on an LUT and consumes 66.8 nW at 0.4-V supply while producing a 500-kHz frequency.
{"title":"A 0.4-V 500-kHz FLL With Reused TDA-Based Calibration and OTA-Accelerated Technique in 65-nm CMOS for Sleep Timer","authors":"Linwei Wang;Rong Zhou;Jianhang Yang;Zhen Li;Zhicheng Dong;Shubin Liu;Zhangming Zhu","doi":"10.1109/TCSII.2024.3502159","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3502159","url":null,"abstract":"In compact and cost-constrained IoT low-power applications, the ultra-low-voltage (ULV) on-chip frequency-locked loop (FLL) offers a potential alternative to crystal oscillators while providing high energy efficiency. Compared to open-loop oscillators, the proposed FLL reuses the time-domain amplifier (TDA) as a temperature sensor, allowing the sleep timer to be calibrated with the use of a look-up table (LUT) to further enhance temperature accuracy. A redesigned OTA-accelerated second-order loop filter (LF) addresses the issue of excessive locking time in such low-frequency FLLs. Fabricated in 65-nm CMOS process, the prototype integrated circuit (IC) achieves a temperature coefficient (TC) of 41.7 ppm/°C with calibration based on an LUT and consumes 66.8 nW at 0.4-V supply while producing a 500-kHz frequency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"93-97"},"PeriodicalIF":4.0,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-18DOI: 10.1109/TCSII.2024.3501384
Jian Zhang;Ming Zhai;Yichen Liu;Xiangjie Yi;Dawei Wang;Wei Zhu;Yan Wang
This brief presents a broadband bidirectional four-element four-beam beamformer. By utilizing the bidirectional attenuator, and phase shifter, this design achieves a 15.5 dB gain range and a 360° phase-shifting range in both receiver (RX) mode and transmitter (TX) mode. A load state switch is integrated with this design to realize more than 30 dB signal bypass of a certain path while maintaining the input/output matching unchanged to make system-level calibration more convenient. An innovative crossover design with horizontal and vertical ground shielding is proposed to suppress the crosstalk caused by the capacitive couplings at the unavoidable cross intersection in the FC network. The measurement results demonstrate that the proposed beamformer achieves < 0.12/0.26 dB root-mean-square (RMS) amplitude error and < 4.2/3.9° RMS phase error in RX/TX mode at 4.5–7 GHz. To the best of our knowledge, this design is the first broadband multi-beam beamformer that can support both RX and TX modes.
{"title":"A Broadband Bidirectional Four-Element Four-Beam Beamformer With Compact Floorplan in a 65nm CMOS Technology","authors":"Jian Zhang;Ming Zhai;Yichen Liu;Xiangjie Yi;Dawei Wang;Wei Zhu;Yan Wang","doi":"10.1109/TCSII.2024.3501384","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3501384","url":null,"abstract":"This brief presents a broadband bidirectional four-element four-beam beamformer. By utilizing the bidirectional attenuator, and phase shifter, this design achieves a 15.5 dB gain range and a 360° phase-shifting range in both receiver (RX) mode and transmitter (TX) mode. A load state switch is integrated with this design to realize more than 30 dB signal bypass of a certain path while maintaining the input/output matching unchanged to make system-level calibration more convenient. An innovative crossover design with horizontal and vertical ground shielding is proposed to suppress the crosstalk caused by the capacitive couplings at the unavoidable cross intersection in the FC network. The measurement results demonstrate that the proposed beamformer achieves < 0.12/0.26 dB root-mean-square (RMS) amplitude error and < 4.2/3.9° RMS phase error in RX/TX mode at 4.5–7 GHz. To the best of our knowledge, this design is the first broadband multi-beam beamformer that can support both RX and TX modes.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"158-162"},"PeriodicalIF":4.0,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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