Pub Date : 2024-08-14DOI: 10.1109/TCSII.2024.3443459
Adilet Dossanov;Christian Ziegler;Vadim Issakov
This brief presents an ultra-low-power sub-1V voltage reference circuit using a self-cascode technique to improve power supply rejection ratio (PSRR) for battery-powered applications. The proposed voltage reference circuit has been fabricated in 22 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology, and it occupies an active area of 0.0104 $text {mm}^{{2}}$ . The measured average output voltage $text {V}_{text {REF}}$ from 12 samples at room temperature is 598 mV with a standard deviation of 0.37%. The $text {V}_{text {REF}}$ shows measured average temperature coefficient $text {TC}_{text {avg}}$ of 61 $text {ppm/}^{circ }text {C}$ over the temperature range of −40°C to 120°C, line sensitivity of 0.12%/V from 1.2V to 1.8V supply voltages, and measured PSRR of 66 dB at 10 Hz. A total power consumption is 45.6nW from a 1.2V supply voltage.
{"title":"Ultra-Low-Power High PSRR Sub-1 V Voltage Reference Circuit in 22 nm FDSOI CMOS","authors":"Adilet Dossanov;Christian Ziegler;Vadim Issakov","doi":"10.1109/TCSII.2024.3443459","DOIUrl":"10.1109/TCSII.2024.3443459","url":null,"abstract":"This brief presents an ultra-low-power sub-1V voltage reference circuit using a self-cascode technique to improve power supply rejection ratio (PSRR) for battery-powered applications. The proposed voltage reference circuit has been fabricated in 22 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology, and it occupies an active area of 0.0104\u0000<inline-formula> <tex-math>$text {mm}^{{2}}$ </tex-math></inline-formula>\u0000. The measured average output voltage \u0000<inline-formula> <tex-math>$text {V}_{text {REF}}$ </tex-math></inline-formula>\u0000 from 12 samples at room temperature is 598 mV with a standard deviation of 0.37%. The \u0000<inline-formula> <tex-math>$text {V}_{text {REF}}$ </tex-math></inline-formula>\u0000 shows measured average temperature coefficient \u0000<inline-formula> <tex-math>$text {TC}_{text {avg}}$ </tex-math></inline-formula>\u0000 of 61\u0000<inline-formula> <tex-math>$text {ppm/}^{circ }text {C}$ </tex-math></inline-formula>\u0000 over the temperature range of −40°C to 120°C, line sensitivity of 0.12%/V from 1.2V to 1.8V supply voltages, and measured PSRR of 66 dB at 10 Hz. A total power consumption is 45.6nW from a 1.2V supply voltage.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4643-4647"},"PeriodicalIF":4.0,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-14DOI: 10.1109/TCSII.2024.3443421
Ye Lin;Anying Jiang;Jingjing Lv;Yuan Du;Li Du
In this brief, a novel offset-cancellation (OC) technique is proposed, utilizing differential pair Charge-Trap Transistors (CTTs) to cancel offset voltage (VOS). The threshold voltage (Vth) degradation of programmed CTTs is characterized and modeled in TSMC 22-nm technology. By utilizing the Vth degradation model of CTTs, an asynchronous programming scheme is proposed to selectively program one of the CTTs based on the differential Vth ( $Delta $ Vth) in each programming (PRG) operation of the differential pair CTTs. The experiment shows that the $Delta $ Vth effectively reduces to less than 1mV, and displays negligible retention loss at 27°C and 85°C based on the differential pair CTTs and asynchronous programming scheme.
{"title":"An Offset-Cancellation Technique Using Charge-Trap Transistors and Asynchronous Programming Scheme","authors":"Ye Lin;Anying Jiang;Jingjing Lv;Yuan Du;Li Du","doi":"10.1109/TCSII.2024.3443421","DOIUrl":"10.1109/TCSII.2024.3443421","url":null,"abstract":"In this brief, a novel offset-cancellation (OC) technique is proposed, utilizing differential pair Charge-Trap Transistors (CTTs) to cancel offset voltage (VOS). The threshold voltage (Vth) degradation of programmed CTTs is characterized and modeled in TSMC 22-nm technology. By utilizing the Vth degradation model of CTTs, an asynchronous programming scheme is proposed to selectively program one of the CTTs based on the differential Vth (\u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000Vth) in each programming (PRG) operation of the differential pair CTTs. The experiment shows that the \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000Vth effectively reduces to less than 1mV, and displays negligible retention loss at 27°C and 85°C based on the differential pair CTTs and asynchronous programming scheme.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4638-4642"},"PeriodicalIF":4.0,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The performance of Sense Amplifiers (SAs) is critical to high-speed SRAMs. Large-offset and slow-resolving SAs can create a bottleneck in the SRAM performance at low voltages because of which a lot of emphasis is laid on designing faster SAs, often at the cost of area. In this brief, we propose a variation-tolerant Supply Boosted Voltage Sense Amplifier (SBVSA) that is up to 45% faster at $5sigma $ than a Conventional Voltage Sense Amplifier (CVSA) in 22nm CMOS technology. This gain is achieved with an area overhead of less than 1% in SRAM instances while improving the read performance of the instances by up to 9% in 22nm CMOS.
{"title":"Up to 45% Faster Supply Boosted Voltage Sense Amplifier (SBVSA) for High-Speed SRAMs","authors":"Rachit Sharma;Anuj Grover;Ajay Shroti;Shouri Chatterjee","doi":"10.1109/TCSII.2024.3443594","DOIUrl":"10.1109/TCSII.2024.3443594","url":null,"abstract":"The performance of Sense Amplifiers (SAs) is critical to high-speed SRAMs. Large-offset and slow-resolving SAs can create a bottleneck in the SRAM performance at low voltages because of which a lot of emphasis is laid on designing faster SAs, often at the cost of area. In this brief, we propose a variation-tolerant Supply Boosted Voltage Sense Amplifier (SBVSA) that is up to 45% faster at \u0000<inline-formula> <tex-math>$5sigma $ </tex-math></inline-formula>\u0000 than a Conventional Voltage Sense Amplifier (CVSA) in 22nm CMOS technology. This gain is achieved with an area overhead of less than 1% in SRAM instances while improving the read performance of the instances by up to 9% in 22nm CMOS.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4683-4687"},"PeriodicalIF":4.0,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-14DOI: 10.1109/tcsii.2024.3444310
Cheng Fan, Lei Su, Xihong Fei, Hao Shen
{"title":"Secure Control of Discrete-Time Markov Jump Power Systems Under Hybrid Attacks Based on Mode Detection Information","authors":"Cheng Fan, Lei Su, Xihong Fei, Hao Shen","doi":"10.1109/tcsii.2024.3444310","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3444310","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"10 1","pages":""},"PeriodicalIF":4.4,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-13DOI: 10.1109/tcsii.2024.3442864
Ying Zhao, Zhe Feng, Peng Wang
{"title":"Dissipativity-Based Bumpless Transfer Control for Switched Positive Systems","authors":"Ying Zhao, Zhe Feng, Peng Wang","doi":"10.1109/tcsii.2024.3442864","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3442864","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"13 1","pages":""},"PeriodicalIF":4.4,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-12DOI: 10.1109/TCSII.2024.3442215
Shin-Hyun Jeong;Yong-Un Jeong;Suhwan Kim
This brief presents an on-chip bias temperature instability (BTI) monitor to accurately detect performance degradation caused by negative BTI (NBTI) and positive BTI (PBTI) in DRAM periphery. The proposed BTI monitor is capable of isolated measurement of both NBTI and PBTI using a configurable pull-up and pull-down switching network. The dual-delay line topology also ensures fast measurement to minimize unwanted BTI recovery, which reduces measurement accuracy. In addition, a calibration scheme for process variation is proposed using body biasing of devices that mimics BTI-induced stress to further enhance measurement accuracy.
{"title":"An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery","authors":"Shin-Hyun Jeong;Yong-Un Jeong;Suhwan Kim","doi":"10.1109/TCSII.2024.3442215","DOIUrl":"10.1109/TCSII.2024.3442215","url":null,"abstract":"This brief presents an on-chip bias temperature instability (BTI) monitor to accurately detect performance degradation caused by negative BTI (NBTI) and positive BTI (PBTI) in DRAM periphery. The proposed BTI monitor is capable of isolated measurement of both NBTI and PBTI using a configurable pull-up and pull-down switching network. The dual-delay line topology also ensures fast measurement to minimize unwanted BTI recovery, which reduces measurement accuracy. In addition, a calibration scheme for process variation is proposed using body biasing of devices that mimics BTI-induced stress to further enhance measurement accuracy.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4628-4632"},"PeriodicalIF":4.0,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-12DOI: 10.1109/TCSII.2024.3442200
Dongwoo Kang;Han-Gon Ko;Kwanseo Park
This brief presents a 3-channel single-ended three-level pulse amplitude modulation (PAM-3) transmitter (TX) for high-density multi-channel systems. The proposed TX employs a crosstalk cancellation (XTC) technique for multi-level signaling, which utilizes the information of transitions obtained through the PAM-3 encoding. Combining with a feedforward equalizer (FFE), the proposed XTC technique is implemented by a minimal hardware overhead. Fabricated in 28-nm CMOS technology, a prototype 3-channel TX is tested with channels which insertion loss and signal-to-crosstalk ratio are 7.8 dB and 5.7 dB, respectively. The proposed TX achieves a data rate of 12 Gb/s/ch with a significant XT-induced jitter (CIJ) reduction of 0.432 UI. Furthermore, it provides an energy efficiency of 1.26 pJ/b while occupying an active area of 0.007 mm2 per channel.
{"title":"A 3×12 -Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS","authors":"Dongwoo Kang;Han-Gon Ko;Kwanseo Park","doi":"10.1109/TCSII.2024.3442200","DOIUrl":"10.1109/TCSII.2024.3442200","url":null,"abstract":"This brief presents a 3-channel single-ended three-level pulse amplitude modulation (PAM-3) transmitter (TX) for high-density multi-channel systems. The proposed TX employs a crosstalk cancellation (XTC) technique for multi-level signaling, which utilizes the information of transitions obtained through the PAM-3 encoding. Combining with a feedforward equalizer (FFE), the proposed XTC technique is implemented by a minimal hardware overhead. Fabricated in 28-nm CMOS technology, a prototype 3-channel TX is tested with channels which insertion loss and signal-to-crosstalk ratio are 7.8 dB and 5.7 dB, respectively. The proposed TX achieves a data rate of 12 Gb/s/ch with a significant XT-induced jitter (CIJ) reduction of 0.432 UI. Furthermore, it provides an energy efficiency of 1.26 pJ/b while occupying an active area of 0.007 mm2 per channel.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4633-4637"},"PeriodicalIF":4.0,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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