This brief introduces a novel adaptive optimal output-feedback controller for permanent magnet synchronous motor (PMSM) systems, eliminating the need for prior knowledge of system dynamics, numerous integral window functions, or unmeasurable states and load torque. Initially, we design an adaptive optimal output-feedback controller by constructing internal states. Then, a policy iteration algorithm based on adaptive dynamic programming approximates the optimal output-feedback gain using only input and trajectory tracking error information. Notably, this method does not require the minimal polynomial of an exosystem or the solution of regulator equations, facilitating the overall design of the feedforward-feedback controller. The effectiveness of the proposed learning algorithm is validated on a PMSM system.
{"title":"Optimal Output-Feedback Controller Design Using Adaptive Dynamic Programming: A Permanent Magnet Synchronous Motor Application","authors":"Zhongyang Wang;Huiru Ye;Youqing Wang;Yukun Shi;Li Liang","doi":"10.1109/TCSII.2024.3483909","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3483909","url":null,"abstract":"This brief introduces a novel adaptive optimal output-feedback controller for permanent magnet synchronous motor (PMSM) systems, eliminating the need for prior knowledge of system dynamics, numerous integral window functions, or unmeasurable states and load torque. Initially, we design an adaptive optimal output-feedback controller by constructing internal states. Then, a policy iteration algorithm based on adaptive dynamic programming approximates the optimal output-feedback gain using only input and trajectory tracking error information. Notably, this method does not require the minimal polynomial of an exosystem or the solution of regulator equations, facilitating the overall design of the feedforward-feedback controller. The effectiveness of the proposed learning algorithm is validated on a PMSM system.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"208-212"},"PeriodicalIF":4.0,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The number of IoT devices has grown significantly in recent years, and edge computing in IoT is considered a new and growing trend in the technology industry. While cryptography is widely used to enhance the security of IoT devices, it also carries limitations such as resource constraints or latency. Therefore, lightweight cryptography (LWC) balances commensurate resource usage and maintaining security while minimizing system costs. The ASCON stands out among the LWC algorithms as a potential target for implementation and cryptoanalysis. It provides authenticated encryption with associated data (AEAD) and hashing functionalities in many variants, aiming for various applications. In this brief, we present an implementation of Ascon cryptography as a peripheral of a RISC-V System-on-a-Chip (SoC). The ASCON crypto core occupies 1,424 LUTs in FPGA and 17.4 kGE in 180nm CMOS technology while achieving 417 Gbits/J energy efficiency at a supply voltage of 1.0V and frequency of 2 MHz.
{"title":"ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications","authors":"Khai-Duy Nguyen;Tuan-Kiet Dang;Binh Kieu-Do-Nguyen;Duc-Hung Le;Cong-Kha Pham;Trong-Thuc Hoang","doi":"10.1109/TCSII.2024.3483214","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3483214","url":null,"abstract":"The number of IoT devices has grown significantly in recent years, and edge computing in IoT is considered a new and growing trend in the technology industry. While cryptography is widely used to enhance the security of IoT devices, it also carries limitations such as resource constraints or latency. Therefore, lightweight cryptography (LWC) balances commensurate resource usage and maintaining security while minimizing system costs. The ASCON stands out among the LWC algorithms as a potential target for implementation and cryptoanalysis. It provides authenticated encryption with associated data (AEAD) and hashing functionalities in many variants, aiming for various applications. In this brief, we present an implementation of Ascon cryptography as a peripheral of a RISC-V System-on-a-Chip (SoC). The ASCON crypto core occupies 1,424 LUTs in FPGA and 17.4 kGE in 180nm CMOS technology while achieving 417 Gbits/J energy efficiency at a supply voltage of 1.0V and frequency of 2 MHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"278-282"},"PeriodicalIF":4.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-18DOI: 10.1109/TCSII.2024.3483575
Guangyu Yan;Wei Han;Chang Liu;Bowang Zhang;Meixuan Li
This brief presents a novel simultaneous wireless power and data transfer (SWPDT) system that combines inductive and capacitive couplings, featuring full-duplex communication with high data transfer rates. Specifically, the power and forward data are transferred through inductive coupling respectively by means of the DD coils and Q coils, while the backward data is transferred through capacitive coupling by means of the stray capacitances. Because of the decoupling characteristic of the DDQ coil structure and the use of two coupling types, the interferences among the power, forward data, and backward data are relatively low. By integrating the two coupling types, a comprehensive circuit model of full-duplex data transfer is established and analyzed. Finally, a 145-W prototype is actualized with 91.4% power transfer efficiency. The forward and backward data transfer rates are 150 kbps and 600 kbps, respectively, demonstrating the feasibility of the proposed system.
{"title":"A Simultaneous Wireless Power and Full-Duplex Data Transfer System Using a Mix of Inductive and Capacitive Couplings","authors":"Guangyu Yan;Wei Han;Chang Liu;Bowang Zhang;Meixuan Li","doi":"10.1109/TCSII.2024.3483575","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3483575","url":null,"abstract":"This brief presents a novel simultaneous wireless power and data transfer (SWPDT) system that combines inductive and capacitive couplings, featuring full-duplex communication with high data transfer rates. Specifically, the power and forward data are transferred through inductive coupling respectively by means of the DD coils and Q coils, while the backward data is transferred through capacitive coupling by means of the stray capacitances. Because of the decoupling characteristic of the DDQ coil structure and the use of two coupling types, the interferences among the power, forward data, and backward data are relatively low. By integrating the two coupling types, a comprehensive circuit model of full-duplex data transfer is established and analyzed. Finally, a 145-W prototype is actualized with 91.4% power transfer efficiency. The forward and backward data transfer rates are 150 kbps and 600 kbps, respectively, demonstrating the feasibility of the proposed system.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"323-327"},"PeriodicalIF":4.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lattice-based cryptography (LBC) exploits the learning with errors (LWE) problem and is the main algorithm standardized for Post-Quantum Cryptography (PQC). Number theoretic transforms (NTT) account for most of the latency and energy in the computation of the LWE problem. This brief presents a Compute-in-Memory (CIM) configurable-pipeline NTT accelerator for PQC. The accelerator incorporates a bidirectional pipeline array to minimize data latency, CIM processing elements to reduce memory access, and a parallel PQC circuit for LBC protocol deployment. A 28 nm chip of the accelerator consumes only 13 nJ per 256-point NTT, while achieving a throughput of 75.6 KOPS that achieves a remarkable reduction of up to 78% in clock cycles and a 45% reduction in energy consumption than state-of-the-art designs.
{"title":"A 28 nm 75.6 KOPS 13 nJ Computing-in-Memory Pipeline Number Theoretic Transform Accelerator for PQC","authors":"Jialiang Zhu;Yiyang Yuan;Long Nie;Weiye Tang;Ming Li;Hao Wu;Xiaojin Zhao;Guozhong Xing;Feng Zhang","doi":"10.1109/TCSII.2024.3481996","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3481996","url":null,"abstract":"Lattice-based cryptography (LBC) exploits the learning with errors (LWE) problem and is the main algorithm standardized for Post-Quantum Cryptography (PQC). Number theoretic transforms (NTT) account for most of the latency and energy in the computation of the LWE problem. This brief presents a Compute-in-Memory (CIM) configurable-pipeline NTT accelerator for PQC. The accelerator incorporates a bidirectional pipeline array to minimize data latency, CIM processing elements to reduce memory access, and a parallel PQC circuit for LBC protocol deployment. A 28 nm chip of the accelerator consumes only 13 nJ per 256-point NTT, while achieving a throughput of 75.6 KOPS that achieves a remarkable reduction of up to 78% in clock cycles and a 45% reduction in energy consumption than state-of-the-art designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"273-277"},"PeriodicalIF":4.0,"publicationDate":"2024-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a wideband continuous-rate reference-less ring-oscillator-based PAM4 CDR. Our proposed frequency-detection-gain-enhanced phase/frequency detector (GE-PFD), in which only two logic gates are added to the Alexander bang-bang phase detector, significantly speeds up the frequency acquisition process of our CDR with wide capture range by controlling an auxiliary charge pump (A-CP). This technique eliminates separate FD or extra clock phases in prior PFDs, thus saving power. Fabricated in a 40-nm CMOS process, our CDR prototype achieves 6-64-Gb/s data rate range, 19.8-Gb/s/ $mu $ s acquisition speed, and <10–12 bit error rate with a PRBS-31 input stream. The energy efficiency is 0.41-pJ/bit, in which only 0.02 pJ/bit is contributed by the extra logic gates of the FDGE-PFD and A-CP.
{"title":"A 6–64-Gb/s 0.41-pJ/Bit Reference-Less PAM4 CDR Using a Frequency-Detection-Gain-Enhanced PFD Achieving 19.8-Gb/s/μs Acquisition Speed","authors":"Liyan Feng;Tuo Li;Xiaofeng Zou;Xiaoming Xiong;Zhao Zhang","doi":"10.1109/TCSII.2024.3481436","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3481436","url":null,"abstract":"This brief presents a wideband continuous-rate reference-less ring-oscillator-based PAM4 CDR. Our proposed frequency-detection-gain-enhanced phase/frequency detector (GE-PFD), in which only two logic gates are added to the Alexander bang-bang phase detector, significantly speeds up the frequency acquisition process of our CDR with wide capture range by controlling an auxiliary charge pump (A-CP). This technique eliminates separate FD or extra clock phases in prior PFDs, thus saving power. Fabricated in a 40-nm CMOS process, our CDR prototype achieves 6-64-Gb/s data rate range, 19.8-Gb/s/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000s acquisition speed, and <10–12 bit error rate with a PRBS-31 input stream. The energy efficiency is 0.41-pJ/bit, in which only 0.02 pJ/bit is contributed by the extra logic gates of the FDGE-PFD and A-CP.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"68-72"},"PeriodicalIF":4.0,"publicationDate":"2024-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-15DOI: 10.1109/TCSII.2024.3481002
Ke Chang;Guohe Zhang;Yang Pu;Yan Wang;Yuxin Wang
This brief proposes an improved architecture for multi-stage noise-shaping (MASH) $Sigma Delta $ modulators ( $Sigma Delta $ Ms), which can reduce quantization noise leakage and eliminate the requirement of high-gain opamps. Based on the proposed filter mismatch shaping (FMS) technique, filter mismatch between analog and digital domains in the MASH $Sigma Delta $ M can be mitigated, reducing inband quantization noise leakage and obtaining less sensitivity to opamps gain. Hence, the DC gain of opamps can be minimized, and simpler opamps with fewer stacked transistors would be allowed, facilitating low-voltage and energy-efficient operation. Fabricated in 55-nm CMOS and sampled at 3.2 MHz, the prototype modulator achieves a peak SNDR of 77.4 dB in a 110.3-kHz bandwidth (BW) while dissipating $116.5~mu $ W from a 1.2-V supply.
{"title":"MASH ΣΔ Modulator With Filter Mismatch Shaping Technique","authors":"Ke Chang;Guohe Zhang;Yang Pu;Yan Wang;Yuxin Wang","doi":"10.1109/TCSII.2024.3481002","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3481002","url":null,"abstract":"This brief proposes an improved architecture for multi-stage noise-shaping (MASH) \u0000<inline-formula> <tex-math>$Sigma Delta $ </tex-math></inline-formula>\u0000 modulators (\u0000<inline-formula> <tex-math>$Sigma Delta $ </tex-math></inline-formula>\u0000Ms), which can reduce quantization noise leakage and eliminate the requirement of high-gain opamps. Based on the proposed filter mismatch shaping (FMS) technique, filter mismatch between analog and digital domains in the MASH \u0000<inline-formula> <tex-math>$Sigma Delta $ </tex-math></inline-formula>\u0000M can be mitigated, reducing inband quantization noise leakage and obtaining less sensitivity to opamps gain. Hence, the DC gain of opamps can be minimized, and simpler opamps with fewer stacked transistors would be allowed, facilitating low-voltage and energy-efficient operation. Fabricated in 55-nm CMOS and sampled at 3.2 MHz, the prototype modulator achieves a peak SNDR of 77.4 dB in a 110.3-kHz bandwidth (BW) while dissipating \u0000<inline-formula> <tex-math>$116.5~mu $ </tex-math></inline-formula>\u0000W from a 1.2-V supply.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"63-67"},"PeriodicalIF":4.0,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-15DOI: 10.1109/TCSII.2024.3481068
Xiangwen Xin;Ping Luo;Hao Wang;Jingwei Huang;Xiaowen Chen;Chang Liu
This brief proposes an ultra-low-power low dropout (LDO) regulator using adaptive pole tracking and adaptive transconductance technique, aimed at further enhancing the efficiency of power management integrated circuits (PMIC). In light current loads, only the folded cascode amplifier is opened to provide excellent output voltage accuracy while reducing power consumption. In heavy current loads, activating the operational transconductance amplifier improves transient performance. An adaptive pole-tracking technique has been applied in the proposed LDO to ensure loop stability. In addition, a low-power bandgap reference was embedded into the proposed LDO, which simplifies the peripheral circuit of LDO in practical application. The proposed ultra-low-power LDO was fabricated in a $0.18~mu $ m BCD process, with an overshoot and undershoot voltage of 12mV, and ultra-low quiescent current of 96nA.
{"title":"A 96-nA Quiescent Current LDO With Embedded BGR Using Adaptive Pole Tracking and Adaptive Transconductance Technique","authors":"Xiangwen Xin;Ping Luo;Hao Wang;Jingwei Huang;Xiaowen Chen;Chang Liu","doi":"10.1109/TCSII.2024.3481068","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3481068","url":null,"abstract":"This brief proposes an ultra-low-power low dropout (LDO) regulator using adaptive pole tracking and adaptive transconductance technique, aimed at further enhancing the efficiency of power management integrated circuits (PMIC). In light current loads, only the folded cascode amplifier is opened to provide excellent output voltage accuracy while reducing power consumption. In heavy current loads, activating the operational transconductance amplifier improves transient performance. An adaptive pole-tracking technique has been applied in the proposed LDO to ensure loop stability. In addition, a low-power bandgap reference was embedded into the proposed LDO, which simplifies the peripheral circuit of LDO in practical application. The proposed ultra-low-power LDO was fabricated in a \u0000<inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>\u0000m BCD process, with an overshoot and undershoot voltage of 12mV, and ultra-low quiescent current of 96nA.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"318-322"},"PeriodicalIF":4.0,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-15DOI: 10.1109/TCSII.2024.3481069
Juwon Kim;Youngjoo Lee;Byung-Wook Min
This brief presents a compact Ka-band bi-directional variable gain phase shifter (BVGPS) using 28-nm CMOS technology. The BVGPS consists of a phase inverting bi-directional variable gain amplifier (PI-BVGA) and 3-bit switched-delay type phase shifter (STPS). The proposed PI-BVGA is implemented with a current cancelling topology for a low phase variation over a gain control range. The PI-BVGA can operate bi-directionally and provide 180° phase shift. Therefore, comparing the conventional BVGPS, this BVGPS achieves a high gain with the compact size since 180° phase shifter and single-pole double-throw (SPDT) switches are eliminated. The average rms phase error over the 16 dB gain control is 1.1° and measured rms phase and gain errors of 16 different phase states are 8.3° and 0.74 dB, respectively, at the center frequency. The maximum gain of the BVGPS is $0.7{pm }1$ .3 dB in the 16 different phase states with a power consumption of 40 mW. The BVGPS occupies 0.21 mm2, excluding the pads.
{"title":"A Compact Ka-Band Variable Gain Phase Shifter With Bi-Directional Phase Inverting Amplifier","authors":"Juwon Kim;Youngjoo Lee;Byung-Wook Min","doi":"10.1109/TCSII.2024.3481069","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3481069","url":null,"abstract":"This brief presents a compact Ka-band bi-directional variable gain phase shifter (BVGPS) using 28-nm CMOS technology. The BVGPS consists of a phase inverting bi-directional variable gain amplifier (PI-BVGA) and 3-bit switched-delay type phase shifter (STPS). The proposed PI-BVGA is implemented with a current cancelling topology for a low phase variation over a gain control range. The PI-BVGA can operate bi-directionally and provide 180° phase shift. Therefore, comparing the conventional BVGPS, this BVGPS achieves a high gain with the compact size since 180° phase shifter and single-pole double-throw (SPDT) switches are eliminated. The average rms phase error over the 16 dB gain control is 1.1° and measured rms phase and gain errors of 16 different phase states are 8.3° and 0.74 dB, respectively, at the center frequency. The maximum gain of the BVGPS is \u0000<inline-formula> <tex-math>$0.7{pm }1$ </tex-math></inline-formula>\u0000.3 dB in the 16 different phase states with a power consumption of 40 mW. The BVGPS occupies 0.21 mm2, excluding the pads.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"133-137"},"PeriodicalIF":4.0,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a balanced power amplifier (BPA) with adaptive-bias for 5G applications based on 28-nm bulk CMOS process. The PA utilizes a differential balanced structure which cancels out reflected signals at the isolation ports, thereby improving return losses. A folded differential quadrature coupler is designed to connect respectively to the input and output of the PAs. The folded layout effectively reduces the chip size. In addition, a complementary adaptive bias is implemented to cancel out the nonlinear effects of the two PAs, significantly enhancing the overall linearity. The measure PA realizes a 3-dB bandwidth of $21.3sim 28$ .4 GHz with a peak gain of 21.1 dB. The large-signal measurement results show that the PA achieve an OP1dB of 20.3 dBm, a $P_{mathrm { sat}}$ of 21.6 dBm, and a peak PAE (PAEmax) of 30.9%. The measured |AM-PM|P1dB is less than 8.9°, which is $3sim 8^{circ }$ lower than when using a normal bias. For 5G NR FR2 200-MHz 64QAM signals, the measured $P_{mathrm { avg}}$ / ${mathrm { PAE}}_{mathrm { avg}}$ / ACPR of 11.2 dBm / 6% / –24.9 dBc are achieved at the EVM of –25 dB. The DC power supply voltage is 1.8 V. The core chip size is only 0.27 mm2, demonstrating a compact design within a balanced architecture.
{"title":"A Balanced Power Amplifier With Complementary Adaptive Bias in 28-nm Bulk CMOS for 5G Millimeter-Wave Systems","authors":"Ning-Zheng Sun;Li Gao;Weisen Zeng;Jie Hu;Xinyang Liu;Xiu Yin Zhang","doi":"10.1109/TCSII.2024.3480706","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3480706","url":null,"abstract":"This brief presents a balanced power amplifier (BPA) with adaptive-bias for 5G applications based on 28-nm bulk CMOS process. The PA utilizes a differential balanced structure which cancels out reflected signals at the isolation ports, thereby improving return losses. A folded differential quadrature coupler is designed to connect respectively to the input and output of the PAs. The folded layout effectively reduces the chip size. In addition, a complementary adaptive bias is implemented to cancel out the nonlinear effects of the two PAs, significantly enhancing the overall linearity. The measure PA realizes a 3-dB bandwidth of \u0000<inline-formula> <tex-math>$21.3sim 28$ </tex-math></inline-formula>\u0000.4 GHz with a peak gain of 21.1 dB. The large-signal measurement results show that the PA achieve an OP1dB of 20.3 dBm, a \u0000<inline-formula> <tex-math>$P_{mathrm { sat}}$ </tex-math></inline-formula>\u0000 of 21.6 dBm, and a peak PAE (PAEmax) of 30.9%. The measured |AM-PM|P1dB is less than 8.9°, which is \u0000<inline-formula> <tex-math>$3sim 8^{circ }$ </tex-math></inline-formula>\u0000 lower than when using a normal bias. For 5G NR FR2 200-MHz 64QAM signals, the measured \u0000<inline-formula> <tex-math>$P_{mathrm { avg}}$ </tex-math></inline-formula>\u0000 / \u0000<inline-formula> <tex-math>${mathrm { PAE}}_{mathrm { avg}}$ </tex-math></inline-formula>\u0000 / ACPR of 11.2 dBm / 6% / –24.9 dBc are achieved at the EVM of –25 dB. The DC power supply voltage is 1.8 V. The core chip size is only 0.27 mm2, demonstrating a compact design within a balanced architecture.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"58-62"},"PeriodicalIF":4.0,"publicationDate":"2024-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-11DOI: 10.1109/TCSII.2024.3478774
Hua Chen;Yuzhong Xiao;Zhenqi Chen;Run Chen;Zhaohui Wu;Bin Li
This brief presents an IEEE 802.15.4z-compliant impulse-radio ultra-wideband (IR-UWB) transmitter for an indoor positioning system. Controlled by the digital baseband, a current-mode digital power amplifier (DPA) generates programmable pulse waveforms, ensuring optimal spectrum utilization and sidelobe suppression. Uniquely, it can directly measure AM-PM distortion caused by non-linear power networks, offering an exclusive compensation method to enhance linearity and elevate in-band spectrum utilization. As a proof-of-concept, a prototype was implemented in a 22-nm FD-SOI process. The measurement result demonstrates that the design can support channels from 6.5 to 10 GHz with 13 dBm peak output power. After calibration, the output spectrum has an in-band spectrum utilization of 81% at peak output power. The chip consumes 33.4 mW at a maximum output power spectral density of −41.3 dBm/MHz.
{"title":"A Digital IR-UWB Transmitter With High Spectrum Utilization and AM-PM Distortion Calibration","authors":"Hua Chen;Yuzhong Xiao;Zhenqi Chen;Run Chen;Zhaohui Wu;Bin Li","doi":"10.1109/TCSII.2024.3478774","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3478774","url":null,"abstract":"This brief presents an IEEE 802.15.4z-compliant impulse-radio ultra-wideband (IR-UWB) transmitter for an indoor positioning system. Controlled by the digital baseband, a current-mode digital power amplifier (DPA) generates programmable pulse waveforms, ensuring optimal spectrum utilization and sidelobe suppression. Uniquely, it can directly measure AM-PM distortion caused by non-linear power networks, offering an exclusive compensation method to enhance linearity and elevate in-band spectrum utilization. As a proof-of-concept, a prototype was implemented in a 22-nm FD-SOI process. The measurement result demonstrates that the design can support channels from 6.5 to 10 GHz with 13 dBm peak output power. After calibration, the output spectrum has an in-band spectrum utilization of 81% at peak output power. The chip consumes 33.4 mW at a maximum output power spectral density of −41.3 dBm/MHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"53-57"},"PeriodicalIF":4.0,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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