Pub Date : 2024-11-20DOI: 10.1109/TCSII.2024.3503363
Marie Andrä;Arkadiusz Dawiec;Rafal Kleczek;Piotr Kmon;Claude Menneglier;Fabienne Orsini;Piotr Otfinowski;Pawel Grybos
A new single photon-counting ASIC prototype called UFERI (Ultra-Fast Energy Resolved Imager) with a matrix of $42times 42$ pixels of $75~mu $ m pitch is developed by the Detector Group of the SOLEIL synchrotron and the Microelectronics Group from AGH University of Krakow, in preparation for the upcoming upgrade of the SOLEIL synchrotron to a fourth-generation facility. The detector is dedicated to pseudo-Laue diffraction applications in intense, pink beams at photon energies between 5 to 30 keV. With its three thresholds and very small offset spread from pixel to pixel of about 1.1 mV, UFERI can discriminate three energy levels while its short dead time ensures a high count rate capability of up to 6 Mcounts/s/pix (10% count rate loss). To keep both, a low noise and a high count rate operation, a front-end amplifier’s feedback capacitor discharge technique is implemented on-chip, enabling high-speed chip operation with an Equivalent Noise Charge (ENC) of 86 e- rms. The UFERI chip can operate with detector signals of both polarities (holes and electrons) and consumes $42~mu $ W/pixel. In this publication, we present a description of the ASIC’s architecture as well as characterization results. The energy calibration, threshold dispersion, gain spread, as well as noise and count rate performance of the UFERI prototype are presented.
{"title":"UFERI—Ultra-Fast Energy Resolved Imager for Next Generation Synchrotron Experiments","authors":"Marie Andrä;Arkadiusz Dawiec;Rafal Kleczek;Piotr Kmon;Claude Menneglier;Fabienne Orsini;Piotr Otfinowski;Pawel Grybos","doi":"10.1109/TCSII.2024.3503363","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3503363","url":null,"abstract":"A new single photon-counting ASIC prototype called UFERI (Ultra-Fast Energy Resolved Imager) with a matrix of \u0000<inline-formula> <tex-math>$42times 42$ </tex-math></inline-formula>\u0000 pixels of \u0000<inline-formula> <tex-math>$75~mu $ </tex-math></inline-formula>\u0000m pitch is developed by the Detector Group of the SOLEIL synchrotron and the Microelectronics Group from AGH University of Krakow, in preparation for the upcoming upgrade of the SOLEIL synchrotron to a fourth-generation facility. The detector is dedicated to pseudo-Laue diffraction applications in intense, pink beams at photon energies between 5 to 30 keV. With its three thresholds and very small offset spread from pixel to pixel of about 1.1 mV, UFERI can discriminate three energy levels while its short dead time ensures a high count rate capability of up to 6 Mcounts/s/pix (10% count rate loss). To keep both, a low noise and a high count rate operation, a front-end amplifier’s feedback capacitor discharge technique is implemented on-chip, enabling high-speed chip operation with an Equivalent Noise Charge (ENC) of 86 e- rms. The UFERI chip can operate with detector signals of both polarities (holes and electrons) and consumes \u0000<inline-formula> <tex-math>$42~mu $ </tex-math></inline-formula>\u0000W/pixel. In this publication, we present a description of the ASIC’s architecture as well as characterization results. The energy calibration, threshold dispersion, gain spread, as well as noise and count rate performance of the UFERI prototype are presented.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"108-112"},"PeriodicalIF":4.0,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10758659","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a high-voltage RF source for trapped-ion quantum computing. It consists of an external transformer and a driver implemented on a single chip. The use of a transformer significantly reduces on-chip current driving requirements to 32mA while delivering a 620-VPP to the output. The proposed architecture also achieves a 20dB improvement in SFDR compared to the previous work. This brief includes a guide for the optimal transformer design that can maximize the output voltage with the minimum power consumption. The proposed design scheme provides a miniaturized implementation of the RF source and makes it promising for scalable quantum computing with multiple RF sources.
{"title":"A 600-V Peak-to-Peak 65-dBc RF Signal Source for Trapped-Ion Quantum Computing","authors":"Seongchan Bae;Myunghun Kim;Junhee Cho;Moonjoo Lee;Jae-Yoon Sim","doi":"10.1109/TCSII.2024.3502802","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3502802","url":null,"abstract":"This brief presents a high-voltage RF source for trapped-ion quantum computing. It consists of an external transformer and a driver implemented on a single chip. The use of a transformer significantly reduces on-chip current driving requirements to 32mA while delivering a 620-VPP to the output. The proposed architecture also achieves a 20dB improvement in SFDR compared to the previous work. This brief includes a guide for the optimal transformer design that can maximize the output voltage with the minimum power consumption. The proposed design scheme provides a miniaturized implementation of the RF source and makes it promising for scalable quantum computing with multiple RF sources.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"103-107"},"PeriodicalIF":4.0,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a 200 MS/s 12 bits cryogenic CMOS (cryo-CMOS) current steering (CS) digital to analog converter (DAC) designed to operate from 300K down to 4 K. The DAC is designed and simulated using a 110nm cryo-CMOS SPICE model, achieving practical performance at 4K. Mismatch in transistor threshold voltage, carrier mobility and layout at cryogenic temperature can lead to unpredictability and incorrect bias voltage, so an off-chip resistor current mirror structure was adopted for the bias circuit. Due to the flexible configuration of the off-chip resistance value and the PMOS current source, this bias structure has certain advantages in overcoming the extended cryogenic nonlinear and mismatch effects to get the correct bias voltage at 4K. This DAC is implemented in a 110nm CMOS process, with a core area < $0.21{mm}^{2}$ . With 9mA full-scale output current, this DAC consumes less than 22mW at 4K. The SFDR achieves 57.94dB, 48.59dB, and 35.33dB at 4.76MHz, 43.67MHz, and 93.47MHz frequency of full swing output, respectively, at 200MS/s and 4K, and the differential and integral nonlinearity are 0.79 LSB and 3.81 LSB, respectively, at 4K.
{"title":"A 200-MS/s 12-b Cryo-CMOS CS DAC for Quantum Computing","authors":"Changchun Zhou;Xuexi He;Bolun Zeng;Jun Xu;Chao Luo;Guoping Guo","doi":"10.1109/TCSII.2024.3502462","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3502462","url":null,"abstract":"This brief presents a 200 MS/s 12 bits cryogenic CMOS (cryo-CMOS) current steering (CS) digital to analog converter (DAC) designed to operate from 300K down to 4 K. The DAC is designed and simulated using a 110nm cryo-CMOS SPICE model, achieving practical performance at 4K. Mismatch in transistor threshold voltage, carrier mobility and layout at cryogenic temperature can lead to unpredictability and incorrect bias voltage, so an off-chip resistor current mirror structure was adopted for the bias circuit. Due to the flexible configuration of the off-chip resistance value and the PMOS current source, this bias structure has certain advantages in overcoming the extended cryogenic nonlinear and mismatch effects to get the correct bias voltage at 4K. This DAC is implemented in a 110nm CMOS process, with a core area <\u0000<inline-formula> <tex-math>$0.21{mm}^{2}$ </tex-math></inline-formula>\u0000. With 9mA full-scale output current, this DAC consumes less than 22mW at 4K. The SFDR achieves 57.94dB, 48.59dB, and 35.33dB at 4.76MHz, 43.67MHz, and 93.47MHz frequency of full swing output, respectively, at 200MS/s and 4K, and the differential and integral nonlinearity are 0.79 LSB and 3.81 LSB, respectively, at 4K.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"98-102"},"PeriodicalIF":4.0,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In compact and cost-constrained IoT low-power applications, the ultra-low-voltage (ULV) on-chip frequency-locked loop (FLL) offers a potential alternative to crystal oscillators while providing high energy efficiency. Compared to open-loop oscillators, the proposed FLL reuses the time-domain amplifier (TDA) as a temperature sensor, allowing the sleep timer to be calibrated with the use of a look-up table (LUT) to further enhance temperature accuracy. A redesigned OTA-accelerated second-order loop filter (LF) addresses the issue of excessive locking time in such low-frequency FLLs. Fabricated in 65-nm CMOS process, the prototype integrated circuit (IC) achieves a temperature coefficient (TC) of 41.7 ppm/°C with calibration based on an LUT and consumes 66.8 nW at 0.4-V supply while producing a 500-kHz frequency.
{"title":"A 0.4-V 500-kHz FLL With Reused TDA-Based Calibration and OTA-Accelerated Technique in 65-nm CMOS for Sleep Timer","authors":"Linwei Wang;Rong Zhou;Jianhang Yang;Zhen Li;Zhicheng Dong;Shubin Liu;Zhangming Zhu","doi":"10.1109/TCSII.2024.3502159","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3502159","url":null,"abstract":"In compact and cost-constrained IoT low-power applications, the ultra-low-voltage (ULV) on-chip frequency-locked loop (FLL) offers a potential alternative to crystal oscillators while providing high energy efficiency. Compared to open-loop oscillators, the proposed FLL reuses the time-domain amplifier (TDA) as a temperature sensor, allowing the sleep timer to be calibrated with the use of a look-up table (LUT) to further enhance temperature accuracy. A redesigned OTA-accelerated second-order loop filter (LF) addresses the issue of excessive locking time in such low-frequency FLLs. Fabricated in 65-nm CMOS process, the prototype integrated circuit (IC) achieves a temperature coefficient (TC) of 41.7 ppm/°C with calibration based on an LUT and consumes 66.8 nW at 0.4-V supply while producing a 500-kHz frequency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"93-97"},"PeriodicalIF":4.0,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-18DOI: 10.1109/TCSII.2024.3501384
Jian Zhang;Ming Zhai;Yichen Liu;Xiangjie Yi;Dawei Wang;Wei Zhu;Yan Wang
This brief presents a broadband bidirectional four-element four-beam beamformer. By utilizing the bidirectional attenuator, and phase shifter, this design achieves a 15.5 dB gain range and a 360° phase-shifting range in both receiver (RX) mode and transmitter (TX) mode. A load state switch is integrated with this design to realize more than 30 dB signal bypass of a certain path while maintaining the input/output matching unchanged to make system-level calibration more convenient. An innovative crossover design with horizontal and vertical ground shielding is proposed to suppress the crosstalk caused by the capacitive couplings at the unavoidable cross intersection in the FC network. The measurement results demonstrate that the proposed beamformer achieves < 0.12/0.26 dB root-mean-square (RMS) amplitude error and < 4.2/3.9° RMS phase error in RX/TX mode at 4.5–7 GHz. To the best of our knowledge, this design is the first broadband multi-beam beamformer that can support both RX and TX modes.
{"title":"A Broadband Bidirectional Four-Element Four-Beam Beamformer With Compact Floorplan in a 65nm CMOS Technology","authors":"Jian Zhang;Ming Zhai;Yichen Liu;Xiangjie Yi;Dawei Wang;Wei Zhu;Yan Wang","doi":"10.1109/TCSII.2024.3501384","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3501384","url":null,"abstract":"This brief presents a broadband bidirectional four-element four-beam beamformer. By utilizing the bidirectional attenuator, and phase shifter, this design achieves a 15.5 dB gain range and a 360° phase-shifting range in both receiver (RX) mode and transmitter (TX) mode. A load state switch is integrated with this design to realize more than 30 dB signal bypass of a certain path while maintaining the input/output matching unchanged to make system-level calibration more convenient. An innovative crossover design with horizontal and vertical ground shielding is proposed to suppress the crosstalk caused by the capacitive couplings at the unavoidable cross intersection in the FC network. The measurement results demonstrate that the proposed beamformer achieves < 0.12/0.26 dB root-mean-square (RMS) amplitude error and < 4.2/3.9° RMS phase error in RX/TX mode at 4.5–7 GHz. To the best of our knowledge, this design is the first broadband multi-beam beamformer that can support both RX and TX modes.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"158-162"},"PeriodicalIF":4.0,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-11DOI: 10.1109/TCSII.2024.3496192
Zhijian Hu;Rong Su;Kai Zhang;Ruiping Wang;Renjie Ma
The increasing penetration of distributed energy resources aggravates the frequency fluctuation of modern power generation systems. In this context, the brief endeavors to propose a frequency estimation method. By simultaneously considering the phasor measurement unit (PMU) and communication link failures and modeling them as independent Bernoulli process, we formulate some linear matrix inequalities-based sufficient conditions, from which the resilient estimation gains capable to ensure the mean-square stability and robust performance of the estimation error system can be automatically selected. Validation results illustrate the superiority of the proposed method over existing ones under different probabilities of PMU and communication link failures.
{"title":"Resilient Frequency Estimation for Renewable Power Generation Against Phasor Measurement Unit and Communication Link Failures","authors":"Zhijian Hu;Rong Su;Kai Zhang;Ruiping Wang;Renjie Ma","doi":"10.1109/TCSII.2024.3496192","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3496192","url":null,"abstract":"The increasing penetration of distributed energy resources aggravates the frequency fluctuation of modern power generation systems. In this context, the brief endeavors to propose a frequency estimation method. By simultaneously considering the phasor measurement unit (PMU) and communication link failures and modeling them as independent Bernoulli process, we formulate some linear matrix inequalities-based sufficient conditions, from which the resilient estimation gains capable to ensure the mean-square stability and robust performance of the estimation error system can be automatically selected. Validation results illustrate the superiority of the proposed method over existing ones under different probabilities of PMU and communication link failures.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"233-237"},"PeriodicalIF":4.0,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief addresses the model-free output feedback (OPFB) stability problem in load frequency control (LFC) of power system and proposes an $H_{infty } $ optimal control scheme considering two-player zero-sum game. Firstly, a novel policy iteration algorithm is developed to determine the optimal control gain. The convergence of this algorithm can be established using Fréchet derivatives. Secondly, a model-free adaptive dynamic programming (ADP) algorithm is introduced, which leverages measured data to learn the optimal gain without relying on model parameters. Finally, simulation results confirm the feasibility of the proposed algorithm.
{"title":"H∞Optimal Load Frequency Control of Power System: A Novel Model-Free Approach","authors":"Shunwei Hu;Yanhong Luo;Xiangpeng Xie;Huaguang Zhang","doi":"10.1109/TCSII.2024.3495679","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3495679","url":null,"abstract":"This brief addresses the model-free output feedback (OPFB) stability problem in load frequency control (LFC) of power system and proposes an \u0000<inline-formula> <tex-math>$H_{infty } $ </tex-math></inline-formula>\u0000 optimal control scheme considering two-player zero-sum game. Firstly, a novel policy iteration algorithm is developed to determine the optimal control gain. The convergence of this algorithm can be established using Fréchet derivatives. Secondly, a model-free adaptive dynamic programming (ADP) algorithm is introduced, which leverages measured data to learn the optimal gain without relying on model parameters. Finally, simulation results confirm the feasibility of the proposed algorithm.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"228-232"},"PeriodicalIF":4.0,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-07DOI: 10.1109/TCSII.2024.3493244
Fan Liu;Hanguang Su;Huaguang Zhang;Ruizhuo Song;Jiawei Wang
In this brief, a novel online near-optimal control scheme is investigated for the voltage tracking control problem of direct current (DC) microgrids under the dynamic self-triggered (DST) mechanism. First, the DC microgrid is modeled as an affine coupled system. The nonzero-sum game issue of the multi-input system is taken into account, where each distributed generator (DG) strives to minimize the individual performance index function and ensure the stability of the whole system. Subsequently, the value function with the non-quadratic utility function is established to seek the optimal constrained control pair. The critic neural network (NN) is devised to approximate the optimal value function. By virtue of experience replay technique, the persistent excitation condition is no more needed. What is more, dynamic event-triggered (DET) control can significantly reduce the waste of computation and communication resources by avoiding the redundant triggers. However, the continuous detection of the DET condition is dependent on dedicated hardware. To overcome the difficulties in hardware realization of DET control, a novel DST method with the dead-zone operation is proposed, in which design the next triggering instant is actively calculated by current data. Besides, the stability of the system and the minimum trigger interval are guaranteed. Finally, a simulation example validates the effectiveness of the algorithm.
{"title":"Dynamic Self-Triggered Adaptive Control for Voltage Regulation of DC Microgrids","authors":"Fan Liu;Hanguang Su;Huaguang Zhang;Ruizhuo Song;Jiawei Wang","doi":"10.1109/TCSII.2024.3493244","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3493244","url":null,"abstract":"In this brief, a novel online near-optimal control scheme is investigated for the voltage tracking control problem of direct current (DC) microgrids under the dynamic self-triggered (DST) mechanism. First, the DC microgrid is modeled as an affine coupled system. The nonzero-sum game issue of the multi-input system is taken into account, where each distributed generator (DG) strives to minimize the individual performance index function and ensure the stability of the whole system. Subsequently, the value function with the non-quadratic utility function is established to seek the optimal constrained control pair. The critic neural network (NN) is devised to approximate the optimal value function. By virtue of experience replay technique, the persistent excitation condition is no more needed. What is more, dynamic event-triggered (DET) control can significantly reduce the waste of computation and communication resources by avoiding the redundant triggers. However, the continuous detection of the DET condition is dependent on dedicated hardware. To overcome the difficulties in hardware realization of DET control, a novel DST method with the dead-zone operation is proposed, in which design the next triggering instant is actively calculated by current data. Besides, the stability of the system and the minimum trigger interval are guaranteed. Finally, a simulation example validates the effectiveness of the algorithm.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"223-227"},"PeriodicalIF":4.0,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-07DOI: 10.1109/TCSII.2024.3494032
Ali Alshawabkeh;Georgios Tzounas;Ángel Molina-García;Federico Milano
This brief discusses the relationships between electrical and affine differential geometry quantities, establishing a link between frequency and time derivatives of voltage, through the utilization of affine geometric invariants. Based on this link, a new instantaneous frequency estimation formula is proposed, which is particularly suited for unbalanced and single-phase systems. Several examples as well as measurements based on two real-world events illustrate the findings of this brief.
{"title":"Instantaneous Frequency Estimation in Unbalanced Systems Using Affine Differential Geometry","authors":"Ali Alshawabkeh;Georgios Tzounas;Ángel Molina-García;Federico Milano","doi":"10.1109/TCSII.2024.3494032","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3494032","url":null,"abstract":"This brief discusses the relationships between electrical and affine differential geometry quantities, establishing a link between frequency and time derivatives of voltage, through the utilization of affine geometric invariants. Based on this link, a new instantaneous frequency estimation formula is proposed, which is particularly suited for unbalanced and single-phase systems. Several examples as well as measurements based on two real-world events illustrate the findings of this brief.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"343-347"},"PeriodicalIF":4.0,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-06DOI: 10.1109/TCSII.2024.3493038
In Cheol Yoo;Dong Ouk Cho;Dong-Woo Kang;Bontae Koo;Chul Woo Byeon
This brief presents the design of a 120 GHz $g_{m}$ -boosting low-noise amplifier (LNA) in 40-nm CMOS. The proposed LNA consists of a single-stage differential $g_{m}$ -boosting common-gate (CG) amplifier and a four-stage differential capacitance-neutralized common-source amplifier. A triple-coupled transformer-based $g_{m}$ -booting technique in the CG stage enhances gain and noise figure (NF) performances. Implemented in 40 nm CMOS, the proposed LNA achieves a measured power gain of 23.8 dB at 123 GHz with a 3-dB bandwidth of 10 GHz. The lowest NF is 5.0 dB at 123 GHz and the NF is below 6.5 dB from 114 to 128 GHz. The LNA consumes 26 mW from a 1-V supply, with a core chip area of 0.25 mm $times 0$ .70 mm.
{"title":"A 120 GHz gm-boosting Low-Noise Amplifier in 40-nm CMOS","authors":"In Cheol Yoo;Dong Ouk Cho;Dong-Woo Kang;Bontae Koo;Chul Woo Byeon","doi":"10.1109/TCSII.2024.3493038","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3493038","url":null,"abstract":"This brief presents the design of a 120 GHz \u0000<inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula>\u0000-boosting low-noise amplifier (LNA) in 40-nm CMOS. The proposed LNA consists of a single-stage differential \u0000<inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula>\u0000-boosting common-gate (CG) amplifier and a four-stage differential capacitance-neutralized common-source amplifier. A triple-coupled transformer-based \u0000<inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula>\u0000-booting technique in the CG stage enhances gain and noise figure (NF) performances. Implemented in 40 nm CMOS, the proposed LNA achieves a measured power gain of 23.8 dB at 123 GHz with a 3-dB bandwidth of 10 GHz. The lowest NF is 5.0 dB at 123 GHz and the NF is below 6.5 dB from 114 to 128 GHz. The LNA consumes 26 mW from a 1-V supply, with a core chip area of 0.25 mm \u0000<inline-formula> <tex-math>$times 0$ </tex-math></inline-formula>\u0000.70 mm.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"153-157"},"PeriodicalIF":4.0,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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