Pub Date : 2025-11-25DOI: 10.1109/TCSII.2025.3632713
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3632713","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3632713","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 12","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11268902","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145595127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-21DOI: 10.1109/TCSII.2025.3635634
Bowen Ding;Ying Song;Lihua Dai;Shuiyang Lin
This article presents a 7-bit high-resolution hybrid vector-modulated (VM) variable gain phase shifter (VGPS) with 1-bit Capacitive Digital-to-Analog Converter (CDAC) in CMOS. Cross-coupled differential common-source pairs are used to form 11-step phase-invariant (PI) variable gain amplifiers (VGAs), ensuring consistent phase and suitable output impedance across varying gain and phase settings. To further improve phase resolution, a 1-bit CDAC is inserted between the coupler-based in-phase and quadrature generator (IQG) and the PI VGA. This integration mitigates typical CDAC drawbacks, such as variations in input/output return loss and sensitivity to VGA load impedance, without introducing phase or gain imbalances in the IQ paths. Measurements show that the proposed VGPS provides a 6 dB gain tuning range and monotonic phase response. It achieves 7-bit phase resolution over 70-85 GHz, with a root-mean-square (RMS) phase error less than 3° and RMS gain error of 0.5 dB. The circuit consumes 30 mW from a 0.9 V supply and occupies a compact core area of $425~mu $ m $times 320~mu $ m.
本文介绍了一种7位高分辨率混合矢量调制（VM）可变增益移相器（VGPS），该移相器具有1位电容式数模转换器（CDAC）。交叉耦合差分共源对用于形成11步相位不变（PI）变增益放大器（VGAs），确保在不同增益和相位设置下相位一致和合适的输出阻抗。为了进一步提高相位分辨率，在基于耦合器的同相和正交发生器（IQG）和PI VGA之间插入1位CDAC。这种集成减轻了典型的CDAC缺点，例如输入/输出返回损耗的变化和对VGA负载阻抗的灵敏度，而不会在IQ路径中引入相位或增益不平衡。测量结果表明，所提出的VGPS具有6 dB增益调谐范围和单调相位响应。在70-85 GHz范围内实现7位相位分辨率，均方根（RMS）相位误差小于3°，RMS增益误差为0.5 dB。该电路从0.9 V的电源消耗30 mW，并占用紧凑的核心面积$425~mu $ m $ × 320~mu $ m $ m。
{"title":"A 7-bit 76–81-GHz Hybrid Vector-Modulated Variable Gain Phase Shifter Combining Phase-Invariant VGA and 1-bit CDAC","authors":"Bowen Ding;Ying Song;Lihua Dai;Shuiyang Lin","doi":"10.1109/TCSII.2025.3635634","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3635634","url":null,"abstract":"This article presents a 7-bit high-resolution hybrid vector-modulated (VM) variable gain phase shifter (VGPS) with 1-bit Capacitive Digital-to-Analog Converter (CDAC) in CMOS. Cross-coupled differential common-source pairs are used to form 11-step phase-invariant (PI) variable gain amplifiers (VGAs), ensuring consistent phase and suitable output impedance across varying gain and phase settings. To further improve phase resolution, a 1-bit CDAC is inserted between the coupler-based in-phase and quadrature generator (IQG) and the PI VGA. This integration mitigates typical CDAC drawbacks, such as variations in input/output return loss and sensitivity to VGA load impedance, without introducing phase or gain imbalances in the IQ paths. Measurements show that the proposed VGPS provides a 6 dB gain tuning range and monotonic phase response. It achieves 7-bit phase resolution over 70-85 GHz, with a root-mean-square (RMS) phase error less than 3° and RMS gain error of 0.5 dB. The circuit consumes 30 mW from a 0.9 V supply and occupies a compact core area of <inline-formula> <tex-math>$425~mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$times 320~mu $ </tex-math></inline-formula>m.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"28-32"},"PeriodicalIF":4.9,"publicationDate":"2025-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a high-linearity third-order 3-bit continuous-time delta-sigma modulator (CTDSM) with 109 dB spurious-free dynamic range (SFDR) for audio applications. The proposed modulator employs a cascade of integrators with feedforward structure using active RC integrators, a 3-bit flash quantizer, and resistor digital-to-analog converter (DAC) feedback. To address both DAC non-linearity and the tonal issues caused by conventional data weighted averaging (DWA), a new bi-directional advancing DWA (Bi-ADWA) with tone-suppressing and tone-transferring capabilities is introduced. Furthermore, the asymmetry in the rise/fall time of the DAC due to the additional paths introduced by Bi-ADWA is mitigated by optimizing the switch control circuitry and layout of the feedback DAC. Fabricated in a 180 nm CMOS technology, the modulator demonstrates a peak SNDR of 95.8 dB alongside a DR of 102.5 dB, consuming 0.58 mW at 1.8 V within an active area of 0.8 mm2.
{"title":"A 109-dB SFDR Continuous-Time Delta-Sigma Modulator for Audio Using Bi-Directional Advancing Data Weighted Averaging","authors":"Aoyun Sun;Lingling Wei;Hong Yang;Gang Liu;Zhang Zhang","doi":"10.1109/TCSII.2025.3635133","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3635133","url":null,"abstract":"This brief presents a high-linearity third-order 3-bit continuous-time delta-sigma modulator (CTDSM) with 109 dB spurious-free dynamic range (SFDR) for audio applications. The proposed modulator employs a cascade of integrators with feedforward structure using active RC integrators, a 3-bit flash quantizer, and resistor digital-to-analog converter (DAC) feedback. To address both DAC non-linearity and the tonal issues caused by conventional data weighted averaging (DWA), a new bi-directional advancing DWA (Bi-ADWA) with tone-suppressing and tone-transferring capabilities is introduced. Furthermore, the asymmetry in the rise/fall time of the DAC due to the additional paths introduced by Bi-ADWA is mitigated by optimizing the switch control circuitry and layout of the feedback DAC. Fabricated in a 180 nm CMOS technology, the modulator demonstrates a peak SNDR of 95.8 dB alongside a <italic>DR</i> of 102.5 dB, consuming 0.58 mW at 1.8 V within an active area of 0.8 mm<sup>2</sup>.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"23-27"},"PeriodicalIF":4.9,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-19DOI: 10.1109/TCSII.2025.3634589
Yan Yu;Deng Luo;Ming Tao;Jianjun Chen;Yaqing Chi;Guofang Yu;Jingtian Liu;Bin Liang
This brief presents a fractional output divider (FOD) with a foreground digital-to-time converter (DTC) INL calibration scheme. This calibration scheme adjusts the delay control words of two main DTCs (mDTCs) to enable mutual comparison between them. By using a sign-least-mean-squares (sign-LMS) algorithm, the INL error codes are obtained and subsequently applied to a calibration DTC (cDTC) to compensate for the mDTC INL. The prototype occupies a compact core area of 0.01mm2 and operates at a 0.9V supply with a power consumption of 3.6mW at 500MHz. Measurements demonstrate an integrated jitter of 512fs (10kHz to 20MHz) and spur level of -70dBc at 123.46MHz.
{"title":"An Area-Efficient Fractional Output Divider Based on Foreground DTC INL Calibration","authors":"Yan Yu;Deng Luo;Ming Tao;Jianjun Chen;Yaqing Chi;Guofang Yu;Jingtian Liu;Bin Liang","doi":"10.1109/TCSII.2025.3634589","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3634589","url":null,"abstract":"This brief presents a fractional output divider (FOD) with a foreground digital-to-time converter (DTC) INL calibration scheme. This calibration scheme adjusts the delay control words of two main DTCs (mDTCs) to enable mutual comparison between them. By using a sign-least-mean-squares (sign-LMS) algorithm, the INL error codes are obtained and subsequently applied to a calibration DTC (cDTC) to compensate for the mDTC INL. The prototype occupies a compact core area of 0.01mm<sup>2</sup> and operates at a 0.9V supply with a power consumption of 3.6mW at 500MHz. Measurements demonstrate an integrated jitter of 512fs (10kHz to 20MHz) and spur level of -70dBc at 123.46MHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"18-22"},"PeriodicalIF":4.9,"publicationDate":"2025-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-17DOI: 10.1109/TCSII.2025.3633654
Zhihao Guo;Xiaohui Qu;Cheng Li;Yundi Li;Jinghang Liu;Chi K. Tse
Unilateral compensation offers a promising solution for the compact and lightweight design of wireless power transfer systems. Inspired by unilateral compensated inductive power transfer (IPT) converters designed from the generalized transformer model, this brief proposes a generalized capacitive coupler model for capacitive power transfer (CPT) converters. By introducing an additional design freedom, the proposed model offers more flexible compensation network design than traditional T- or $boldsymbol {Pi }$ -type model, while establishing a unified analytical framework. Subsequently, a family of unilateral compensation networks is readily derived on the basis of this model, with advantages of near unity power factor, flexible load-independent constant-voltage (CV) or -current (CC) output, soft switching and so on. Finally, a 100 W CPT prototype with LLL-None(N) unilateral network is built to verify the analysis.
{"title":"A Novel Generalized Capacitive Coupler Model With Application to Unilateral Compensated Capacitive Power Transfer Systems","authors":"Zhihao Guo;Xiaohui Qu;Cheng Li;Yundi Li;Jinghang Liu;Chi K. Tse","doi":"10.1109/TCSII.2025.3633654","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3633654","url":null,"abstract":"Unilateral compensation offers a promising solution for the compact and lightweight design of wireless power transfer systems. Inspired by unilateral compensated inductive power transfer (IPT) converters designed from the generalized transformer model, this brief proposes a generalized capacitive coupler model for capacitive power transfer (CPT) converters. By introducing an additional design freedom, the proposed model offers more flexible compensation network design than traditional T- or <inline-formula> <tex-math>$boldsymbol {Pi }$ </tex-math></inline-formula>-type model, while establishing a unified analytical framework. Subsequently, a family of unilateral compensation networks is readily derived on the basis of this model, with advantages of near unity power factor, flexible load-independent constant-voltage (CV) or -current (CC) output, soft switching and so on. Finally, a 100 W CPT prototype with LLL-None(N) unilateral network is built to verify the analysis.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"98-102"},"PeriodicalIF":4.9,"publicationDate":"2025-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1109/TCSII.2025.3633245
Dongjun Lee;Bona Lim;Yonghwa Kwon;Jaeduk Han
This brief presents a single-channel 8-bit time-domain analog-to-digital converter (TD-ADC) that employs a selection-first successive approximation register (SAR) time-to-digital converter (TDC) to address key limitations of prior TDC designs used in TD-ADCs. By adopting the selection-first approach, each bit decision requires only one reference delay path per bit, improving metastability tolerance compared to conventional computation-first designs. Moreover, the proposed TDC eliminates input-dependent errors and reduces the vulnerability to time-comparator mismatches observed in gate-based TDCs. Fabricated in 28-nm CMOS technology, the prototype TD-ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 36.4 dB for a Nyquist-rate input at 6 GS/s while consuming 51 mW.
{"title":"A 6-GS/s 8-bit Time-Domain ADC With Selection-First Pipelined Successive Approximation Register TDC in 28-nm CMOS Technology","authors":"Dongjun Lee;Bona Lim;Yonghwa Kwon;Jaeduk Han","doi":"10.1109/TCSII.2025.3633245","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3633245","url":null,"abstract":"This brief presents a single-channel 8-bit time-domain analog-to-digital converter (TD-ADC) that employs a selection-first successive approximation register (SAR) time-to-digital converter (TDC) to address key limitations of prior TDC designs used in TD-ADCs. By adopting the selection-first approach, each bit decision requires only one reference delay path per bit, improving metastability tolerance compared to conventional computation-first designs. Moreover, the proposed TDC eliminates input-dependent errors and reduces the vulnerability to time-comparator mismatches observed in gate-based TDCs. Fabricated in 28-nm CMOS technology, the prototype TD-ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 36.4 dB for a Nyquist-rate input at 6 GS/s while consuming 51 mW.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"13-17"},"PeriodicalIF":4.9,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1109/TCSII.2025.3633181
Moonis Amir Zaman;Muhammad Bilal Khan;Waqar Ahmad;Ayesha Khalid;Máire O'Neill
The Number Theoretic Transform (NTT) and its inverse (INTT) are pivotal operations in Fully Homomorphic Encryption (FHE) schemes to facilitate efficient polynomial multiplication over modular rings. We propose a compact and hardware-efficient NTT/INTT architecture for FHE systems with a novel twiddle factor generator (TFG) for Radix-2 multi-path delay commutator (MDC) designs, saving up to 97.2% of on-chip memory by storing the twiddle factors (TF) for the initial 11 stages (for $log _{2}(N)=15$ to 17) and only the TF bases for on-the-fly generation in the remaining stages. DSP-efficient multipliers via non-standard tiling are designed to reduce DSP utilization as compared to standard tiling, without sacrificing performance. Benchmarking on comparable Xilinx FPGAs reveals that our design is the most compact, along with a significant efficiency advantage with up to $2.72times $ reduction in average area-time product (ATP) and up to $2.57times $ increase in throughput-per-equivalent-LUT (TPE) compared to state-of-the-art NTT designs. In various configurations, the architecture maintains lower BRAM and DSP utilization, and better overall efficiency, making it a scalable and efficient solution for real-world FHE deployments.
{"title":"A Lightweight and Hardware-Efficient NTT FPGA Accelerator for FHE Applications","authors":"Moonis Amir Zaman;Muhammad Bilal Khan;Waqar Ahmad;Ayesha Khalid;Máire O'Neill","doi":"10.1109/TCSII.2025.3633181","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3633181","url":null,"abstract":"The Number Theoretic Transform (NTT) and its inverse (INTT) are pivotal operations in Fully Homomorphic Encryption (FHE) schemes to facilitate efficient polynomial multiplication over modular rings. We propose a compact and hardware-efficient NTT/INTT architecture for FHE systems with a novel twiddle factor generator (TFG) for Radix-2 multi-path delay commutator (MDC) designs, saving up to 97.2% of on-chip memory by storing the twiddle factors (TF) for the initial 11 stages (for <inline-formula> <tex-math>$log _{2}(N)=15$ </tex-math></inline-formula> to 17) and only the TF bases for on-the-fly generation in the remaining stages. DSP-efficient multipliers via non-standard tiling are designed to reduce DSP utilization as compared to standard tiling, without sacrificing performance. Benchmarking on comparable Xilinx FPGAs reveals that our design is the most compact, along with a significant efficiency advantage with up to <inline-formula> <tex-math>$2.72times $ </tex-math></inline-formula> reduction in average area-time product (ATP) and up to <inline-formula> <tex-math>$2.57times $ </tex-math></inline-formula> increase in throughput-per-equivalent-LUT (TPE) compared to state-of-the-art NTT designs. In various configurations, the architecture maintains lower BRAM and DSP utilization, and better overall efficiency, making it a scalable and efficient solution for real-world FHE deployments.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"78-82"},"PeriodicalIF":4.9,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1109/TCSII.2025.3632858
Yinuo Su;Jingchao Zhang;Liyan Qiao
This brief proposes a joint error information theoretic criterion (JET) assisted blind calibration method for multichannel compressive sampling systems under complete blindness. Addressing gain-phase errors and mutual coupling, we first estimate these errors, then leverage an information theoretic criterion (ITC) to estimate signal sparsity, enabling blind calibration and signal reconstruction. An optimal ITC penalty term is derived through joint error model analysis. Simulation and hardware experiments validate the method’s effectiveness. Simulation experiments and hardware experiments confirm that our method achieves over 99.9% accuracy in sparsity estimation within the range [0-0.5] of gain-phase errors and mutual coupling errors.
{"title":"JET: Joint Error Information Theoretic Criterion for Multichannel Compressive Sampling Systems","authors":"Yinuo Su;Jingchao Zhang;Liyan Qiao","doi":"10.1109/TCSII.2025.3632858","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3632858","url":null,"abstract":"This brief proposes a joint error information theoretic criterion (JET) assisted blind calibration method for multichannel compressive sampling systems under complete blindness. Addressing gain-phase errors and mutual coupling, we first estimate these errors, then leverage an information theoretic criterion (ITC) to estimate signal sparsity, enabling blind calibration and signal reconstruction. An optimal ITC penalty term is derived through joint error model analysis. Simulation and hardware experiments validate the method’s effectiveness. Simulation experiments and hardware experiments confirm that our method achieves over 99.9% accuracy in sparsity estimation within the range [0-0.5] of gain-phase errors and mutual coupling errors.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"103-107"},"PeriodicalIF":4.9,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-13DOI: 10.1109/TCSII.2025.3632254
Long Wang;Jiarun Xu;Fayu Wan;Xiaohe Chen;Nathan B. Gurgel;Lagouge Tartibu;Dmitry Kholodnyak;Glauco Fontgalland;Blaise Ravelo
Miniaturization remains a critical challenge for Negative Group Delay (NGD) circuit design. This brief presents an inductorless bandpass (BP) NGD integrated circuit (IC) designed based on an RC-topology leveraging 180-nm complementary metal-oxide-semiconductor (CMOS) technology. The schematic and layout of the BP-NGD CMOS IC prototype are designed with CADENCE VIRTUOSO (Registered trademark.) commercial tool. The compact BP-NGD chip area is 1.06 mm $times 0.55$ mm. The key performance metrics include a center frequency of 18.67 MHz, an NGD of -0.91 ns, a bandwidth of 74.31 MHz, a maximum insertion loss of -3.86 dB, and a minimum return loss of -11.04 dB. The results demonstrate that the IC design effectively balances miniaturization with high-performance NGD characteristics, providing a promising solution for NGD integration in system-on-chip (SoC) applications.
{"title":"Experimentation of Bandpass NGD Inductorless Integrated Circuit Designed With 180-nm CMOS Technology RC-Network","authors":"Long Wang;Jiarun Xu;Fayu Wan;Xiaohe Chen;Nathan B. Gurgel;Lagouge Tartibu;Dmitry Kholodnyak;Glauco Fontgalland;Blaise Ravelo","doi":"10.1109/TCSII.2025.3632254","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3632254","url":null,"abstract":"Miniaturization remains a critical challenge for Negative Group Delay (NGD) circuit design. This brief presents an inductorless bandpass (BP) NGD integrated circuit (IC) designed based on an RC-topology leveraging 180-nm complementary metal-oxide-semiconductor (CMOS) technology. The schematic and layout of the BP-NGD CMOS IC prototype are designed with CADENCE VIRTUOSO (Registered trademark.) commercial tool. The compact BP-NGD chip area is 1.06 mm <inline-formula> <tex-math>$times 0.55$ </tex-math></inline-formula> mm. The key performance metrics include a center frequency of 18.67 MHz, an NGD of -0.91 ns, a bandwidth of 74.31 MHz, a maximum insertion loss of -3.86 dB, and a minimum return loss of -11.04 dB. The results demonstrate that the IC design effectively balances miniaturization with high-performance NGD characteristics, providing a promising solution for NGD integration in system-on-chip (SoC) applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"63-67"},"PeriodicalIF":4.9,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this brief, a frequency synchronization method for time-based-controlled power converters is presented. The proposed synchronization technique makes it possible to precisely lock the internal oscillators frequency of the time-based controller (i.e., the power converter switching frequency) to any externally provided clock signal, without trading the dynamic performance. By leveraging the differential structure of the time-based controller, the proposed feedback loop operates orthogonally with respect to the main voltage regulation loop, minimizing any interaction with the latter. The presented frequency synchronization scheme has been implemented on a time-based buck converter in a 180-nm BCD process to fully verify the performance.
{"title":"Frequency Synchronization Techniques for DC–DC Converters With Time-Based Control","authors":"Alessandro Bertolini;Paolo Melillo;Mauro Leoncini;Alessandro Gasparini;Salvatore Levantino;Massimo Ghioni","doi":"10.1109/TCSII.2025.3632634","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3632634","url":null,"abstract":"In this brief, a frequency synchronization method for time-based-controlled power converters is presented. The proposed synchronization technique makes it possible to precisely lock the internal oscillators frequency of the time-based controller (i.e., the power converter switching frequency) to any externally provided clock signal, without trading the dynamic performance. By leveraging the differential structure of the time-based controller, the proposed feedback loop operates orthogonally with respect to the main voltage regulation loop, minimizing any interaction with the latter. The presented frequency synchronization scheme has been implemented on a time-based buck converter in a 180-nm BCD process to fully verify the performance.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"93-97"},"PeriodicalIF":4.9,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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