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Time-Elapsed-Reliant Observer-Based Control of Semi-Markov Jump Linear Systems With Bilaterally Bounded Sojourn Time
IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-11-04 DOI: 10.1109/TCSII.2024.3491032
Yongxiao Tian;Zepeng Ning;Huaicheng Yan;Yan Peng
This brief focuses on the observer-based output-feedback (OBOF) control of discrete-time semi-Markov jump linear systems (SMJLSs) with bilateral bounds of sojourn time. To lessen the conservatism in OBOF controller design, we develop a decoupling technique that facilitates the simultaneous design of the time-elapsed-reliant observer and controller, which also alleviates the computational burden. Following this approach, mean-square stability analysis and OBOF control synthesis are implemented for SMJLSs by resorting to semi-Markov kernel within an equivalent closed-loop augmented system. The theoretical results are validated through an electromagnetic oscillation circuit to elucidate the efficacy and practical utility of the proposed control methodology.
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引用次数: 0
An On-Chip AC Coupled AFE With Asymmetric Output Stage for d-ToF LiDAR
IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-11-04 DOI: 10.1109/TCSII.2024.3489640
Yuye Yang;Hao Feng;Zhenyu Yin;Shuaizhe Ma;Jia Li;Xinyin Shan;Yifei Xia;Ruixuan Yang;Bing Zhang;Li Geng;Dan Li
In this brief, an on-chip AC coupled analog front-end circuit with asymmetric output stage is proposed for a pulsed direct time-of-flight LiDAR receiver. The AFE employs a novel on-chip AC coupled scheme for APD cathode bias voltage tuning in a cost-effective manner. A reverse current cancellation circuit helps the circuit recover rapidly under large input current. A transimpedance amplifier is designed for low noise which is desirable to process weak signals. An asymmetric output stage doubles the output swing under the same bias current compared to conventional current mode logic topology. This prototype chip is fabricated in a standard 180 nm CMOS process and the measurement results shows bandwidth, gain, input-referred noise current of 151 MHz, 102 dB $Omega $ , and 3.51 pA/ $surd $ Hz, respectively. The maximum differential output swing reaches $1.8~rm V_{textrm {pp,diff}}$ based on both electrical and optical measurement setup.
{"title":"An On-Chip AC Coupled AFE With Asymmetric Output Stage for d-ToF LiDAR","authors":"Yuye Yang;Hao Feng;Zhenyu Yin;Shuaizhe Ma;Jia Li;Xinyin Shan;Yifei Xia;Ruixuan Yang;Bing Zhang;Li Geng;Dan Li","doi":"10.1109/TCSII.2024.3489640","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3489640","url":null,"abstract":"In this brief, an on-chip AC coupled analog front-end circuit with asymmetric output stage is proposed for a pulsed direct time-of-flight LiDAR receiver. The AFE employs a novel on-chip AC coupled scheme for APD cathode bias voltage tuning in a cost-effective manner. A reverse current cancellation circuit helps the circuit recover rapidly under large input current. A transimpedance amplifier is designed for low noise which is desirable to process weak signals. An asymmetric output stage doubles the output swing under the same bias current compared to conventional current mode logic topology. This prototype chip is fabricated in a standard 180 nm CMOS process and the measurement results shows bandwidth, gain, input-referred noise current of 151 MHz, 102 dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, and 3.51 pA/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000 Hz, respectively. The maximum differential output swing reaches \u0000<inline-formula> <tex-math>$1.8~rm V_{textrm {pp,diff}}$ </tex-math></inline-formula>\u0000 based on both electrical and optical measurement setup.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"148-152"},"PeriodicalIF":4.0,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference
IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-30 DOI: 10.1109/TCSII.2024.3488526
Zhengqing Zhong;Haibing Wang;Mingju Chen;Yingcheng Lin;Min Tian;Tengxiao Wang;Liyuan Liu;Cong Shi
Neuromorphic processors are promising candidates for energy-constrained intelligent systems, as they emulate cortical computations via spatiotemporally sparse binary spikes. However, achieving high-accuracy, high-throughput and cost-efficient neuromorphic processing remains challenging. To fully utilize hardware resources for performance improvement, we propose a multi-core neuromorphic architecture characteristic of a uniform neuron-core mapping scheme and a layer-wise event-batch-based parallel processing paradigm. These techniques ensure highly balanced cross-core workloads regardless of actual mapped neural network topologies as well as unpredictable input and internally generated spike counts varying from sample to sample. An FPGA prototype of our neuromorphic processor was implemented. It exhibited comparably high on-chip learning accuracies on various visual and non-visual benchmarks, high learning/inference frame rates (low processing latencies), with a moderate amount of logic and memory resource consumptions.
{"title":"MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference","authors":"Zhengqing Zhong;Haibing Wang;Mingju Chen;Yingcheng Lin;Min Tian;Tengxiao Wang;Liyuan Liu;Cong Shi","doi":"10.1109/TCSII.2024.3488526","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3488526","url":null,"abstract":"Neuromorphic processors are promising candidates for energy-constrained intelligent systems, as they emulate cortical computations via spatiotemporally sparse binary spikes. However, achieving high-accuracy, high-throughput and cost-efficient neuromorphic processing remains challenging. To fully utilize hardware resources for performance improvement, we propose a multi-core neuromorphic architecture characteristic of a uniform neuron-core mapping scheme and a layer-wise event-batch-based parallel processing paradigm. These techniques ensure highly balanced cross-core workloads regardless of actual mapped neural network topologies as well as unpredictable input and internally generated spike counts varying from sample to sample. An FPGA prototype of our neuromorphic processor was implemented. It exhibited comparably high on-chip learning accuracies on various visual and non-visual benchmarks, high learning/inference frame rates (low processing latencies), with a moderate amount of logic and memory resource consumptions.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"293-297"},"PeriodicalIF":4.0,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Circuits and Systems Society Information 电气和电子工程师学会电路与系统协会信息
IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-29 DOI: 10.1109/TCSII.2024.3477193
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3477193","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3477193","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10738135","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information 电气和电子工程师学会电路与系统论文集--II:特快摘要》出版信息
IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-29 DOI: 10.1109/TCSII.2024.3477191
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3477191","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3477191","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10738009","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Guest Editorial Special Issue on the 2024 ISICAS: A CAS Journal Track Symposium 2024 年国际科学与应用科学会议特邀编辑特刊:中国科学院期刊专题讨论会
IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-29 DOI: 10.1109/TCSII.2024.3467908
Antonio Liscidini
{"title":"Guest Editorial Special Issue on the 2024 ISICAS: A CAS Journal Track Symposium","authors":"Antonio Liscidini","doi":"10.1109/TCSII.2024.3467908","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3467908","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4607-4607"},"PeriodicalIF":4.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10738013","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reachable Set Estimation of Inertial Complex-Valued Memristive Neural Networks
IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-28 DOI: 10.1109/TCSII.2024.3486746
Jiemei Zhao;Yi Shen;Leimin Wang;Liqi Yu
This brief investigates the reachable set estimation (RSE) of inertial complex-valued memristive neural networks (ICVMNNs) with bounded disturbances. By taking into account the analysis method and inequality technique, an algebraic criterion of RES is established. To deal with the inertial terms in memristive neural networks, a nonreduced-order approach is adopted. Besides, the non-separation analysis method is applied to investigate complex-valued problems. Then, a complex-valued feedback control scheme is designed to ensure that the states of ICVMNNs converge to a bounded region. Eventually, a numerical example is provided to illustrate the effectiveness of the obtained theoretical result.
{"title":"Reachable Set Estimation of Inertial Complex-Valued Memristive Neural Networks","authors":"Jiemei Zhao;Yi Shen;Leimin Wang;Liqi Yu","doi":"10.1109/TCSII.2024.3486746","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3486746","url":null,"abstract":"This brief investigates the reachable set estimation (RSE) of inertial complex-valued memristive neural networks (ICVMNNs) with bounded disturbances. By taking into account the analysis method and inequality technique, an algebraic criterion of RES is established. To deal with the inertial terms in memristive neural networks, a nonreduced-order approach is adopted. Besides, the non-separation analysis method is applied to investigate complex-valued problems. Then, a complex-valued feedback control scheme is designed to ensure that the states of ICVMNNs converge to a bounded region. Eventually, a numerical example is provided to illustrate the effectiveness of the obtained theoretical result.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"213-217"},"PeriodicalIF":4.0,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Efficient Brain-Inspired Accelerator Using a High-Accuracy Conversion Algorithm for Spiking Deformable CNN
IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-28 DOI: 10.1109/TCSII.2024.3487266
Haonan Zhang;Siyu Zhang;Wendong Mao;Zhongfeng Wang
Spiking Neural Network (SNN), inspired by the brain, has shown promising potential in terms of low-power deployment on resource-constrained devices. The SNN can be obtained by two approaches: training from scratch or conversion from existing Artificial Neural Network (ANN). However, the directly training SNN often leads to suboptimal accuracy. Therefore, methods based on converting existing ANN have become the preferred choice for achieving high accuracy. To enhance the feature-capturing capability of the converted SNNs, various operations, such as transposed convolution and deformable convolution, have been introduced, which bring multiple challenges to conversion algorithms and hardware designs. In this brief, we propose a universal SNN conversion method for deformable convolution to enhance the modeling capability of receptive fields for spatial information. The proposed conversion algorithm not only maintains high accuracy but also makes converted deformable convolutions highly hardware-efficient. Building upon the deformable SNN, we develop a low-complexity processing element and computing array, enabling flexible execution of complex and heterogeneous operations within deformable SNNs without requiring any multipliers. In addition, the overall architecture with energy-efficient dataflow is designed for our deformable SNN model and is implemented in TSMC 28-nm HPC+ technology node. Experiments show that the proposed conversion algorithm suffers negligible accuracy degradation in the challenging object detection task. The accelerator achieves at least $1.2times $ higher energy efficiency compared to previous designs while maintaining 47.9% mAP.
{"title":"An Efficient Brain-Inspired Accelerator Using a High-Accuracy Conversion Algorithm for Spiking Deformable CNN","authors":"Haonan Zhang;Siyu Zhang;Wendong Mao;Zhongfeng Wang","doi":"10.1109/TCSII.2024.3487266","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3487266","url":null,"abstract":"Spiking Neural Network (SNN), inspired by the brain, has shown promising potential in terms of low-power deployment on resource-constrained devices. The SNN can be obtained by two approaches: training from scratch or conversion from existing Artificial Neural Network (ANN). However, the directly training SNN often leads to suboptimal accuracy. Therefore, methods based on converting existing ANN have become the preferred choice for achieving high accuracy. To enhance the feature-capturing capability of the converted SNNs, various operations, such as transposed convolution and deformable convolution, have been introduced, which bring multiple challenges to conversion algorithms and hardware designs. In this brief, we propose a universal SNN conversion method for deformable convolution to enhance the modeling capability of receptive fields for spatial information. The proposed conversion algorithm not only maintains high accuracy but also makes converted deformable convolutions highly hardware-efficient. Building upon the deformable SNN, we develop a low-complexity processing element and computing array, enabling flexible execution of complex and heterogeneous operations within deformable SNNs without requiring any multipliers. In addition, the overall architecture with energy-efficient dataflow is designed for our deformable SNN model and is implemented in TSMC 28-nm HPC+ technology node. Experiments show that the proposed conversion algorithm suffers negligible accuracy degradation in the challenging object detection task. The accelerator achieves at least \u0000<inline-formula> <tex-math>$1.2times $ </tex-math></inline-formula>\u0000 higher energy efficiency compared to previous designs while maintaining 47.9% mAP.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"288-292"},"PeriodicalIF":4.0,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An X-Band 7-Bit High Resolution and Ultra-Low Amplitude Variations Phase Shifter With Current Correction Technique
IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-25 DOI: 10.1109/TCSII.2024.3486569
Dongwei Pang;Jun Wang;Zongming Duan
In this brief, an X-band 7-bit digital-controlled vector-sum phase shifter (VSPS) with high resolution and ultra-low amplitude variations is presented. The 7-bit digital-to-analog converter (DAC) incorporating 2-bit quadrant control bits is employed to adjust the amplitude of In-phase/Quadrature (I/Q) signals, and synthesizing the desired phase, which achieves a minimum step control of 2.8125° within a full 360° range. Moreover, a current correction technique is proposed to address the challenges of degraded phase shifting accuracy caused by excessive phase stepping at quadrant intersections, as well as large amplitude variations due to the nonlinear change of transconductance with the square root of bias current. The VSPS, implemented in 130-nm CMOS technology, shows outstanding phase accuracy with the root mean square (rms) error of less than 0.93°, while the rms amplitude error is less than 0.16 dB over the frequency range of 8 to 12 GHz.
{"title":"An X-Band 7-Bit High Resolution and Ultra-Low Amplitude Variations Phase Shifter With Current Correction Technique","authors":"Dongwei Pang;Jun Wang;Zongming Duan","doi":"10.1109/TCSII.2024.3486569","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3486569","url":null,"abstract":"In this brief, an X-band 7-bit digital-controlled vector-sum phase shifter (VSPS) with high resolution and ultra-low amplitude variations is presented. The 7-bit digital-to-analog converter (DAC) incorporating 2-bit quadrant control bits is employed to adjust the amplitude of In-phase/Quadrature (I/Q) signals, and synthesizing the desired phase, which achieves a minimum step control of 2.8125° within a full 360° range. Moreover, a current correction technique is proposed to address the challenges of degraded phase shifting accuracy caused by excessive phase stepping at quadrant intersections, as well as large amplitude variations due to the nonlinear change of transconductance with the square root of bias current. The VSPS, implemented in 130-nm CMOS technology, shows outstanding phase accuracy with the root mean square (rms) error of less than 0.93°, while the rms amplitude error is less than 0.16 dB over the frequency range of 8 to 12 GHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"88-92"},"PeriodicalIF":4.0,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 12-V Input 0.3 V-to-0.6 V Output Imbalanced Inductor-Currents Converter That Achieves a Peak Efficiency of 90.7%
IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-10-25 DOI: 10.1109/TCSII.2024.3486362
Chan-Ho Lee;Jeong-Hun Kim;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong
This brief proposed an imbalanced inductor-current buck (IIB) converter. The proposed IIB converter has two inductor current paths. The IIB converter provides majority of the load current through a current path composed of low voltage transistors and minority of the load current through the current path composed of high voltage transistors, which becomes further as voltage conversion ratio decreases. Therefore, the IIB converter reduces conduction loss as the voltage conversion ratio decreases, which is considerably important in low voltage applications. In addition, since this converter uses a flying capacitor network behind the inductor, it is invulnerable to the input voltage variation. The proposed converter has peak efficiencies of 90.7% at ${mathrm { V}}_{mathrm { IN}} {=} 12$ V, ${mathrm { V}}_{mathrm { O}} {=} 0.6$ V, and 85.6% at ${mathrm { V}}_{mathrm { IN}} {=} 12$ V, ${mathrm { V}}_{mathrm { O}} {=} 0.3$ V. The chip was fabricated in 130-nm BCD process with an area of 6.177 mm2.
{"title":"A 12-V Input 0.3 V-to-0.6 V Output Imbalanced Inductor-Currents Converter That Achieves a Peak Efficiency of 90.7%","authors":"Chan-Ho Lee;Jeong-Hun Kim;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong","doi":"10.1109/TCSII.2024.3486362","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3486362","url":null,"abstract":"This brief proposed an imbalanced inductor-current buck (IIB) converter. The proposed IIB converter has two inductor current paths. The IIB converter provides majority of the load current through a current path composed of low voltage transistors and minority of the load current through the current path composed of high voltage transistors, which becomes further as voltage conversion ratio decreases. Therefore, the IIB converter reduces conduction loss as the voltage conversion ratio decreases, which is considerably important in low voltage applications. In addition, since this converter uses a flying capacitor network behind the inductor, it is invulnerable to the input voltage variation. The proposed converter has peak efficiencies of 90.7% at \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { IN}} {=} 12$ </tex-math></inline-formula>\u0000 V, \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { O}} {=} 0.6$ </tex-math></inline-formula>\u0000 V, and 85.6% at \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { IN}} {=} 12$ </tex-math></inline-formula>\u0000 V, \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { O}} {=} 0.3$ </tex-math></inline-formula>\u0000 V. The chip was fabricated in 130-nm BCD process with an area of 6.177 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"338-342"},"PeriodicalIF":4.0,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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