Pub Date : 2025-11-11DOI: 10.1109/TCSII.2025.3631479
Maximilian Froitzheim;Florian Protze;Franz Alwin Dürrwald;Ronny Henker;Frank Ellinger
This work investigates the concept and design of optical-duobinary vertical-cavity-surface-emitting-laser transmitters. Duobinary modulation exhibits significant advantages compared to conventional non-return-to-zero modulation.We present a novel concept: an optical duobinary transmitter. The usually problematic low bandwidth of the laser is exploited to directly generate the duobinary signal in the optical domain. For proper encoding the frequency response of the laser and the driver circuit have to match the frequency response of a duobinary encoder. Our encoderless concept does not need multilevel driver circuits or equalizers to achieve the desired high data rates. A suitable transmitter integrated circuit was designed in an advanced SiGe bipolar CMOS technology. Optical measurements show good transmission performance and efficiency at 60 GBit/s. The achieved data rate is triple the bandwidth of the laser, which is remarkable compared to the state of the art.
{"title":"A 60 Gbit/s Integrated Encoderless Duobinary VCSEL-Driver","authors":"Maximilian Froitzheim;Florian Protze;Franz Alwin Dürrwald;Ronny Henker;Frank Ellinger","doi":"10.1109/TCSII.2025.3631479","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3631479","url":null,"abstract":"This work investigates the concept and design of optical-duobinary vertical-cavity-surface-emitting-laser transmitters. Duobinary modulation exhibits significant advantages compared to conventional non-return-to-zero modulation.We present a novel concept: an optical duobinary transmitter. The usually problematic low bandwidth of the laser is exploited to directly generate the duobinary signal in the optical domain. For proper encoding the frequency response of the laser and the driver circuit have to match the frequency response of a duobinary encoder. Our encoderless concept does not need multilevel driver circuits or equalizers to achieve the desired high data rates. A suitable transmitter integrated circuit was designed in an advanced SiGe bipolar CMOS technology. Optical measurements show good transmission performance and efficiency at 60 GBit/s. The achieved data rate is triple the bandwidth of the laser, which is remarkable compared to the state of the art.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"58-62"},"PeriodicalIF":4.9,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-11DOI: 10.1109/TCSII.2025.3631512
Guibin Zou;Yuan Dai;Wenbo Yin;Lingli Wang
As a core component of logarithmic number systems, this brief proposes a constraint-driven automated parameter exploration framework for the logarithmic converter circuit. The framework innovatively integrates two optimization algorithms, including the Intercept Compensation and Error-Flattening Non-Uniform Segmentation Scheme for high-precision implementations and the Unity-Slope Piecewise Linear Approximation for low-precision implementations that require less hardware overhead. Employing constraint-driven automated exploration of adder count, segment count, error-redundancy factor, and segment-point bit-width, optimal parameters are selected for an optimized logarithmic converter implementation. Experimental results demonstrate that compared to state-of-the-art designs with identical maximum absolute error constraints, the proposed circuits achieve superior area (up to 62.7% reduction), power (up to 62.4% reduction), and delay (up to 29.9% reduction), yielding 7.3%–88.5% improvements in the comprehensive error-area-delay-power (eADP) metric.
{"title":"Toward Efficient Logarithmic Converter Circuit Design via Constraint-Driven Parameter Exploration","authors":"Guibin Zou;Yuan Dai;Wenbo Yin;Lingli Wang","doi":"10.1109/TCSII.2025.3631512","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3631512","url":null,"abstract":"As a core component of logarithmic number systems, this brief proposes a constraint-driven automated parameter exploration framework for the logarithmic converter circuit. The framework innovatively integrates two optimization algorithms, including the Intercept Compensation and Error-Flattening Non-Uniform Segmentation Scheme for high-precision implementations and the Unity-Slope Piecewise Linear Approximation for low-precision implementations that require less hardware overhead. Employing constraint-driven automated exploration of adder count, segment count, error-redundancy factor, and segment-point bit-width, optimal parameters are selected for an optimized logarithmic converter implementation. Experimental results demonstrate that compared to state-of-the-art designs with identical maximum absolute error constraints, the proposed circuits achieve superior area (up to 62.7% reduction), power (up to 62.4% reduction), and delay (up to 29.9% reduction), yielding 7.3%–88.5% improvements in the comprehensive error-area-delay-power (eADP) metric.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"83-87"},"PeriodicalIF":4.9,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-10DOI: 10.1109/TCSII.2025.3630821
Luyao Zhang;Haolin Wang;Wanrun Xia;Tong Guo;Yao Mao
This brief investigates the disturbance rejection control problem for discrete systems with time-varying delays using a scaled gain-based extended state observer (SGESO). Based on the two-term approximation of $x(k-tau (k))$ , a modified extended state observer and input compensation are designed to obtain estimates of the system state and disturbances, where the input compensation is used to compensate for the impact of time delays. Then, a model transformation is employed to transform the closed-loop system into a delay-free interconnected form. Moreover, a delay-dependent condition is provided in terms of linear matrix inequalities (LMIs) to ensure the stability property. Finally, the application to photoelectric tracking systems on an experimental platform was considered, and the experimental results verified the superiority of the SGESO-based anti-disturbance control method.
{"title":"Scaled Gain-Based Extended State Observer for Disturbed Systems With Time-Varying Delays","authors":"Luyao Zhang;Haolin Wang;Wanrun Xia;Tong Guo;Yao Mao","doi":"10.1109/TCSII.2025.3630821","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3630821","url":null,"abstract":"This brief investigates the disturbance rejection control problem for discrete systems with time-varying delays using a scaled gain-based extended state observer (SGESO). Based on the two-term approximation of <inline-formula> <tex-math>$x(k-tau (k))$ </tex-math></inline-formula>, a modified extended state observer and input compensation are designed to obtain estimates of the system state and disturbances, where the input compensation is used to compensate for the impact of time delays. Then, a model transformation is employed to transform the closed-loop system into a delay-free interconnected form. Moreover, a delay-dependent condition is provided in terms of linear matrix inequalities (LMIs) to ensure the stability property. Finally, the application to photoelectric tracking systems on an experimental platform was considered, and the experimental results verified the superiority of the SGESO-based anti-disturbance control method.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"68-72"},"PeriodicalIF":4.9,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a fully dynamic discrete-time (DT) $2^{text {nd}}$ -order delta-sigma ($Delta Sigma $ ) ADC using a gain-switched floating inverter amplifier (FIA) with correlated level shifting (CLS) and sampling noise cancellation (SNC). The proposed FIA realizes stable open-loop gains in both low-gain and high-gain modes while maintaining high power efficiency. This leads to a stable sampling noise cancellation when employed in the SNC. The measurement results demonstrate that the proposed ADC achieves 93.4 dB signal-to-noise ratio (SNR) and 91.8 dB signal-to-noise-and-distortion ratio (SNDR) for a 24 kHz bandwidth while consuming 87.7 $mu $ W from a 1.2V supply at a 10 MHz sampling frequency, resulting in a FoMS of 176.2 dB. The SNR is improved by 2.7 dB with SNC.
{"title":"A 91.8-dB SNDR 24-kHz BW Discrete-Time ΔΣ ADC Employing Gain-Switched FIA With Sampling Noise Cancellation","authors":"Ximing Wang;Yuyang Zhu;Haoming Zhang;Yunjie Chen;Jiaao Yu;Sota Kano;Ritaro Takenaka;Shuowei Li;Tomohiro Nezuka;Yoshikazu Furuta;Tetsuya Iizuka","doi":"10.1109/TCSII.2025.3630610","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3630610","url":null,"abstract":"This brief presents a fully dynamic discrete-time (DT) <inline-formula> <tex-math>$2^{text {nd}}$ </tex-math></inline-formula>-order delta-sigma (<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>) ADC using a gain-switched floating inverter amplifier (FIA) with correlated level shifting (CLS) and sampling noise cancellation (SNC). The proposed FIA realizes stable open-loop gains in both low-gain and high-gain modes while maintaining high power efficiency. This leads to a stable sampling noise cancellation when employed in the SNC. The measurement results demonstrate that the proposed ADC achieves 93.4 dB signal-to-noise ratio (SNR) and 91.8 dB signal-to-noise-and-distortion ratio (SNDR) for a 24 kHz bandwidth while consuming 87.7 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W from a 1.2V supply at a 10 MHz sampling frequency, resulting in a FoM<sub>S</sub> of 176.2 dB. The SNR is improved by 2.7 dB with SNC.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"8-12"},"PeriodicalIF":4.9,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11236471","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-07DOI: 10.1109/TCSII.2025.3630506
Yaehoon Roh;Gyeore Lee;Donggu Im
This work presents a sub-GHz (400 MHz $sim ~950$ MHz) wideband CMOS receiver front-end with a 49 dB gain range and constant output-referred third-order intercept point (OIP3) across gain reduction, implemented in a 130-nm CMOS process for IoT applications. To enhance loop gain and improve the noise figure (NF) while achieving wideband input impedance matching, the differential outputs from the single-to-differential (S2D) converter are converted into a single-ended signal using a voltage-subtractor-based differential-to-single (D2S) buffer. This single-ended signal is then fed back to the input of the S2D converter through a feedback resistor. Additionally, two separate gain paths are implemented by employing two optimized S2D converters, one designed for low noise and the other for high linearity, to enable gain control while maintaining a nearly constant output 1 dB compression point (OP1dB) and OIP3. In particular, when very strong signals are received, the feedback path is disabled, and a pi-attenuator is activated in front of the S2D converter optimized for high linearity, in order to attenuate the signal while keeping a constant input impedance. A current-mode passive mixer with a transimpedance amplifier (TIA) is adopted to maintain low impedance and reduce the voltage swing at the mixer output, thereby enhancing linearity. In the measurement, the proposed receiver front-end shows an average conversion gain of 50.5 dB, NF of 3.3 dB, and OIP3 of + 24.3 dBm at high gain mode over the operating frequency band. In addition, it achieves a gain range of 49 dB with nearly constant OIP3. The current consumption is 12.4 mA from a 1.2 V supply.
{"title":"A Sub-GHz Wideband CMOS Receiver Front-End With 49 dB Gain Range and Constant OIP3 Across Gain Reduction","authors":"Yaehoon Roh;Gyeore Lee;Donggu Im","doi":"10.1109/TCSII.2025.3630506","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3630506","url":null,"abstract":"This work presents a sub-GHz (400 MHz <inline-formula> <tex-math>$sim ~950$ </tex-math></inline-formula> MHz) wideband CMOS receiver front-end with a 49 dB gain range and constant output-referred third-order intercept point (OIP3) across gain reduction, implemented in a 130-nm CMOS process for IoT applications. To enhance loop gain and improve the noise figure (NF) while achieving wideband input impedance matching, the differential outputs from the single-to-differential (S2D) converter are converted into a single-ended signal using a voltage-subtractor-based differential-to-single (D2S) buffer. This single-ended signal is then fed back to the input of the S2D converter through a feedback resistor. Additionally, two separate gain paths are implemented by employing two optimized S2D converters, one designed for low noise and the other for high linearity, to enable gain control while maintaining a nearly constant output 1 dB compression point (OP1dB) and OIP3. In particular, when very strong signals are received, the feedback path is disabled, and a pi-attenuator is activated in front of the S2D converter optimized for high linearity, in order to attenuate the signal while keeping a constant input impedance. A current-mode passive mixer with a transimpedance amplifier (TIA) is adopted to maintain low impedance and reduce the voltage swing at the mixer output, thereby enhancing linearity. In the measurement, the proposed receiver front-end shows an average conversion gain of 50.5 dB, NF of 3.3 dB, and OIP3 of + 24.3 dBm at high gain mode over the operating frequency band. In addition, it achieves a gain range of 49 dB with nearly constant OIP3. The current consumption is 12.4 mA from a 1.2 V supply.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"53-57"},"PeriodicalIF":4.9,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1109/TCSII.2025.3621997
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3621997","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3621997","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11230157","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145442728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1109/TCSII.2025.3629413
Le Chen;Jinwei Zhang;Shubin Liu;Haolin Han
This brief presents a digital background calibration technique that uses a split-least-significant-bit (Split-LSB) weight to simultaneously address both capacitor mismatch and gain nonlinearity in pipelined successive approximation register analog-to-digital converters (SAR ADCs). The key innovation of this approach lies in the use of sub-LSB weights, derived from splitting the LSB capacitor, to detect and correct nonlinearity. By integrating 1-bit dynamic element matching (DEM) with a separate-averaging algorithm, this technique achieves the first offset-immune background calibration capable of calibrating both error sources simultaneously. Behavioral simulations of a 14-bit pipelined SAR ADC show significant performance improvements: the signal-to-noise-and-distortion ratio (SNDR) increases from 52.4 dB to 84.2 dB, and the spurious-free dynamic range (SFDR) rises from 56.3 dB to 104.5 dB. These results validate the effectiveness of the proposed technique.
{"title":"Offset-Immune Split-LSB Weight Calibration for Capacitor Mismatch and Gain Nonlinearity in Pipelined SAR ADC","authors":"Le Chen;Jinwei Zhang;Shubin Liu;Haolin Han","doi":"10.1109/TCSII.2025.3629413","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3629413","url":null,"abstract":"This brief presents a digital background calibration technique that uses a split-least-significant-bit (Split-LSB) weight to simultaneously address both capacitor mismatch and gain nonlinearity in pipelined successive approximation register analog-to-digital converters (SAR ADCs). The key innovation of this approach lies in the use of sub-LSB weights, derived from splitting the LSB capacitor, to detect and correct nonlinearity. By integrating 1-bit dynamic element matching (DEM) with a separate-averaging algorithm, this technique achieves the first offset-immune background calibration capable of calibrating both error sources simultaneously. Behavioral simulations of a 14-bit pipelined SAR ADC show significant performance improvements: the signal-to-noise-and-distortion ratio (SNDR) increases from 52.4 dB to 84.2 dB, and the spurious-free dynamic range (SFDR) rises from 56.3 dB to 104.5 dB. These results validate the effectiveness of the proposed technique.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"3-7"},"PeriodicalIF":4.9,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1109/TCSII.2025.3611062
Antonio Liscidini
{"title":"Guest Editorial Special Issue on the 2025 ISICAS: A CAS Journal Track Symposium","authors":"Antonio Liscidini","doi":"10.1109/TCSII.2025.3611062","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3611062","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"1479-1479"},"PeriodicalIF":4.9,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11230207","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145442727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1109/TCSII.2025.3621999
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3621999","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3621999","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 11","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11230146","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145442729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-04DOI: 10.1109/TCSII.2025.3629098
Youming Zhang;Fengyi Huang;Xusheng Tang;Zhennan Wei;Yunqi Cao;Zhengyang Li;Yan Liu
This brief presents a full-band multi-mode reconfigurable CMOS transceiver (TRX) covering TDD/FDD 3GPP/WLAN, candidate 6G and WiFi 7 (5.925–7.125 GHz) frequency bands. A novel multi-mode architecture is proposed in the receiver (RX) chain, which supports reconfigurable low-noise (LN) and high-linearity (HL) operations with the RX chain reused for feedback observation (FBO). The RX achieves a noise figure of $2.0-5.4$ dB in the LN mode, an IP1dB of −4.6 dBm and an IIP3 of +5.3 dBm in the HL mode. In the TX chain, a modified RFATT integrated with a symmetrical passive resistor network (SPRN) is utilized to achieve high precision, large dynamic power control and high linearity. The TX achieves >92 dB TX power control range with 0.25-dB step, 62.0 dBc ACLR, −66.1 dBc IRR, and −38.8 dB EVM at 40-MHz 256QAM 802.11ac signal. The LO generation chain incorporates a quadrature error correction circuit with a single VCO of 67% tuning range, exhibiting a phase noise of −128.2 dBc/Hz @1MHz (with 2.1 GHz carrier). Powered by 1.2/2.5-V supplies, the $3.54times 2.75$ mm2 TRX circuit consumes 0.25 W/0.4 W in TDD/FDD modes. The present chip provides a fully reconfigurable solution for any carrier frequency from 50 MHz to 7 GHz with an instantaneous RF bandwidth of 110 MHz, with major performances comparable to the prior arts without resorting to digital calibration circuits.
{"title":"A Full-Band Reconfigurable CMOS Transceiver in the 50 MHz-to-7 GHz Frequency Range","authors":"Youming Zhang;Fengyi Huang;Xusheng Tang;Zhennan Wei;Yunqi Cao;Zhengyang Li;Yan Liu","doi":"10.1109/TCSII.2025.3629098","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3629098","url":null,"abstract":"This brief presents a full-band multi-mode reconfigurable CMOS transceiver (TRX) covering TDD/FDD 3GPP/WLAN, candidate 6G and WiFi 7 (5.925–7.125 GHz) frequency bands. A novel multi-mode architecture is proposed in the receiver (RX) chain, which supports reconfigurable low-noise (LN) and high-linearity (HL) operations with the RX chain reused for feedback observation (FBO). The RX achieves a noise figure of <inline-formula> <tex-math>$2.0-5.4$ </tex-math></inline-formula> dB in the LN mode, an IP1dB of −4.6 dBm and an IIP3 of +5.3 dBm in the HL mode. In the TX chain, a modified RFATT integrated with a symmetrical passive resistor network (SPRN) is utilized to achieve high precision, large dynamic power control and high linearity. The TX achieves >92 dB TX power control range with 0.25-dB step, 62.0 dBc ACLR, −66.1 dBc IRR, and −38.8 dB EVM at 40-MHz 256QAM 802.11ac signal. The LO generation chain incorporates a quadrature error correction circuit with a single VCO of 67% tuning range, exhibiting a phase noise of −128.2 dBc/Hz @1MHz (with 2.1 GHz carrier). Powered by 1.2/2.5-V supplies, the <inline-formula> <tex-math>$3.54times 2.75$ </tex-math></inline-formula> mm<sup>2</sup> TRX circuit consumes 0.25 W/0.4 W in TDD/FDD modes. The present chip provides a fully reconfigurable solution for any carrier frequency from 50 MHz to 7 GHz with an instantaneous RF bandwidth of 110 MHz, with major performances comparable to the prior arts without resorting to digital calibration circuits.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"48-52"},"PeriodicalIF":4.9,"publicationDate":"2025-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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