In this study, we proposed an enhanced mode P-GaN/AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) by combining thermal oxidation treatment of P-GaN with atomic layer deposition (OTALD) prior to gate metal deposition. Due to the thermal oxidation treatment, a smooth oxide interlayer between P-GaN and Al $_{mathbf {{2}}}$ O $_{mathbf {{3}}}$ is formed. Compared with the device without treatment, the P-GaN gate HEMTs with OTALD present increased threshold voltage significantly from 1.8 V to 7.1 V and improved gate breakdown voltage from 18.9 V to 26.9 V. Additionally, the devices maintained a high on/off current ratio above $10^{mathbf {{8}}}$ and a further improvement in off-state breakdown voltage from 1315 V to 1980 V. The record high threshold voltage and breakdown voltage make this technology promising for widespread application in P-GaN power devices.
{"title":"High Breakdown Voltage P-GaN Gate HEMTs With Threshold Voltage of 7.1 V","authors":"Siheng Chen;Peng Cui;Xin Luo;Liu Wang;Jiacheng Dai;Kaifa Qi;Tieying Zhang;Handoko Linewih;Zhaojun Lin;Xiangang Xu;Jisheng Han","doi":"10.1109/LED.2024.3478819","DOIUrl":"https://doi.org/10.1109/LED.2024.3478819","url":null,"abstract":"In this study, we proposed an enhanced mode P-GaN/AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) by combining thermal oxidation treatment of P-GaN with atomic layer deposition (OTALD) prior to gate metal deposition. Due to the thermal oxidation treatment, a smooth oxide interlayer between P-GaN and Al\u0000<inline-formula> <tex-math>$_{mathbf {{2}}}$ </tex-math></inline-formula>\u0000O\u0000<inline-formula> <tex-math>$_{mathbf {{3}}}$ </tex-math></inline-formula>\u0000 is formed. Compared with the device without treatment, the P-GaN gate HEMTs with OTALD present increased threshold voltage significantly from 1.8 V to 7.1 V and improved gate breakdown voltage from 18.9 V to 26.9 V. Additionally, the devices maintained a high on/off current ratio above \u0000<inline-formula> <tex-math>$10^{mathbf {{8}}}$ </tex-math></inline-formula>\u0000 and a further improvement in off-state breakdown voltage from 1315 V to 1980 V. The record high threshold voltage and breakdown voltage make this technology promising for widespread application in P-GaN power devices.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2343-2346"},"PeriodicalIF":4.1,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142761444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1109/LED.2024.3477605
Yifei Huang;Qimeng Jiang;Yixu Yao;Sen Huang;Xinhua Wang;Xinyu Liu
Dynamic ${E}_{text {OSS}}$ of Schottky p-GaN gate GaN devices is investigated by a proposed novel circuit. The easy-to-implement circuit allows for the analysis of dynamic ${E}_{text {OSS}}$ under different stress types, varied stress times and temperatures. It is observed that, the ${E}_{text {OSS}}$ is significantly reduced when the device is under continuous hard-switching stress (HSW) compared to devices subjected to OFF-state high voltage drain stress (HDC) and fresh devices, especially under relatively low bus voltage conditions (e.g., 100 V). These findings, linked to the dynamic change of 2DEG, provide new insights into Schottky p-GaN gate HEMT behavior and application understanding.
{"title":"Investigation of Dynamic Eₒₛₛ in p-GaN Gate AlGaN/GaN HEMT","authors":"Yifei Huang;Qimeng Jiang;Yixu Yao;Sen Huang;Xinhua Wang;Xinyu Liu","doi":"10.1109/LED.2024.3477605","DOIUrl":"https://doi.org/10.1109/LED.2024.3477605","url":null,"abstract":"Dynamic \u0000<inline-formula> <tex-math>${E}_{text {OSS}}$ </tex-math></inline-formula>\u0000 of Schottky p-GaN gate GaN devices is investigated by a proposed novel circuit. The easy-to-implement circuit allows for the analysis of dynamic \u0000<inline-formula> <tex-math>${E}_{text {OSS}}$ </tex-math></inline-formula>\u0000 under different stress types, varied stress times and temperatures. It is observed that, the \u0000<inline-formula> <tex-math>${E}_{text {OSS}}$ </tex-math></inline-formula>\u0000 is significantly reduced when the device is under continuous hard-switching stress (HSW) compared to devices subjected to OFF-state high voltage drain stress (HDC) and fresh devices, especially under relatively low bus voltage conditions (e.g., 100 V). These findings, linked to the dynamic change of 2DEG, provide new insights into Schottky p-GaN gate HEMT behavior and application understanding.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2339-2342"},"PeriodicalIF":4.1,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142761495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Plasma treatment has been extensively employed for doping or etching organic semiconductors. Both doping and etching effects occur simultaneously during the plasma treatment. Polymer semiconductors, which contain both crystalline and amorphous phases, exhibit inherent selective etching characteristics. However, the combined effects of doping and selective etching on the electrical properties of polymer semiconductors have not been thoroughly investigated. In this study, we examine the influence of plasma treatment on the surface morphology and electrical properties of organic field-effect transistors utilizing the polymer semiconductor DPP-DTT. A competitive effect between doping and trap formation is observed during plasma treatment, resulting in controllable bidirectional shifts in threshold voltage with acceptable mobility degradation. Under optimal plasma treatment conditions, a 3.45-fold increase in the current response and improved recovery performance were observed in NO2 gas sensing applications, attributed to the formation of trap and the pore structure from selective etching. These results highlight the significant potential of plasma treatment for optimizing polymer-based organic transistors.
{"title":"Competing Effects of Doping and Trap Formation in Polymer Semiconductors During Plasma Treatment","authors":"Hongquan Yu;Zhenyuan Tang;Min Tu;Yangjiang Wu;Kaihuan Zhang","doi":"10.1109/LED.2024.3477598","DOIUrl":"https://doi.org/10.1109/LED.2024.3477598","url":null,"abstract":"Plasma treatment has been extensively employed for doping or etching organic semiconductors. Both doping and etching effects occur simultaneously during the plasma treatment. Polymer semiconductors, which contain both crystalline and amorphous phases, exhibit inherent selective etching characteristics. However, the combined effects of doping and selective etching on the electrical properties of polymer semiconductors have not been thoroughly investigated. In this study, we examine the influence of plasma treatment on the surface morphology and electrical properties of organic field-effect transistors utilizing the polymer semiconductor DPP-DTT. A competitive effect between doping and trap formation is observed during plasma treatment, resulting in controllable bidirectional shifts in threshold voltage with acceptable mobility degradation. Under optimal plasma treatment conditions, a 3.45-fold increase in the current response and improved recovery performance were observed in NO2 gas sensing applications, attributed to the formation of trap and the pore structure from selective etching. These results highlight the significant potential of plasma treatment for optimizing polymer-based organic transistors.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2506-2509"},"PeriodicalIF":4.1,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142753890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, the cause of the poor uniformity in indium tungsten oxide (IWO) thin-film transistors (TFTs) is investigated. The significant fluctuation in tungsten (W) content, which results from the non-uniformity of the IWO target, is responsible. To solve this problem, RF magnetron co-sputtering of In2O3 and WO3 targets is adopted to eliminate the variation of W content, thereby achieving high-uniformity IWO TFTs with enhanced performance. This co-sputtering methodology could shed light on the pathways for mitigating the device uniformity challenges encountered in mass production settings, thus leading to substantial cost reductions.
{"title":"Enhancement of Device Uniformity in IWO TFTs via RF Magnetron Co-Sputtering of In2O3 and WO3 Targets","authors":"Zihan Wang;Feilian Chen;Mingjun Zhang;Xiaoliang Zhou;Paramasivam Balasubramanian;Yan Yan;Meng Zhang","doi":"10.1109/LED.2024.3477443","DOIUrl":"https://doi.org/10.1109/LED.2024.3477443","url":null,"abstract":"In this letter, the cause of the poor uniformity in indium tungsten oxide (IWO) thin-film transistors (TFTs) is investigated. The significant fluctuation in tungsten (W) content, which results from the non-uniformity of the IWO target, is responsible. To solve this problem, RF magnetron co-sputtering of In2O3 and WO3 targets is adopted to eliminate the variation of W content, thereby achieving high-uniformity IWO TFTs with enhanced performance. This co-sputtering methodology could shed light on the pathways for mitigating the device uniformity challenges encountered in mass production settings, thus leading to substantial cost reductions.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2423-2426"},"PeriodicalIF":4.1,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1109/LED.2024.3477434
James L. Doherty;Ye Zhang;Brittany N. Smith;Hansel Alex Hobbie;Ioannis Kymissis;Aaron D. Franklin
We report the first demonstration of displays driven by embedded transistors that were additively manufactured entirely by aerosol jet printing. The backplanes of the liquid crystal displays (LCDs) consist of transistors printed from graphene, carbon nanotubes, and crystalline nanocellulose onto a glass substrate with prepatterned indium tin oxide electrodes. We addressed challenges of integrating fully printed devices into both the crossbar array structure and layered vertical structure required for an LCD, showing successful pixel switching at up to 60 Hz. As these thin-film transistors are printed exclusively from carbon-based recyclable materials, without high temperatures or vacuum processing, they offer a promising means for reducing waste in future display technologies.
{"title":"Liquid Crystal Displays With Printed Carbon-Based Recyclable Transistor Backplanes","authors":"James L. Doherty;Ye Zhang;Brittany N. Smith;Hansel Alex Hobbie;Ioannis Kymissis;Aaron D. Franklin","doi":"10.1109/LED.2024.3477434","DOIUrl":"https://doi.org/10.1109/LED.2024.3477434","url":null,"abstract":"We report the first demonstration of displays driven by embedded transistors that were additively manufactured entirely by aerosol jet printing. The backplanes of the liquid crystal displays (LCDs) consist of transistors printed from graphene, carbon nanotubes, and crystalline nanocellulose onto a glass substrate with prepatterned indium tin oxide electrodes. We addressed challenges of integrating fully printed devices into both the crossbar array structure and layered vertical structure required for an LCD, showing successful pixel switching at up to 60 Hz. As these thin-film transistors are printed exclusively from carbon-based recyclable materials, without high temperatures or vacuum processing, they offer a promising means for reducing waste in future display technologies.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2427-2430"},"PeriodicalIF":4.1,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1109/LED.2024.3477747
Jayatika Sakhuja;Udayan Ganguly;Sandip Lashkare
Low voltage (<1V) bi-directional and symmetric electrostatic discharge (ESD) protection devices are essential for system level ESD protection of low voltage electronics such Low voltage GPIO for MCU, Sub-20nm I/O’s, and potentially for next gen interfaces USB3.2 Gen2, Thunderbolt 4. Here, a triangular barrier designed Silicon NIPIN (n+ -i-p+ -i-n+) punch-through diode with variable voltage <0.5V to 2V is proposed for low-voltage system level ESD protection. The NIPIN diode utilizes the sub-bandgap voltage impact ionization to enable the ultra-low voltage breakdown. The control over the breakdown voltage is demonstrated via TCAD simulations by controlling the lengths of intrinsic, and p+ -doped regions and the doping of p+ -doped region. Finally, standoff voltage and clamping voltages are compared with other low voltage protection devices and demonstrate near ideal voltage performance of the NIPIN protection device. Such a low voltage ESD protection with low clamping voltage is a critical development for low-voltage electronics.
{"title":"Low Voltage NIPIN Symmetric and Bi-Directional Diode for System Level ESD Protection","authors":"Jayatika Sakhuja;Udayan Ganguly;Sandip Lashkare","doi":"10.1109/LED.2024.3477747","DOIUrl":"https://doi.org/10.1109/LED.2024.3477747","url":null,"abstract":"Low voltage (<1V) bi-directional and symmetric electrostatic discharge (ESD) protection devices are essential for system level ESD protection of low voltage electronics such Low voltage GPIO for MCU, Sub-20nm I/O’s, and potentially for next gen interfaces USB3.2 Gen2, Thunderbolt 4. Here, a triangular barrier designed Silicon NIPIN (n+ -i-p+ -i-n+) punch-through diode with variable voltage <0.5V to 2V is proposed for low-voltage system level ESD protection. The NIPIN diode utilizes the sub-bandgap voltage impact ionization to enable the ultra-low voltage breakdown. The control over the breakdown voltage is demonstrated via TCAD simulations by controlling the lengths of intrinsic, and p+ -doped regions and the doping of p+ -doped region. Finally, standoff voltage and clamping voltages are compared with other low voltage protection devices and demonstrate near ideal voltage performance of the NIPIN protection device. Such a low voltage ESD protection with low clamping voltage is a critical development for low-voltage electronics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2483-2486"},"PeriodicalIF":4.1,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142754246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1109/LED.2024.3477430
Jiajin Kuang;Rong Liu;Wenbo Cao;Yang Wang;Chong Chen;Junwei Chen;Mingtai Wang
Indium copper sulfide (CuInS $_{{2}}text {)}$ has attracted considerable attention as an efficient and stable photon-absorbing material for inorganic heterojunction solar cells. Hole transport layer (HTL), serving as a hole extracting material, plays an integral role in determining device performance of solar cells. Here, the high-quality CuSCN film has been prepared successfully by using green mixed solution (dimethyl sulfoxide and dipropyl sulfide) and employed firstly to fabricate efficient CuInS2 planar heterojunction (PHJ) solar cells. The morphology, absorption properties, crystallinity and crystal orientation of CuSCN film are investigated by scanning electron microscopy (SEM), ultraviolet-visible spectroscopy (UV-vis) and X-ray diffraction (XRD) techniques. Results show the CuSCN film layer ( ${T}_{c} = 100~^{text {o}}$ C) suggests good crystallinity and superior transmittance. The champion CuInS2 PHJ solar cell with inorganic CuSCN HTM achieves an inspiring power conversion efficiency ( $eta text {)}$ of 5.0% with the highest fill factor (FF) of 65.66% in the similar photovoltaic devices.
{"title":"Solution-Processed CuSCN Films With Low Toxic and Environmentally Friendly Solvent for Efficient All-Inorganic CuInS₂ Solar Cells","authors":"Jiajin Kuang;Rong Liu;Wenbo Cao;Yang Wang;Chong Chen;Junwei Chen;Mingtai Wang","doi":"10.1109/LED.2024.3477430","DOIUrl":"https://doi.org/10.1109/LED.2024.3477430","url":null,"abstract":"Indium copper sulfide (CuInS\u0000<inline-formula> <tex-math>$_{{2}}text {)}$ </tex-math></inline-formula>\u0000 has attracted considerable attention as an efficient and stable photon-absorbing material for inorganic heterojunction solar cells. Hole transport layer (HTL), serving as a hole extracting material, plays an integral role in determining device performance of solar cells. Here, the high-quality CuSCN film has been prepared successfully by using green mixed solution (dimethyl sulfoxide and dipropyl sulfide) and employed firstly to fabricate efficient CuInS2 planar heterojunction (PHJ) solar cells. The morphology, absorption properties, crystallinity and crystal orientation of CuSCN film are investigated by scanning electron microscopy (SEM), ultraviolet-visible spectroscopy (UV-vis) and X-ray diffraction (XRD) techniques. Results show the CuSCN film layer (\u0000<inline-formula> <tex-math>${T}_{c} = 100~^{text {o}}$ </tex-math></inline-formula>\u0000C) suggests good crystallinity and superior transmittance. The champion CuInS2 PHJ solar cell with inorganic CuSCN HTM achieves an inspiring power conversion efficiency (\u0000<inline-formula> <tex-math>$eta text {)}$ </tex-math></inline-formula>\u0000 of 5.0% with the highest fill factor (FF) of 65.66% in the similar photovoltaic devices.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2307-2310"},"PeriodicalIF":4.1,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142761408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1109/LED.2024.3478073
Bazila Parvez;Akhil S. Kumar;James W. Pomeroy;Matthew D. Smith;Robert S. Howell;Martin Kuball
A electroluminescence (EL) based methodology has been devised to screen AlGaN/GaN Super-Lattice Castellated Field Effect Transistors (SLCFETs). EL intensity captured during off-state stressing has been correlated with an increase in gate leakage current after stress. Two off-state constant-voltage stress conditions were used, both applied over a stress time ( ${mathrm {t}}_{text {stress}}$ ) of 90 seconds: (a) ${mathrm{V}}_{text {GS}} = -12$ V, ${mathrm{V}}_{text {DS}} = 12$ V, and (b) ${mathrm{V}}_{text {GS}} = -12$ V, ${mathrm{V}}_{text {DS}} = 14$ V. The integrated EL intensity was found to scale with the ratio of off-state gate leakage current before and after the stress. The results were verified using step-stress tests to find the breakdown voltage (BV) of the gate dielectric of the stressed devices. BV was again found to scale with the measured integrated EL intensity for both the stress conditions. The results show that a short duration off-state stress in conjunction with EL can be a beneficial tool for quick assessment of the quality of gate dielectric across the wafer without incurring any significant damage to the devices. This becomes especially useful for rapid on-wafer device screening during large-scale production.
{"title":"Rapid On-Wafer Quality Screening of AlGaN/GaN Superlattice Castellated Field Effect Transistors Using Short-Term Stress and Electroluminescence","authors":"Bazila Parvez;Akhil S. Kumar;James W. Pomeroy;Matthew D. Smith;Robert S. Howell;Martin Kuball","doi":"10.1109/LED.2024.3478073","DOIUrl":"https://doi.org/10.1109/LED.2024.3478073","url":null,"abstract":"A electroluminescence (EL) based methodology has been devised to screen AlGaN/GaN Super-Lattice Castellated Field Effect Transistors (SLCFETs). EL intensity captured during off-state stressing has been correlated with an increase in gate leakage current after stress. Two off-state constant-voltage stress conditions were used, both applied over a stress time (\u0000<inline-formula> <tex-math>${mathrm {t}}_{text {stress}}$ </tex-math></inline-formula>\u0000) of 90 seconds: (a) \u0000<inline-formula> <tex-math>${mathrm{V}}_{text {GS}} = -12$ </tex-math></inline-formula>\u0000 V, \u0000<inline-formula> <tex-math>${mathrm{V}}_{text {DS}} = 12$ </tex-math></inline-formula>\u0000 V, and (b) \u0000<inline-formula> <tex-math>${mathrm{V}}_{text {GS}} = -12$ </tex-math></inline-formula>\u0000 V, \u0000<inline-formula> <tex-math>${mathrm{V}}_{text {DS}} = 14$ </tex-math></inline-formula>\u0000 V. The integrated EL intensity was found to scale with the ratio of off-state gate leakage current before and after the stress. The results were verified using step-stress tests to find the breakdown voltage (BV) of the gate dielectric of the stressed devices. BV was again found to scale with the measured integrated EL intensity for both the stress conditions. The results show that a short duration off-state stress in conjunction with EL can be a beneficial tool for quick assessment of the quality of gate dielectric across the wafer without incurring any significant damage to the devices. This becomes especially useful for rapid on-wafer device screening during large-scale production.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2503-2505"},"PeriodicalIF":4.1,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142754261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1109/LED.2024.3477438
Jie Luo;Yanyu Yang;Yupeng Lu;Yunjiao Bao;Guilei Wang;Gaobo Xu;Huaxiang Yin;Chao Zhao;Jun Luo
During the investigation of amorphous oxide semiconductor thin film transistors (TFTs), researchers found that TFTs containing a heterostructure-channel demonstrate exceptional mobility. This study focuses on the physical insights into the interfacial channel formation and modulating the device performance. The InGaZnO / InSnO heterostructure-channel TFTs were utilized. The band structure of their interface channel was elucidated by Ultraviolet Photoelectron Spectroscopy and Reflection Electron Energy Loss Spectroscopy. Through the examination of the band structures of heterostructure -channel TFTs, we have discovered that the thickness of the InSnO layer can modify the interface band-edge via the quantum confinement effect. By that, the threshold voltage of the heterostructure-channel TFT was altered.
{"title":"Effective Interface Channel Control in IGZO/ITO Heterostructure-Channel Thin Film Transistors","authors":"Jie Luo;Yanyu Yang;Yupeng Lu;Yunjiao Bao;Guilei Wang;Gaobo Xu;Huaxiang Yin;Chao Zhao;Jun Luo","doi":"10.1109/LED.2024.3477438","DOIUrl":"https://doi.org/10.1109/LED.2024.3477438","url":null,"abstract":"During the investigation of amorphous oxide semiconductor thin film transistors (TFTs), researchers found that TFTs containing a heterostructure-channel demonstrate exceptional mobility. This study focuses on the physical insights into the interfacial channel formation and modulating the device performance. The InGaZnO / InSnO heterostructure-channel TFTs were utilized. The band structure of their interface channel was elucidated by Ultraviolet Photoelectron Spectroscopy and Reflection Electron Energy Loss Spectroscopy. Through the examination of the band structures of heterostructure -channel TFTs, we have discovered that the thickness of the InSnO layer can modify the interface band-edge via the quantum confinement effect. By that, the threshold voltage of the heterostructure-channel TFT was altered.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2419-2422"},"PeriodicalIF":4.1,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1109/LED.2024.3477505
Ya-Ching Yu;Chia-Hsien Tsai;Zhi-Qiang Lee;Chin-Yu Chang;Cheng-Chien Lin;Yi-Cheng Liao;Tzu-Hsuan Hsu;Ming-Huang Li
In this study, we explore the design and implementation of a magnetic-free radio frequency (RF) circulator using spatiotemporal modulated thin film surface acoustic wave delay lines. The four-port circulator is designed based on two tightly packed low-propagation loss acoustic delay lines (ADLs) on a single LN/SiO2/sapphire (LNOS) chip with sequentially-switched delay line (SSDL) topology, complemented by two external switch modules composed of commercially available RF switches. The ADLs are characterized by a low insertion loss (IL) of 5.54 dB, a wide 3-dB bandwidth of 5.45%, and a large group delay of 110 ns at 880 MHz, operating in shear horizontal (SH) mode. The implemented circulator achieves a nonreciprocal contrast of 18.2 dB and 20.8 dB between IL of 10.8 dB and isolation of 29 dB (port 3 to port 1) and 31.6 dB (port 4 to port 1) over an isolation bandwidth of 6% (53.6 MHz), with a low modulation frequency of 2.27 MHz.
{"title":"A Magnetic-Free RF Circulator Based on Spatiotemporal Modulated LN/SiO2/Sapphire Surface Acoustic Wave Delay Lines","authors":"Ya-Ching Yu;Chia-Hsien Tsai;Zhi-Qiang Lee;Chin-Yu Chang;Cheng-Chien Lin;Yi-Cheng Liao;Tzu-Hsuan Hsu;Ming-Huang Li","doi":"10.1109/LED.2024.3477505","DOIUrl":"https://doi.org/10.1109/LED.2024.3477505","url":null,"abstract":"In this study, we explore the design and implementation of a magnetic-free radio frequency (RF) circulator using spatiotemporal modulated thin film surface acoustic wave delay lines. The four-port circulator is designed based on two tightly packed low-propagation loss acoustic delay lines (ADLs) on a single LN/SiO2/sapphire (LNOS) chip with sequentially-switched delay line (SSDL) topology, complemented by two external switch modules composed of commercially available RF switches. The ADLs are characterized by a low insertion loss (IL) of 5.54 dB, a wide 3-dB bandwidth of 5.45%, and a large group delay of 110 ns at 880 MHz, operating in shear horizontal (SH) mode. The implemented circulator achieves a nonreciprocal contrast of 18.2 dB and 20.8 dB between IL of 10.8 dB and isolation of 29 dB (port 3 to port 1) and 31.6 dB (port 4 to port 1) over an isolation bandwidth of 6% (53.6 MHz), with a low modulation frequency of 2.27 MHz.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2514-2517"},"PeriodicalIF":4.1,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142754259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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