Enhancement-mode (E-mode) AlN/GaN high electron mobility transistors (HEMTs) with a 160-nm T- shape recessed gate on a silicon substrate were fabricated. The fabricated device has a ${V}_{text {TH}}$ of +0.35 V, and shows a maximum drain current ( ${I}_{text {DMAX}}text {)}$ of 1.58 A/mm, a low on- resistance ( ${R}_{text {ON}}text {)}$ of $1.8~Omega cdot $ mm, and a peak transconductance ( ${G}_{text {MMAX}}text {)}$ over 580 mS/mm. A cut-off frequency ( ${f}_{text {T}}text {)}$ of 85 GHz and a maximum oscillation frequency ( ${f}_{max }text {)}$ of 75 GHz were obtained. Load pull continuous-wave (CW) power sweep measurement at 3.6 GHz demonstrated a peak power-added-efficiency (PAE) of 71.4% and a saturated output power density ( ${P}_{text {out}}text {)}$ of 0.70 W/mm at ${V}_{text {DS}}=6$ V. At 3.6 GHz pulsed wave (PW) power sweep at ${V}_{text {DS}}=6$ V the device demonstrated an 80.4% PAE and 0.5 W/mm associated ${P}_{text {out}}$ . These results promises the great potential of E-mode AlN/GaN HEMTs with gate recess in the applications of low supply voltage RF power applications.
在硅衬底上制备了具有160 nm T型凹槽栅的增强模式（E-mode） AlN/GaN高电子迁移率晶体管（hemt）。该器件的电压${V}_{text {TH}}$为+0.35 V，最大漏极电流${I}_{text {DMAX}}text {)}$为1.58 a /mm，导通电阻${R}_{text {ON}}text {)}$为$1.8~Omega cdot $ mm，峰值跨导${G}_{text {MMAX}}text {)}$超过580 mS/mm。截止频率${f}_{text {T}}text {)}$为85 GHz，最大振荡频率${f}_{max }text {)}$为75 GHz。负载拉连续波（CW）在3.6 GHz下的功率扫描测量显示，峰值功率附加效率（PAE）为71.4% and a saturated output power density ( ${P}_{text {out}}text {)}$ of 0.70 W/mm at ${V}_{text {DS}}=6$ V. At 3.6 GHz pulsed wave (PW) power sweep at ${V}_{text {DS}}=6$ V the device demonstrated an 80.4% PAE and 0.5 W/mm associated ${P}_{text {out}}$ . These results promises the great potential of E-mode AlN/GaN HEMTs with gate recess in the applications of low supply voltage RF power applications.
{"title":"E-Mode AlN/GaN HEMTs on Si With 80.4% PAE at 3.6 GHz for Low-Supply-Voltage RF Power Applications","authors":"Guangjie Gao;Zhihong Liu;Lu Hao;Fang Zhang;Xiaojin Chen;Hanghai Du;Weichuan Xing;Hong Zhou;Jincheng Zhang;Yue Hao","doi":"10.1109/LED.2024.3495672","DOIUrl":"https://doi.org/10.1109/LED.2024.3495672","url":null,"abstract":"Enhancement-mode (E-mode) AlN/GaN high electron mobility transistors (HEMTs) with a 160-nm T- shape recessed gate on a silicon substrate were fabricated. The fabricated device has a \u0000<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>\u0000 of +0.35 V, and shows a maximum drain current (\u0000<inline-formula> <tex-math>${I}_{text {DMAX}}text {)}$ </tex-math></inline-formula>\u0000 of 1.58 A/mm, a low on- resistance (\u0000<inline-formula> <tex-math>${R}_{text {ON}}text {)}$ </tex-math></inline-formula>\u0000 of \u0000<inline-formula> <tex-math>$1.8~Omega cdot $ </tex-math></inline-formula>\u0000 mm, and a peak transconductance (\u0000<inline-formula> <tex-math>${G}_{text {MMAX}}text {)}$ </tex-math></inline-formula>\u0000 over 580 mS/mm. A cut-off frequency (\u0000<inline-formula> <tex-math>${f}_{text {T}}text {)}$ </tex-math></inline-formula>\u0000 of 85 GHz and a maximum oscillation frequency (\u0000<inline-formula> <tex-math>${f}_{max }text {)}$ </tex-math></inline-formula>\u0000 of 75 GHz were obtained. Load pull continuous-wave (CW) power sweep measurement at 3.6 GHz demonstrated a peak power-added-efficiency (PAE) of 71.4% and a saturated output power density (\u0000<inline-formula> <tex-math>${P}_{text {out}}text {)}$ </tex-math></inline-formula>\u0000 of 0.70 W/mm at \u0000<inline-formula> <tex-math>${V}_{text {DS}}=6$ </tex-math></inline-formula>\u0000 V. At 3.6 GHz pulsed wave (PW) power sweep at \u0000<inline-formula> <tex-math>${V}_{text {DS}}=6$ </tex-math></inline-formula>\u0000 V the device demonstrated an 80.4% PAE and 0.5 W/mm associated \u0000<inline-formula> <tex-math>${P}_{text {out}}$ </tex-math></inline-formula>\u0000. These results promises the great potential of E-mode AlN/GaN HEMTs with gate recess in the applications of low supply voltage RF power applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 1","pages":"40-43"},"PeriodicalIF":4.1,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-11DOI: 10.1109/LED.2024.3495654
Lei Lei;Zihe Zhu;Wenliang Wang;Guoqiang Li
With the increasing wireless capacity demand for in sixth-generation (6G) networks exacerbating the issue of spectrum scarcity, high-speed visible light communication (VLC) based on GaN-based light-emitting diodes (LEDs) has emerged as a crucial supplementary solution. However, the lack of LED performance severely limits the development of VLC. Herein, the blue micro-LED array with the gradient of In component in the InxGa1-xN quantum barrier (QB) was demonstrated. Among them, the micro-LED array of two QBs with linearly increasing In component along [0001] direction serves to effectively suppress the polarization electric field, thereby increasing the radiative recombination efficiency and carrier concentration. At the current density of 2000 A/cm2, the light output power (LOP) is 28.9 mW, and the -3 dB bandwidth reaches 580 MHz, approximately 34% higher than that of the GaN barrier. This work presents a novel and simple strategy for realizing a high modulation bandwidth micro-LED array.
{"title":"Large Modulation Bandwidth GaN-Based Micro-LED Arrays on Si Substrates With Graded in Composition Barriers","authors":"Lei Lei;Zihe Zhu;Wenliang Wang;Guoqiang Li","doi":"10.1109/LED.2024.3495654","DOIUrl":"https://doi.org/10.1109/LED.2024.3495654","url":null,"abstract":"With the increasing wireless capacity demand for in sixth-generation (6G) networks exacerbating the issue of spectrum scarcity, high-speed visible light communication (VLC) based on GaN-based light-emitting diodes (LEDs) has emerged as a crucial supplementary solution. However, the lack of LED performance severely limits the development of VLC. Herein, the blue micro-LED array with the gradient of In component in the InxGa1-xN quantum barrier (QB) was demonstrated. Among them, the micro-LED array of two QBs with linearly increasing In component along [0001] direction serves to effectively suppress the polarization electric field, thereby increasing the radiative recombination efficiency and carrier concentration. At the current density of 2000 A/cm2, the light output power (LOP) is 28.9 mW, and the -3 dB bandwidth reaches 580 MHz, approximately 34% higher than that of the GaN barrier. This work presents a novel and simple strategy for realizing a high modulation bandwidth micro-LED array.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 1","pages":"28-31"},"PeriodicalIF":4.1,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chalcogenide-based novel Selector-Only Memory (SOM) has attracted much attention due to its fast-speed performance and manufacturability. However, the lack of endurance, caused by the polarity operation, needs to be improved. Here, we investigate an indium doping scheme for write endurance enhanced and large memory window of GeSe-based SOM. With the evidence of atomic migration, we propose a trade-off relationship between MW and endurance and a relevant model of Se-migration in a restricted range. Based on this model, we demonstrate that less than 5% In-doping can fit the optimization requirements. Besides, the performance of GeSe devices with different In concentrations further confirms the trade-off relationship. Finally, 3% In-doping GeSe SOM devices are fabricated with a large MW (1.3 V), three orders of magnitude improvement of write endurance compared with GeSe devices ( $10^{{6}}$ ) and excellent read endurance ( $10^{{9}}$ ). This work helps the endurance optimization of SOM devices and is promising to accelerate its widespread application.
{"title":"Write Endurance Enhanced and Large Memory Window of GeSe-Based Selector-Only Memory With Indium Doping Scheme","authors":"Jinyu Wen;Chuanqi Yi;Jiangxi Chen;Lun Wang;Zixuan Liu;Ziqi Chen;Hao Tong;Xiangshui Miao","doi":"10.1109/LED.2024.3495778","DOIUrl":"https://doi.org/10.1109/LED.2024.3495778","url":null,"abstract":"Chalcogenide-based novel Selector-Only Memory (SOM) has attracted much attention due to its fast-speed performance and manufacturability. However, the lack of endurance, caused by the polarity operation, needs to be improved. Here, we investigate an indium doping scheme for write endurance enhanced and large memory window of GeSe-based SOM. With the evidence of atomic migration, we propose a trade-off relationship between MW and endurance and a relevant model of Se-migration in a restricted range. Based on this model, we demonstrate that less than 5% In-doping can fit the optimization requirements. Besides, the performance of GeSe devices with different In concentrations further confirms the trade-off relationship. Finally, 3% In-doping GeSe SOM devices are fabricated with a large MW (1.3 V), three orders of magnitude improvement of write endurance compared with GeSe devices (\u0000<inline-formula> <tex-math>$10^{{6}}$ </tex-math></inline-formula>\u0000) and excellent read endurance (\u0000<inline-formula> <tex-math>$10^{{9}}$ </tex-math></inline-formula>\u0000). This work helps the endurance optimization of SOM devices and is promising to accelerate its widespread application.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 1","pages":"115-118"},"PeriodicalIF":4.1,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142905858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Despite the low dielectric constant and minimal loss of glass substrates, noise coupling remains a challenge in high-frequency, high-density interconnects. In this letter, six noise shielding structures are proposed, and a simplified TGV noise coupling circuit model is developed to estimate their effectiveness. Seven test vehicles were fabricated for comparison, and good agreement was observed between the measured, simulated, and estimated results. This analysis effectively estimates noise coupling without the need for complex simulations. Noise suppression improvements of 20 dB at 40 GHz and 35 dB at 60 GHz were achieved with the guard rings, significantly outperforming traditional techniques. A 40 dB reduction in noise at 60 GHz was achieved with the guard trenches. Proposed shielding structures and evaluation methods can be applied to noise coupling in future millimeter-wave broadband glass core substrate integration.
{"title":"Noise Coupling and Shielding Structures for Glass Core Substrate","authors":"Zhen Fang;Jihua Zhang;Jinxu Liu;Ding Wen;Libin Gao;Hongwei Chen;Xingzhou Cai;Zhihua Tao;Wanli Zhang","doi":"10.1109/LED.2024.3493599","DOIUrl":"https://doi.org/10.1109/LED.2024.3493599","url":null,"abstract":"Despite the low dielectric constant and minimal loss of glass substrates, noise coupling remains a challenge in high-frequency, high-density interconnects. In this letter, six noise shielding structures are proposed, and a simplified TGV noise coupling circuit model is developed to estimate their effectiveness. Seven test vehicles were fabricated for comparison, and good agreement was observed between the measured, simulated, and estimated results. This analysis effectively estimates noise coupling without the need for complex simulations. Noise suppression improvements of 20 dB at 40 GHz and 35 dB at 60 GHz were achieved with the guard rings, significantly outperforming traditional techniques. A 40 dB reduction in noise at 60 GHz was achieved with the guard trenches. Proposed shielding structures and evaluation methods can be applied to noise coupling in future millimeter-wave broadband glass core substrate integration.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 1","pages":"84-87"},"PeriodicalIF":4.1,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-01DOI: 10.1109/LED.2024.3482099
Giuk Kim;Hyojun Choi;Hongrae Cho;Sangho Lee;Hunbeom Shin;Hyunjun Kang;Hoon Kim;Seokjoong Shin;Seonjae Park;Sunseong Kwon;Youngjin Lim;Kang Kim;Jong Min Chung;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon
The ferroelectric (FE) NAND flash, featuring metal-interlayer-FE-interlayer-silicon (MIFIS) gate stacks, leverages both charge trapping and polarization (P) switching to achieve a broad memory window (MW) and low operation voltage. These remarkable advancements establish it as a viable contender for future NAND flash technologies. However, the read-after-write-delay (RAWD) problem during program/erase (PGM/ERS), caused by channel-injected interface trapped charges ( ${Q}_{text {it}}$ ) between the FE layer and the channel interlayer (Ch.IL), leading to short-term Vth variations, remains unexplored in MIFIS FE-NAND cells. This letter presents the first analysis of RAWD in FE-NAND cells, including the experimental optimization of a de-trap pulse that effectively eliminates ${Q}_{text {it}}$ whereas preserving both gate-injected interface trapped charges ( ${Q}_{text {it}}$ ’) and P. Consequently, the FE-NAND cell exhibits a narrow MW of 3.45 V at a delay time ( ${t}_{text {Delay}}text {)}$ of $1~mu $ s between PGM/ERS and read operations, expending to 7.40 V at a tDelay of 1 s. This variation is attributed to the generation of ${Q}_{text {it}}$ and the subsequent de-trap process, affecting channel conductivity. To thoroughly address the RAWD, various pulse widths and amplitudes are experimentally explored immediately post-PGM/ERS to optimize the de-trap pulse for selective ${Q}_{text {it}}$ removal. Upon applying the optimized de-trap pulse, the stable wide MW (7.40 V) is consistently maintained regardless of ${t}_{text {Delay}}$ . This work is meaningful as it brings attention to previously unexplored issues in next-generation ferroelectric (FE) NAND cells and suggests practical operational solutions.
{"title":"Optimizing De-Trap Pulses in Gate-Injection Type Ferroelectric NAND Cells to Minimize Read After Write Delay Issue","authors":"Giuk Kim;Hyojun Choi;Hongrae Cho;Sangho Lee;Hunbeom Shin;Hyunjun Kang;Hoon Kim;Seokjoong Shin;Seonjae Park;Sunseong Kwon;Youngjin Lim;Kang Kim;Jong Min Chung;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon","doi":"10.1109/LED.2024.3482099","DOIUrl":"https://doi.org/10.1109/LED.2024.3482099","url":null,"abstract":"The ferroelectric (FE) NAND flash, featuring metal-interlayer-FE-interlayer-silicon (MIFIS) gate stacks, leverages both charge trapping and polarization (P) switching to achieve a broad memory window (MW) and low operation voltage. These remarkable advancements establish it as a viable contender for future NAND flash technologies. However, the read-after-write-delay (RAWD) problem during program/erase (PGM/ERS), caused by channel-injected interface trapped charges (\u0000<inline-formula> <tex-math>${Q}_{text {it}}$ </tex-math></inline-formula>\u0000) between the FE layer and the channel interlayer (Ch.IL), leading to short-term Vth variations, remains unexplored in MIFIS FE-NAND cells. This letter presents the first analysis of RAWD in FE-NAND cells, including the experimental optimization of a de-trap pulse that effectively eliminates \u0000<inline-formula> <tex-math>${Q}_{text {it}}$ </tex-math></inline-formula>\u0000 whereas preserving both gate-injected interface trapped charges (\u0000<inline-formula> <tex-math>${Q}_{text {it}}$ </tex-math></inline-formula>\u0000’) and P. Consequently, the FE-NAND cell exhibits a narrow MW of 3.45 V at a delay time (\u0000<inline-formula> <tex-math>${t}_{text {Delay}}text {)}$ </tex-math></inline-formula>\u0000 of \u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000s between PGM/ERS and read operations, expending to 7.40 V at a tDelay of 1 s. This variation is attributed to the generation of \u0000<inline-formula> <tex-math>${Q}_{text {it}}$ </tex-math></inline-formula>\u0000 and the subsequent de-trap process, affecting channel conductivity. To thoroughly address the RAWD, various pulse widths and amplitudes are experimentally explored immediately post-PGM/ERS to optimize the de-trap pulse for selective \u0000<inline-formula> <tex-math>${Q}_{text {it}}$ </tex-math></inline-formula>\u0000 removal. Upon applying the optimized de-trap pulse, the stable wide MW (7.40 V) is consistently maintained regardless of \u0000<inline-formula> <tex-math>${t}_{text {Delay}}$ </tex-math></inline-formula>\u0000. This work is meaningful as it brings attention to previously unexplored issues in next-generation ferroelectric (FE) NAND cells and suggests practical operational solutions.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2359-2362"},"PeriodicalIF":4.1,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ferroelectric (FE) Hf $_{text {1-x}}$ ZrxO2 (HZO) thin films have attracted considerable interest for their potential application in Ferroelectric Random-Access Memory (FeRAM) and Ferroelectric Field-Effect Transistors (FeFET), owing to their high dielectric constant, stability, and compatibility with CMOS processes. However, enhancing the polarization switching speed of HZO thin films remains a significant challenge. In this study, we successfully reduced the coercive field and improved the switching speed of HZO devices by integrating ferroelectric and antiferroelectric layers. We employed a high-speed pulsed measurement system with sub-nanosecond resolution to evaluate the switching speed of these devices. An ultrafast switching time of 780 ps at 2V was achieved, as supported by the nucleation-limited switching model. This work demonstrates a promising strategy for enhancing the switching speed in HZO films through structural engineering, offering valuable insights for practical device applications.
{"title":"Ultrafast Switching of Ferroelectric HfO2-ZrO2 Under Low Voltage With Layered Structure","authors":"Yifan Song;Jiajie Yu;Zhuming Wang;Kangli Xu;Yongkai Liu;Chen Wang;Kun Chen;Qingqing Sun;David Wei Zhang;Lin Chen","doi":"10.1109/LED.2024.3487169","DOIUrl":"https://doi.org/10.1109/LED.2024.3487169","url":null,"abstract":"Ferroelectric (FE) Hf\u0000<inline-formula> <tex-math>$_{text {1-x}}$ </tex-math></inline-formula>\u0000ZrxO2 (HZO) thin films have attracted considerable interest for their potential application in Ferroelectric Random-Access Memory (FeRAM) and Ferroelectric Field-Effect Transistors (FeFET), owing to their high dielectric constant, stability, and compatibility with CMOS processes. However, enhancing the polarization switching speed of HZO thin films remains a significant challenge. In this study, we successfully reduced the coercive field and improved the switching speed of HZO devices by integrating ferroelectric and antiferroelectric layers. We employed a high-speed pulsed measurement system with sub-nanosecond resolution to evaluate the switching speed of these devices. An ultrafast switching time of 780 ps at 2V was achieved, as supported by the nucleation-limited switching model. This work demonstrates a promising strategy for enhancing the switching speed in HZO films through structural engineering, offering valuable insights for practical device applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 1","pages":"12-15"},"PeriodicalIF":4.1,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, we propose a hybrid bonding process for the preparation of micro-light-emitting diode (Micro-LED) based on asymmetric structures. This process employs a bonding system comprised of metal and photopolymer. The asymmetric structure is formed by utilizing a blue film to selectively remove the metal from the photoresist after the metal has been evaporated. Cross-sectional observation of the Micro-LED after bonding reveals that effective filling can be achieved. Consequently, compared to the symmetrical structure process, the steps of spin coating the polymer and chemical mechanical polishing (CMP) on both sides are omitted, greatly simplifying the process. Tests indicate that the Micro-LED device manufactured using this method exhibits excellent electrical and optical properties, with a bonding strength of 17.1 MPa, which is 73.6% greater than that of bump bonding. Furthermore, the asymmetric structure mitigates the sliding issues associated with joining symmetric structures and enhances pixel isolation, thereby improving bonding accuracy. It is crucial for increasing the yield and reducing the cost of Micro-LED in terms of commercialization.
{"title":"Research on Hybrid Bonding Process of Micro-LED Preparation Based on Asymmetric Structure","authors":"Luqiao Yin;Jianxin Li;Zhu Yang;Xiaoxiao Ji;Haojie Zhou;Jianhua Zhang","doi":"10.1109/LED.2024.3486568","DOIUrl":"https://doi.org/10.1109/LED.2024.3486568","url":null,"abstract":"In this letter, we propose a hybrid bonding process for the preparation of micro-light-emitting diode (Micro-LED) based on asymmetric structures. This process employs a bonding system comprised of metal and photopolymer. The asymmetric structure is formed by utilizing a blue film to selectively remove the metal from the photoresist after the metal has been evaporated. Cross-sectional observation of the Micro-LED after bonding reveals that effective filling can be achieved. Consequently, compared to the symmetrical structure process, the steps of spin coating the polymer and chemical mechanical polishing (CMP) on both sides are omitted, greatly simplifying the process. Tests indicate that the Micro-LED device manufactured using this method exhibits excellent electrical and optical properties, with a bonding strength of 17.1 MPa, which is 73.6% greater than that of bump bonding. Furthermore, the asymmetric structure mitigates the sliding issues associated with joining symmetric structures and enhances pixel isolation, thereby improving bonding accuracy. It is crucial for increasing the yield and reducing the cost of Micro-LED in terms of commercialization.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2475-2478"},"PeriodicalIF":4.1,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142754257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/LED.2024.3475766
{"title":"IEEE Transactions on Electron Devices Table of Contents","authors":"","doi":"10.1109/LED.2024.3475766","DOIUrl":"https://doi.org/10.1109/LED.2024.3475766","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 11","pages":"2254-C3"},"PeriodicalIF":4.1,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736131","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142524122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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