Pub Date : 2025-09-26DOI: 10.1109/LED.2025.3608539
{"title":"IEEE Transactions on Electron Devices Table of Contents","authors":"","doi":"10.1109/LED.2025.3608539","DOIUrl":"https://doi.org/10.1109/LED.2025.3608539","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1931-C3"},"PeriodicalIF":4.5,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11182277","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-26DOI: 10.1109/LED.2025.3608535
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Reliability of Advanced Nodes","authors":"","doi":"10.1109/LED.2025.3608535","DOIUrl":"https://doi.org/10.1109/LED.2025.3608535","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1927-1928"},"PeriodicalIF":4.5,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11182282","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-26DOI: 10.1109/LED.2025.3614968
Jie Zhang;Jian Guan;Jiangnan Liu;Paiting Liu;Shubham Mondal;Yuxuan Luan;Md Tanvir Hasan;Yuyang Chen;Edgar Meyhofer;Pramod Reddy;Zetian Mi
We investigate self-heating effects (SHE) and thermal mitigation strategies in ferroelectric ScAlN/GaN high-electron-mobility transistors (HEMTs). Molecular beam epitaxy (MBE)-grown devices demonstrate a large memory window (MW) of ~3.8 V, on/off current ratio (I${}_{mathbf {text {on}}}$ /I${}_{mathbf {text {off}}}$ ) $gt 10^{mathbf {{8}}}$ , and sub-Boltzmann subthreshold swing (SS) ~20 mV/dec, enabled by ScAlN polarization control of the two-dimensional electron gas (2DEG). Under high drain bias, SHE degrades memory and subthreshold characteristics. The thermal origin of degradation is confirmed by external heating and transconductance analysis. Multi-frequency conductance measurements reveal charge trapping and detrapping, which may be accelerated by SHE. Heat sink integration effectively reduces temperature rise, as verified by scanning thermal microscopy. These results underscore the importance of thermal management for reliable ferroelectric HEMT operation in high-power and extreme-environment applications.
{"title":"Self-Heating Effects and Thermal Mitigation Strategies in Ferroelectric ScAlN/GaN HEMTs","authors":"Jie Zhang;Jian Guan;Jiangnan Liu;Paiting Liu;Shubham Mondal;Yuxuan Luan;Md Tanvir Hasan;Yuyang Chen;Edgar Meyhofer;Pramod Reddy;Zetian Mi","doi":"10.1109/LED.2025.3614968","DOIUrl":"https://doi.org/10.1109/LED.2025.3614968","url":null,"abstract":"We investigate self-heating effects (SHE) and thermal mitigation strategies in ferroelectric ScAlN/GaN high-electron-mobility transistors (HEMTs). Molecular beam epitaxy (MBE)-grown devices demonstrate a large memory window (MW) of ~3.8 V, on/off current ratio (I<inline-formula> <tex-math>${}_{mathbf {text {on}}}$ </tex-math></inline-formula>/I<inline-formula> <tex-math>${}_{mathbf {text {off}}}$ </tex-math></inline-formula>) <inline-formula> <tex-math>$gt 10^{mathbf {{8}}}$ </tex-math></inline-formula>, and sub-Boltzmann subthreshold swing (SS) ~20 mV/dec, enabled by ScAlN polarization control of the two-dimensional electron gas (2DEG). Under high drain bias, SHE degrades memory and subthreshold characteristics. The thermal origin of degradation is confirmed by external heating and transconductance analysis. Multi-frequency conductance measurements reveal charge trapping and detrapping, which may be accelerated by SHE. Heat sink integration effectively reduces temperature rise, as verified by scanning thermal microscopy. These results underscore the importance of thermal management for reliable ferroelectric HEMT operation in high-power and extreme-environment applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 12","pages":"2373-2376"},"PeriodicalIF":4.5,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11181178","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145665843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-26DOI: 10.1109/LED.2025.3608537
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/LED.2025.3608537","DOIUrl":"https://doi.org/10.1109/LED.2025.3608537","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1929-1930"},"PeriodicalIF":4.5,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11182273","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-26DOI: 10.1109/LED.2025.3608533
{"title":"IEEE Electron Device Letters Information for Authors","authors":"","doi":"10.1109/LED.2025.3608533","DOIUrl":"https://doi.org/10.1109/LED.2025.3608533","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1926-1926"},"PeriodicalIF":4.5,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11182278","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To adapt to diverse tasks under varying operational environments, memristor devices are usually required to emulate multiple biological functions. However, integrating such diverse functionalities within a single self-rectifying memristor remains a significant challenge. In this work, we report a self-rectifying memristor based on a Pt/TiO${}_{mathbf {x}}$ N${}_{mathbf {y}}$ /HfO${}_{mathbf {{2}}}$ /W structure. For the first time, we demonstrate that a single device can emulate both leaky integrate-and-fire (LIF) neuron and nociceptor behaviors. Under pulse stimulation with a $10~mu $ s width, the device functions as an LIF neuron, while increasing the pulse width to $100~mu $ s or longer enables nociceptor-like responses. Notably, the LIF neuron operation exhibits ultra-low energy consumption of only 0.8 fJ/spike. In addition, the device exhibits a high rectifying ratio ($gt 10^{5}$ ), large switching ratio ($gt 10^{4}$ ), and ultra-low leakage current (~100 pA). This multifunctional self-rectifying memristor offers a promising pathway toward compact neuromorphic systems by enabling simplified device architectures with integrated perceptual and computational capabilities.
{"title":"A Multifunctional Self-Rectifying Memristor Enabling LIF Neuron and Nociceptor Behaviors","authors":"Bingqi Cai;Chen Wang;Kun Chen;Qingqing Sun;David Wei Zhang;Lin Chen","doi":"10.1109/LED.2025.3614142","DOIUrl":"https://doi.org/10.1109/LED.2025.3614142","url":null,"abstract":"To adapt to diverse tasks under varying operational environments, memristor devices are usually required to emulate multiple biological functions. However, integrating such diverse functionalities within a single self-rectifying memristor remains a significant challenge. In this work, we report a self-rectifying memristor based on a Pt/TiO<inline-formula> <tex-math>${}_{mathbf {x}}$ </tex-math></inline-formula> N<inline-formula> <tex-math>${}_{mathbf {y}}$ </tex-math></inline-formula>/HfO<inline-formula> <tex-math>${}_{mathbf {{2}}}$ </tex-math></inline-formula>/W structure. For the first time, we demonstrate that a single device can emulate both leaky integrate-and-fire (LIF) neuron and nociceptor behaviors. Under pulse stimulation with a <inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>s width, the device functions as an LIF neuron, while increasing the pulse width to <inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>s or longer enables nociceptor-like responses. Notably, the LIF neuron operation exhibits ultra-low energy consumption of only 0.8 fJ/spike. In addition, the device exhibits a high rectifying ratio (<inline-formula> <tex-math>$gt 10^{5}$ </tex-math></inline-formula>), large switching ratio (<inline-formula> <tex-math>$gt 10^{4}$ </tex-math></inline-formula>), and ultra-low leakage current (~100 pA). This multifunctional self-rectifying memristor offers a promising pathway toward compact neuromorphic systems by enabling simplified device architectures with integrated perceptual and computational capabilities.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 12","pages":"2361-2364"},"PeriodicalIF":4.5,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145665814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-25DOI: 10.1109/LED.2025.3614492
Tamanna Nazeer;Sheikh Aamir Ahsan
We present a physics-based static DC SPICE model for 2D-material-based reconfigurable FETs (RFETs) using our in-house core, which integrates Fermi–Dirac (FD) statistics with 2D density of states (DOS) and models transport via thermionic (TE), field emission (FE), and drift-diffusion (DD) formalisms. The model takes advantage of its SPICE compatibility by virtue of the Lambert-W function, which renders it compatible with Verilog-A, and is validated through experimental device and inverter characteristics. This is followed by model-based Monte Carlo simulations in Keysight’s ADS for circuit level variability analysis. Subsequently, the implementation of polymorphic NAND/NOR gates using the reconfigurable 2D-FETs is demonstrated for secure circuits.
{"title":"Analyzing Variability in Reconfigurable 2D-FET Circuits Using a Physics-Based SPICE Model","authors":"Tamanna Nazeer;Sheikh Aamir Ahsan","doi":"10.1109/LED.2025.3614492","DOIUrl":"https://doi.org/10.1109/LED.2025.3614492","url":null,"abstract":"We present a physics-based static DC SPICE model for 2D-material-based reconfigurable FETs (RFETs) using our in-house core, which integrates Fermi–Dirac (FD) statistics with 2D density of states (DOS) and models transport via thermionic (TE), field emission (FE), and drift-diffusion (DD) formalisms. The model takes advantage of its SPICE compatibility by virtue of the Lambert-W function, which renders it compatible with Verilog-A, and is validated through experimental device and inverter characteristics. This is followed by model-based Monte Carlo simulations in Keysight’s ADS for circuit level variability analysis. Subsequently, the implementation of polymorphic NAND/NOR gates using the reconfigurable 2D-FETs is demonstrated for secure circuits.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 12","pages":"2369-2372"},"PeriodicalIF":4.5,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145665734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-25DOI: 10.1109/LED.2025.3614511
Sandeep Semwal;Pin Su
This work leverages the unique nature of CFETs for superior ambipolar conduction characteristics and explores CFET-based designs for frequency doubling, phase following, and phase reversal operations. The results highlight the advantages of CFETs for analog signal modulation and pave the way for future communication systems using logic-compatible technology.
{"title":"Exploration of Analog Signal Modulation With Complementary Field-Effect Transistor (CFET)","authors":"Sandeep Semwal;Pin Su","doi":"10.1109/LED.2025.3614511","DOIUrl":"https://doi.org/10.1109/LED.2025.3614511","url":null,"abstract":"This work leverages the unique nature of CFETs for superior ambipolar conduction characteristics and explores CFET-based designs for frequency doubling, phase following, and phase reversal operations. The results highlight the advantages of CFETs for analog signal modulation and pave the way for future communication systems using logic-compatible technology.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 12","pages":"2345-2348"},"PeriodicalIF":4.5,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145665805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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