This letter demonstrates the functionality of barrier-less 20nm NiAl for 100nm metal pitch interconnects fabricated on 300mm full wafers. We have developed an industry-relevant integration route consisting of a SiN hard mask patterned by reactive ion etching and directional NiAl etching by ion beam etch techniques. The resistivity for NiAl is found to be close to Ru, along with 99% electrical yield, impressive uniformity across the full wafer, and no bridging or line collapsing was observed.
{"title":"Directional Etching of Barrierless NiAl Lines on 300-mm Wafers for Interconnects Applications","authors":"Souvik Kundu;J.-P. Soulié;G. Marti;F. U. Okudur;Shreya Kundu;L. Souriau;F. Lazzarino;G. Murdoch;S. Park;Z. Tőkei","doi":"10.1109/LED.2024.3449219","DOIUrl":"10.1109/LED.2024.3449219","url":null,"abstract":"This letter demonstrates the functionality of barrier-less 20nm NiAl for 100nm metal pitch interconnects fabricated on 300mm full wafers. We have developed an industry-relevant integration route consisting of a SiN hard mask patterned by reactive ion etching and directional NiAl etching by ion beam etch techniques. The resistivity for NiAl is found to be close to Ru, along with 99% electrical yield, impressive uniformity across the full wafer, and no bridging or line collapsing was observed.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"2033-2035"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter demonstrates a hybrid p-GaN/MIS gate HEMT (HG-HEMT) to suppress the drain-induced dynamic threshold voltage ( ${V}_{text {th}}text {)}$ instability. By implementing a depletion-mode (D-mode) MIS gate adjacent to Schottky-type p-GaN gate, the drain-induced bidirectional shift of dynamic ${V}_{text {th}}$ is significantly reduced. The fabricated HG-HEMT exhibits decent performances compared to the conventional Schottky-type p-GaN gate HEMT (Conv-HEMT), with saturation current ( ${I}_{text {D, {sat}}}text {)}$ of 345 mA/mm, on-resistance ( ${R}_{text {ON}}text {)}$ of $13.2~Omega cdot $ mm, and hard breakdown voltage ( BV ) of 1315 V, which are similar to the Conv-HEMT. The HG-HEMT demonstrates significantly improved dynamic ${V}_{text {th}}$ stability under drain bias, with a negligible dynamic ${V}_{text {th}}$ shift at on-state drain bias of 50 V, and a small positive dynamic ${V}_{text {th}}$ shift of +0.05 V after off-state drain bias of 400 V. As a comparison, ${V}_{text {th}}$ shifts of the Conv-HEMT are −0.28 V and +0.42 V, respectively. The improved dynamic ${V}_{text {th}}$ stability of the HG-HEMT is owing to a D-mode MIS-gate region that shields the interplay between drain and the p-GaN region. The proposed HG-HEMT paves the way for highly stable GaN power electronics applications.
{"title":"Hybrid p-GaN/MIS Gate HEMT Suppressing Drain-Induced Dynamic Threshold Voltage Instability","authors":"Chen Wang;Jinyan Wang;Xin Wang;Ziheng Liu;Jiayin He;Ju Gao;Chengkang Ao;Maojun Wang;Jin Wei","doi":"10.1109/LED.2024.3448362","DOIUrl":"10.1109/LED.2024.3448362","url":null,"abstract":"This letter demonstrates a hybrid p-GaN/MIS gate HEMT (HG-HEMT) to suppress the drain-induced dynamic threshold voltage (\u0000<inline-formula> <tex-math>${V}_{text {th}}text {)}$ </tex-math></inline-formula>\u0000 instability. By implementing a depletion-mode (D-mode) MIS gate adjacent to Schottky-type p-GaN gate, the drain-induced bidirectional shift of dynamic \u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000 is significantly reduced. The fabricated HG-HEMT exhibits decent performances compared to the conventional Schottky-type p-GaN gate HEMT (Conv-HEMT), with saturation current (\u0000<inline-formula> <tex-math>${I}_{text {D, {sat}}}text {)}$ </tex-math></inline-formula>\u0000 of 345 mA/mm, on-resistance (\u0000<inline-formula> <tex-math>${R}_{text {ON}}text {)}$ </tex-math></inline-formula>\u0000 of \u0000<inline-formula> <tex-math>$13.2~Omega cdot $ </tex-math></inline-formula>\u0000 mm, and hard breakdown voltage (\u0000<italic>BV</i>\u0000) of 1315 V, which are similar to the Conv-HEMT. The HG-HEMT demonstrates significantly improved dynamic \u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000 stability under drain bias, with a negligible dynamic \u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000 shift at on-state drain bias of 50 V, and a small positive dynamic \u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000 shift of +0.05 V after off-state drain bias of 400 V. As a comparison, \u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000 shifts of the Conv-HEMT are −0.28 V and +0.42 V, respectively. The improved dynamic \u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000 stability of the HG-HEMT is owing to a D-mode MIS-gate region that shields the interplay between drain and the p-GaN region. The proposed HG-HEMT paves the way for highly stable GaN power electronics applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1732-1735"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-23DOI: 10.1109/LED.2024.3448504
Wentao Ma;Kangpei Yao;Xiaoyang Zhong;Jie Liu
When simulating charging effects in electron beam lithography (EBL) using the drift-diffusion recombination (DDR) model, traditional numerical iterative solvers face issues of slow computational speed and limited scalability. To solve this problem, we employ the Smoothed aggregation algebraic multigrid (SA-AMG) solver based on bi-conjugate gradient stabilized (BICGSTAB) and preconditioned conjugate gradient (PCG) to accelerate the computation of the DDR and Poisson equations separately. Compared to the Gauss-Seidel solver with a time complexity of ${O}text {(}{n}^{{2}}text {)}$ and the PCG, BICGSTAB solvers with a time complexity of O ( ${n}^{text {3/ {2}}}text {)}$ , the SA-AMG solver reduces the time complexity to ${O}text {(}{n}text {)}$ . This implies that at a charging time of $1~mu $ s, the computation time for simulating charging effects with SA-AMG is 93, 296, and 646 times faster than the Gauss-Seidel solver when the grid point count of ${n} = 10^{{6}}$ , $10^{{7}}$ , $10^{{8}}$ , respectively. Furthermore, compared to the combined PCG and BICGSTAB solvers, the SA-AMG solver is 4, 7, and 13 times faster for the same grid point counts.
{"title":"Efficient Calculation of Charging Effects in Electron Beam Lithography Using the SA-AMG","authors":"Wentao Ma;Kangpei Yao;Xiaoyang Zhong;Jie Liu","doi":"10.1109/LED.2024.3448504","DOIUrl":"10.1109/LED.2024.3448504","url":null,"abstract":"When simulating charging effects in electron beam lithography (EBL) using the drift-diffusion recombination (DDR) model, traditional numerical iterative solvers face issues of slow computational speed and limited scalability. To solve this problem, we employ the Smoothed aggregation algebraic multigrid (SA-AMG) solver based on bi-conjugate gradient stabilized (BICGSTAB) and preconditioned conjugate gradient (PCG) to accelerate the computation of the DDR and Poisson equations separately. Compared to the Gauss-Seidel solver with a time complexity of \u0000<inline-formula> <tex-math>${O}text {(}{n}^{{2}}text {)}$ </tex-math></inline-formula>\u0000 and the PCG, BICGSTAB solvers with a time complexity of \u0000<italic>O</i>\u0000(\u0000<inline-formula> <tex-math>${n}^{text {3/ {2}}}text {)}$ </tex-math></inline-formula>\u0000, the SA-AMG solver reduces the time complexity to \u0000<inline-formula> <tex-math>${O}text {(}{n}text {)}$ </tex-math></inline-formula>\u0000. This implies that at a charging time of \u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000 s, the computation time for simulating charging effects with SA-AMG is 93, 296, and 646 times faster than the Gauss-Seidel solver when the grid point count of \u0000<inline-formula> <tex-math>${n} = 10^{{6}}$ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$10^{{7}}$ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$10^{{8}}$ </tex-math></inline-formula>\u0000, respectively. Furthermore, compared to the combined PCG and BICGSTAB solvers, the SA-AMG solver is 4, 7, and 13 times faster for the same grid point counts.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1945-1948"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Despite successfully demonstrating GaN trench gate vertical transistors for power electronics, the devices possess inconsistent electrical properties that depend strongly on the process conditions. This work compares the vertical transistors’ threshold voltages and current densities with sidewalls treated by either H 3 PO 4 or TMAH (tetramethylammonium hydroxide). With the H 3 PO 4 sidewall post-etching treatment, the device’s threshold voltage can be restored to a higher value of 7.2 V by removing donor-type defects incurred during sidewall dry etching in the p-GaN region. In comparison, the threshold voltage of the TMAH-treated device is 0.1 V. Surface treatment also affects the current density because it changes the effective gate length and sidewall orientation. A flatter sidewall profile after H 3 PO 4 treatment results in a larger effective gate length and smaller carrier mobility when transporting in the semipolar GaN crystalline plane. The current density of the H 3 PO 4 -treated device is smaller than that treated by TMAH.
{"title":"Performance Comparisons of GaN Vertical Transistors With Sidewalls Treated by TMAH and H₃PO₄ Solutions","authors":"Yu-Chuan Chu;Chih-Kang Chang;Zhi-Xiang Zhang;Anuj Chauhan;Yi-Ta Chung;Tien-Yu Wang;Miin-Jang Chen;Wei-Chi Lai;Jian-Jang Huang","doi":"10.1109/LED.2024.3448196","DOIUrl":"10.1109/LED.2024.3448196","url":null,"abstract":"Despite successfully demonstrating GaN trench gate vertical transistors for power electronics, the devices possess inconsistent electrical properties that depend strongly on the process conditions. This work compares the vertical transistors’ threshold voltages and current densities with sidewalls treated by either H\u0000<sub>3</sub>\u0000PO\u0000<sub>4</sub>\u0000 or TMAH (tetramethylammonium hydroxide). With the H\u0000<sub>3</sub>\u0000PO\u0000<sub>4</sub>\u0000 sidewall post-etching treatment, the device’s threshold voltage can be restored to a higher value of 7.2 V by removing donor-type defects incurred during sidewall dry etching in the p-GaN region. In comparison, the threshold voltage of the TMAH-treated device is 0.1 V. Surface treatment also affects the current density because it changes the effective gate length and sidewall orientation. A flatter sidewall profile after H\u0000<sub>3</sub>\u0000PO\u0000<sub>4</sub>\u0000 treatment results in a larger effective gate length and smaller carrier mobility when transporting in the semipolar GaN crystalline plane. The current density of the H\u0000<sub>3</sub>\u0000PO\u0000<sub>4</sub>\u0000-treated device is smaller than that treated by TMAH.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1744-1747"},"PeriodicalIF":4.1,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Increasing demands on medical diagnostics, miniaturized spectroscopy, and optical communication raise the need for developing compact photodetectors with spectral selectivity. Narrowband photodetector stands out as a promising solution. Self-filtering narrowband organic photodetectors respectively peaked at 660 nm and 860 nm are fabricated following the exciton dissociation narrowing (EDN) strategy. A full width at half maximum (FWHM) of 83.0 nm with a peak EQE of 59% at 860 nm and 72.9 nm with a peak EQE of 59% at 660 nm are achieved. The narrow-band photodetectors show excellent stability that maintained a high specific detectivity of ${1}.{2}times {10}^{{12}}$ Jones at 860 nm and ${7}.{6}times {10}^{{11}}$ Jones at 660 nm after being aged in air at room temperature for 280 days. By integrating the self-filtering narrowband photodetectors peaked at 660 nm and 860 nm with red and infrared LEDs, respectively, a device for real-time non-invasive monitoring of arterial PPG signals, blood oxygen saturation, and heart rates was realized.
{"title":"Self-Filtering Narrowband Organic Photodetectors for Non-Invasive Blood-Oxygen Monitoring","authors":"Muyi Fu;Yanwei Chen;Yunhao Cao;Zihao Lin;Xiye Yang;Sheng Dong;Kai Zhang;Fei Huang","doi":"10.1109/LED.2024.3447588","DOIUrl":"10.1109/LED.2024.3447588","url":null,"abstract":"Increasing demands on medical diagnostics, miniaturized spectroscopy, and optical communication raise the need for developing compact photodetectors with spectral selectivity. Narrowband photodetector stands out as a promising solution. Self-filtering narrowband organic photodetectors respectively peaked at 660 nm and 860 nm are fabricated following the exciton dissociation narrowing (EDN) strategy. A full width at half maximum (FWHM) of 83.0 nm with a peak EQE of 59% at 860 nm and 72.9 nm with a peak EQE of 59% at 660 nm are achieved. The narrow-band photodetectors show excellent stability that maintained a high specific detectivity of \u0000<inline-formula> <tex-math>${1}.{2}times {10}^{{12}}$ </tex-math></inline-formula>\u0000 Jones at 860 nm and \u0000<inline-formula> <tex-math>${7}.{6}times {10}^{{11}}$ </tex-math></inline-formula>\u0000 Jones at 660 nm after being aged in air at room temperature for 280 days. By integrating the self-filtering narrowband photodetectors peaked at 660 nm and 860 nm with red and infrared LEDs, respectively, a device for real-time non-invasive monitoring of arterial PPG signals, blood oxygen saturation, and heart rates was realized.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1891-1894"},"PeriodicalIF":4.1,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Non-volatile cryogenic memories are crucial for realizing energy-efficient and scaled quantum computing systems. In this letter, we evaluate the cryogenic performance of an HZO-based ferroelectric capacitor (FeCAP) with a compound semiconductor (InAs) as the bottom electrode. We demonstrate that near identical remnant polarization can be obtained at 14 K compared to room temperature by increasing the voltage during the wake-up process. The switching dynamics of the FeCAP are studied at temperatures as low as 50 K with measured data analyzed by the nucleation-limited switching model. These results together with the increased endurance at cryogenic temperatures present promising opportunities for cryogenic ferroelectrics.
非易失性低温存储器对于实现高能效、大规模量子计算系统至关重要。在这封信中，我们评估了以化合物半导体（InAs）为底电极的基于 HZO 的铁电电容器（FeCAP）的低温性能。我们证明，与室温相比，通过在唤醒过程中增加电压，可在 14 K 温度下获得近乎相同的残余极化。我们在低至 50 K 的温度下研究了 FeCAP 的开关动态，并通过成核限制开关模型分析了测量数据。这些结果以及在低温条件下增强的耐久性为低温铁电带来了大好机会。
{"title":"Cryogenic Ferroelectricity of HZO Capacitors on a III–V Semiconductor","authors":"Mamidala Karthik Ram;Hannes Dahlberg;Lars-Erik Wernersson","doi":"10.1109/LED.2024.3448378","DOIUrl":"10.1109/LED.2024.3448378","url":null,"abstract":"Non-volatile cryogenic memories are crucial for realizing energy-efficient and scaled quantum computing systems. In this letter, we evaluate the cryogenic performance of an HZO-based ferroelectric capacitor (FeCAP) with a compound semiconductor (InAs) as the bottom electrode. We demonstrate that near identical remnant polarization can be obtained at 14 K compared to room temperature by increasing the voltage during the wake-up process. The switching dynamics of the FeCAP are studied at temperatures as low as 50 K with measured data analyzed by the nucleation-limited switching model. These results together with the increased endurance at cryogenic temperatures present promising opportunities for cryogenic ferroelectrics.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1827-1830"},"PeriodicalIF":4.1,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142227511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To assess the reliability of GaN power transistors, off-state leakage characteristic is measured for Schottky p-GaN gate HEMTs under negative gate biases. It is found that the drain leakage current increases abnormally with the decrease of gate-to-source voltage, which is contrary to the situation in normally-on GaN MISHEMTs. It is proposed that the phenomenon is caused by the combined effect of source electrostatic interaction and source-connected field plate, which enhance the electric field near the gate edge on the drain side at negative gate bias. And such effect is more severe in the GaN HEMTs with a p-GaN gate stack due to geometry effect, which enhance the source electrostatic interaction.
为了评估氮化镓功率晶体管的可靠性，我们测量了负栅极偏压下肖特基 p-GaN 栅极 HEMT 的离态漏电流特性。结果发现，漏极漏电流随着栅极至源极电压的降低而异常增大，这与正常导通的 GaN MISHEMT 的情况相反。研究人员认为，这种现象是源极静电相互作用和源极连接场板的共同作用造成的，在负栅偏压下，源极静电相互作用会增强漏极侧栅极边缘附近的电场。由于几何效应，这种效应在具有 p-GaN 栅极堆栈的 GaN HEMT 中更为严重，从而增强了源静电相互作用。
{"title":"Effect of Source Electrostatic Interaction on the Off-State Leakage Current of p-GaN Gate HEMTs","authors":"Jiaojiao Song;Maojun Wang;Jin Wei;Zetao Fan;Jiaxin Zhang;Han Yang;Pengfei Wang;Bing Xie;Cheng Li;Li Yuan;Bo Shen","doi":"10.1109/LED.2024.3447236","DOIUrl":"https://doi.org/10.1109/LED.2024.3447236","url":null,"abstract":"To assess the reliability of GaN power transistors, off-state leakage characteristic is measured for Schottky p-GaN gate HEMTs under negative gate biases. It is found that the drain leakage current increases abnormally with the decrease of gate-to-source voltage, which is contrary to the situation in normally-on GaN MISHEMTs. It is proposed that the phenomenon is caused by the combined effect of source electrostatic interaction and source-connected field plate, which enhance the electric field near the gate edge on the drain side at negative gate bias. And such effect is more severe in the GaN HEMTs with a p-GaN gate stack due to geometry effect, which enhance the source electrostatic interaction.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1728-1731"},"PeriodicalIF":4.1,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142383455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three-dimensional (3D) perovskite with good charge transport and structural stability, showing application potential in light-emitting diodes (LED). However, the grain size of 3D perovskite in the liquid-solid process is relatively large and large amounts of defects on the grain surface and grain boundaries were produced, leading to a reduced efficiency of LED devices. Herein, we report a dual rivet strategy to regulate perovskite growth kinetics in liquid-solid processes by introducing 3-(Hydroxy(phenyl) phosphoryl)propanoic acid (CEPPA) into the perovskite precursor. CEPPA has a dual coordination functional group, which can simultaneously form covalent bonds with two uncoordinated lead atoms on the surface of perovskite, effectively controlling the crystals during the liquid-solid process and obtaining high-quality perovskite films with smaller grain sizes. Moreover, the coordination of CEPPA with Pb atoms on the surface of perovskite can effectively reduce film defects and thus improve the efficiency of radiation recombination. The functional molecule double rivet strategy is beneficial to the preparation of high-performance 3D perovskite LEDs with peak external quantum efficiencies exceeding 20% and with a maximum brightness of 17795 cd m -2 .
三维（3D）透晶石具有良好的电荷传输和结构稳定性，在发光二极管（LED）中具有应用潜力。然而，在液固工艺中，三维包晶的晶粒尺寸相对较大，晶面和晶界上会产生大量缺陷，导致 LED 器件的效率降低。在此，我们报告了一种双铆钉策略，通过在包晶前驱体中引入 3-（羟基（苯基）磷酰）丙酸（CEPPA）来调节包晶在液固工艺中的生长动力学。CEPPA 具有双配位官能团，可同时与包晶表面的两个非配位铅原子形成共价键，从而在液固过程中有效控制晶体，获得晶粒尺寸更小的高质量包晶薄膜。此外，CEPPA 与包晶表面的铅原子配位可有效减少薄膜缺陷，从而提高辐射重组效率。功能分子双铆钉策略有利于制备峰值外部量子效率超过 20%、最大亮度达到 17795 cd m-2 的高性能三维包晶发光二极管。
{"title":"Multifunctional Molecule-Assisted Crystallization Control for Efficient Perovskite Light-Emitting Diodes","authors":"Wanxing Yang;Chengxi Zhang;Jun Dai;Xuyong Yang;Xiaoyang Zhang;Tong Zhang","doi":"10.1109/LED.2024.3446993","DOIUrl":"https://doi.org/10.1109/LED.2024.3446993","url":null,"abstract":"Three-dimensional (3D) perovskite with good charge transport and structural stability, showing application potential in light-emitting diodes (LED). However, the grain size of 3D perovskite in the liquid-solid process is relatively large and large amounts of defects on the grain surface and grain boundaries were produced, leading to a reduced efficiency of LED devices. Herein, we report a dual rivet strategy to regulate perovskite growth kinetics in liquid-solid processes by introducing 3-(Hydroxy(phenyl) phosphoryl)propanoic acid (CEPPA) into the perovskite precursor. CEPPA has a dual coordination functional group, which can simultaneously form covalent bonds with two uncoordinated lead atoms on the surface of perovskite, effectively controlling the crystals during the liquid-solid process and obtaining high-quality perovskite films with smaller grain sizes. Moreover, the coordination of CEPPA with Pb atoms on the surface of perovskite can effectively reduce film defects and thus improve the efficiency of radiation recombination. The functional molecule double rivet strategy is beneficial to the preparation of high-performance 3D perovskite LEDs with peak external quantum efficiencies exceeding 20% and with a maximum brightness of 17795 cd m\u0000<sup>-2</sup>\u0000.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1895-1898"},"PeriodicalIF":4.1,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A reconfigurable interconnection technology is proposed in this letter for chiplet integrated systems, with conductive bridging random access memory (CBRAM) based switch matrix. The switch matrix with a crossbar structure is implemented easily by spin-coating process, compatible with the packaging technology of high-resistivity silicon interposer. The equivalent circuit model is established. A ${2}times {2}$ switch matrix prototype is developed with the insertion loss below 3.8 dB for arbitrary transmission path from DC to 67 GHz. The fabricated ${4}times {4}$ switch matrix prototype achieves the 3-dB bandwidth over DC to 30 GHz. Under the data rate of 30 Gbps and the rise time of 15 ps, the near- and far-end crosstalks are all below 3% of the input signal swing, the eye height is 71%, and the root-mean-square jitter is only 1.26 ps. Noting that the CBRAM-based switch matrix consumes no static power, the proposed reconfigurable passive silicon interposer is a promising technology for flexible chiplet integration.
{"title":"Conductive Bridging Random Access Memory-Based Switch Matrix for Reconfigurable Interconnection of Chiplet Integration","authors":"Zong-Rui Xu;Zhi-Yi Zhang;Zhangchen Hou;Aiping Cao;Zhigao Hu;Lin-Sheng Wu","doi":"10.1109/LED.2024.3447063","DOIUrl":"https://doi.org/10.1109/LED.2024.3447063","url":null,"abstract":"A reconfigurable interconnection technology is proposed in this letter for chiplet integrated systems, with conductive bridging random access memory (CBRAM) based switch matrix. The switch matrix with a crossbar structure is implemented easily by spin-coating process, compatible with the packaging technology of high-resistivity silicon interposer. The equivalent circuit model is established. A \u0000<inline-formula> <tex-math>${2}times {2}$ </tex-math></inline-formula>\u0000 switch matrix prototype is developed with the insertion loss below 3.8 dB for arbitrary transmission path from DC to 67 GHz. The fabricated \u0000<inline-formula> <tex-math>${4}times {4}$ </tex-math></inline-formula>\u0000 switch matrix prototype achieves the 3-dB bandwidth over DC to 30 GHz. Under the data rate of 30 Gbps and the rise time of 15 ps, the near- and far-end crosstalks are all below 3% of the input signal swing, the eye height is 71%, and the root-mean-square jitter is only 1.26 ps. Noting that the CBRAM-based switch matrix consumes no static power, the proposed reconfigurable passive silicon interposer is a promising technology for flexible chiplet integration.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1823-1826"},"PeriodicalIF":4.1,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Herein, In 2 O 3 /Al 2 O 3 /Y 6 transistors exhibiting bidirectional photoresponse (BPR) characteristic were fabricated. By utilizing this feature, XOR optoelectronic logic gate was successfully designed and applied in near-infrared (NIR) image encryption. Furthermore, an identity verification was proposed by binary encoding the current from different NIR and ultraviolet (UV) illumination combinations. Finally, a photoelectric watermark scheme responsive to UV light was proposed leveraging NIR’s non-volatile programming. The integration of a secure sensor strategy that encompasses image encryption, identity verification, and photoelectric watermark addresses the need for enhanced data protection and offering a comprehensive security solution for the Internet of Things (IoT).
{"title":"All-in-One of Image Encryption, Identity Verification, and Photoelectric Watermark Based on Bidirectionally Photoresponsive Transistors","authors":"Tonglong Zeng;Dingwei Li;Rui Wang;Xiaotao Jing;Wanlin Zhang;Dinghan Zhang;Chen Yan;Peilin Zhang;Xiaohua Ma;Bowen Zhu;Hong Wang;Yue Hao","doi":"10.1109/LED.2024.3446872","DOIUrl":"https://doi.org/10.1109/LED.2024.3446872","url":null,"abstract":"Herein, In\u0000<sub>2</sub>\u0000O\u0000<sub>3</sub>\u0000/Al\u0000<sub>2</sub>\u0000O\u0000<sub>3</sub>\u0000/Y\u0000<sub>6</sub>\u0000 transistors exhibiting bidirectional photoresponse (BPR) characteristic were fabricated. By utilizing this feature, XOR optoelectronic logic gate was successfully designed and applied in near-infrared (NIR) image encryption. Furthermore, an identity verification was proposed by binary encoding the current from different NIR and ultraviolet (UV) illumination combinations. Finally, a photoelectric watermark scheme responsive to UV light was proposed leveraging NIR’s non-volatile programming. The integration of a secure sensor strategy that encompasses image encryption, identity verification, and photoelectric watermark addresses the need for enhanced data protection and offering a comprehensive security solution for the Internet of Things (IoT).","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1859-1862"},"PeriodicalIF":4.1,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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