Pub Date : 2024-08-26DOI: 10.1109/LED.2024.3440825
{"title":"IEEE Electron Device Letters Information for Authors","authors":"","doi":"10.1109/LED.2024.3440825","DOIUrl":"https://doi.org/10.1109/LED.2024.3440825","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 9","pages":"1680-1680"},"PeriodicalIF":4.1,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10648921","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142077621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-23DOI: 10.1109/LED.2024.3448508
Kyeongwoo Jang;Yuseong Jang;Soobin An;Soo-Yeon Lee
We present an in-situ IGZO/ITON heterojunction phototransistor with exceptional performance under visible light. By introducing a low bandgap of ITON as a light absorption layer, the responsivity of 30.2 A/W, photosensitivity of $6.3times 10^{{4}}$ , and detectivity of $4.8times 10^{{13}}$ Jones under red light illumination (635nm). Because the ITON was deposited by the sputtering with controlling Ar/N 2 gas mixture condition immediately after IGZO deposition without breaking the vacuum, the suggested structure is not only compatible with the conventional large-area manufacturing process but also minimizes the interfacial defects between IGZO and ITON.
{"title":"In-Situ IGZO/ITON Heterostructure Phototransistor to Enhance Visible Light Detection","authors":"Kyeongwoo Jang;Yuseong Jang;Soobin An;Soo-Yeon Lee","doi":"10.1109/LED.2024.3448508","DOIUrl":"10.1109/LED.2024.3448508","url":null,"abstract":"We present an in-situ IGZO/ITON heterojunction phototransistor with exceptional performance under visible light. By introducing a low bandgap of ITON as a light absorption layer, the responsivity of 30.2 A/W, photosensitivity of \u0000<inline-formula> <tex-math>$6.3times 10^{{4}}$ </tex-math></inline-formula>\u0000, and detectivity of \u0000<inline-formula> <tex-math>$4.8times 10^{{13}}$ </tex-math></inline-formula>\u0000 Jones under red light illumination (635nm). Because the ITON was deposited by the sputtering with controlling Ar/N\u0000<sub>2</sub>\u0000 gas mixture condition immediately after IGZO deposition without breaking the vacuum, the suggested structure is not only compatible with the conventional large-area manufacturing process but also minimizes the interfacial defects between IGZO and ITON.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1839-1842"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142227887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Herein, thin-film transistors (TFT) with ITO as the n-channel active layer were prepared on transparent substrates by magnetron sputtering at room temperature. The use of chitosan with an electric-double-layer (EDL) effect as the gate dielectric enabled low power consumption. The relaxation phenomenon induced by ion migration was effectively utilized, enabling ITO synaptic transistors to emulate various synaptic behaviors, including excitatory postsynaptic currents (EPSC) and inhibitory postsynaptic currents (IPSC), paired pulse depression (PPD), long term depression (LTD), and short term memory (STM) to long term memory (LTM) transition, highlight the potential of ITO thin film transistors in emulating complex neural processes. Additionally, the devices display frequency dependent capacitance characteristics, indicating suitability for low-pass filter applications in signal processing. The ITO thin film synaptic transistors with paired pulse depressed behavior represent a promising potential for advancing neuromorphic computing systems, offering avenues for further research and development in synaptic bionics, emulating human learning and memory, and neural chips.
在此，通过磁控溅射法在室温下在透明衬底上制备了以 ITO 为 n 沟道活性层的薄膜晶体管 (TFT)。使用具有双电层效应（EDL）的壳聚糖作为栅极电介质可实现低功耗。离子迁移引起的弛豫现象得到了有效利用，从而使 ITO 突触晶体管能够模拟各种突触行为，包括兴奋性突触后电流（EPSC）和抑制性突触后电流（IPSC）、成对脉冲抑制（PPD）、长期抑制（LTD）以及从短期记忆（STM）到长期记忆（LTM）的转变，凸显了 ITO 薄膜晶体管在模拟复杂神经过程方面的潜力。此外，这些器件还显示出与频率相关的电容特性，表明其适用于信号处理中的低通滤波器应用。具有成对脉冲抑制行为的 ITO 薄膜突触晶体管代表了推进神经形态计算系统的巨大潜力，为突触仿生学、模拟人类学习和记忆以及神经芯片的进一步研究和开发提供了途径。
{"title":"Low-Voltage ITO Depressed Synaptic Transistors for Neuromorphic Application","authors":"Pengfei Chen;Wei Dou;Yuling Peng;Xiaodong Xu;Yingjie Ai;Weichang Zhou;Dongsheng Tang","doi":"10.1109/LED.2024.3448367","DOIUrl":"10.1109/LED.2024.3448367","url":null,"abstract":"Herein, thin-film transistors (TFT) with ITO as the n-channel active layer were prepared on transparent substrates by magnetron sputtering at room temperature. The use of chitosan with an electric-double-layer (EDL) effect as the gate dielectric enabled low power consumption. The relaxation phenomenon induced by ion migration was effectively utilized, enabling ITO synaptic transistors to emulate various synaptic behaviors, including excitatory postsynaptic currents (EPSC) and inhibitory postsynaptic currents (IPSC), paired pulse depression (PPD), long term depression (LTD), and short term memory (STM) to long term memory (LTM) transition, highlight the potential of ITO thin film transistors in emulating complex neural processes. Additionally, the devices display frequency dependent capacitance characteristics, indicating suitability for low-pass filter applications in signal processing. The ITO thin film synaptic transistors with paired pulse depressed behavior represent a promising potential for advancing neuromorphic computing systems, offering avenues for further research and development in synaptic bionics, emulating human learning and memory, and neural chips.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1863-1866"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, we experimentally demonstrated a state-of-the-art three-dimensional (3-D) self-aligned stacked hetero-oriented p-type Ge rectangle nanowire (NW) gate-all-around field-effect transistor (GAAFET) on n-type Ge diamond NW GAAFET of single-gate complementary FET (CFET). Anisotropic and isotropic dry etching processes are used to form the stacked NWs. Using Ge as the channel material with its optimal surface orientations of (111) for diamond NW nFET and (110) for rectangle NW pFET can enhance the device performance. The 3-D TCAD simulation indicates outperformance of the CFET device for 1-nm node applications. The proposed CFET structure can simplify the manufacturing technology and be fully compatible with current CMOS technology platform.
在这项研究中，我们通过实验展示了一种最先进的三维（3-D）自对准堆叠异取向 p 型 Ge 矩形纳米线（NW）栅全包围场效应晶体管（GAAFET），它位于单栅互补场效应晶体管（CFET）的 n 型 Ge 金刚石 NW GAAFET 上。采用各向异性和各向同性的干法蚀刻工艺来形成叠层 NW。使用 Ge 作为沟道材料，其最佳表面取向为金刚石 NW nFET 的 (111) 和矩形 NW pFET 的 (110)，可以提高器件性能。三维 TCAD 仿真表明，1 纳米节点应用中的 CFET 器件性能更优。所提出的 CFET 结构可以简化制造技术，并与当前的 CMOS 技术平台完全兼容。
{"title":"3-D Self-Aligned Stacked Ge Nanowires Complementary FET Featuring Single Gate Simple Process","authors":"Yi-Wen Lin;Bo-An Chen;Kai-Wei Huang;Bo-Xu Chen;Guang-Li Luo;Yung-Chun Wu;Fu-Ju Hou","doi":"10.1109/LED.2024.3448477","DOIUrl":"10.1109/LED.2024.3448477","url":null,"abstract":"In this study, we experimentally demonstrated a state-of-the-art three-dimensional (3-D) self-aligned stacked hetero-oriented p-type Ge rectangle nanowire (NW) gate-all-around field-effect transistor (GAAFET) on n-type Ge diamond NW GAAFET of single-gate complementary FET (CFET). Anisotropic and isotropic dry etching processes are used to form the stacked NWs. Using Ge as the channel material with its optimal surface orientations of (111) for diamond NW nFET and (110) for rectangle NW pFET can enhance the device performance. The 3-D TCAD simulation indicates outperformance of the CFET device for 1-nm node applications. The proposed CFET structure can simplify the manufacturing technology and be fully compatible with current CMOS technology platform.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"2013-2016"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-23DOI: 10.1109/LED.2024.3449150
Woo Young Park;In Gyu Lee;Young Uk Ryu;Woojin Jeon
A novel approach using a controlled interfacial layer (CIL) to modulate HfO 2 thin film crystallization in ZrO 2 /HfO 2 /ZrO 2 (ZHZ) structures was investigated. Through X-ray diffraction and high-resolution transmission electron microscopy, the CIL suppresses undesired monoclinic phases in HfO 2 , favoring the desired tetragonal phase for high dielectric constants. Precise control of HfO 2 thickness via CIL maintains constant dielectric constants across ZHZ structures, addressing challenges of fluctuating constants. This study highlights CIL’s potential in tailored ZrO 2 /HfO 2 engineering for electronics, providing insights into crystallization behavior and paving the way for advanced device applications.
{"title":"Introducing a Controlled Interfacial Layer to Enhance the Template Effect of ZrO₂ in the ZrO₂/HfO₂/ZrO₂ Structure","authors":"Woo Young Park;In Gyu Lee;Young Uk Ryu;Woojin Jeon","doi":"10.1109/LED.2024.3449150","DOIUrl":"10.1109/LED.2024.3449150","url":null,"abstract":"A novel approach using a controlled interfacial layer (CIL) to modulate HfO\u0000<sub>2</sub>\u0000 thin film crystallization in ZrO\u0000<sub>2</sub>\u0000/HfO\u0000<sub>2</sub>\u0000/ZrO\u0000<sub>2</sub>\u0000 (ZHZ) structures was investigated. Through X-ray diffraction and high-resolution transmission electron microscopy, the CIL suppresses undesired monoclinic phases in HfO\u0000<sub>2</sub>\u0000, favoring the desired tetragonal phase for high dielectric constants. Precise control of HfO\u0000<sub>2</sub>\u0000 thickness via CIL maintains constant dielectric constants across ZHZ structures, addressing challenges of fluctuating constants. This study highlights CIL’s potential in tailored ZrO\u0000<sub>2</sub>\u0000/HfO\u0000<sub>2</sub>\u0000 engineering for electronics, providing insights into crystallization behavior and paving the way for advanced device applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1808-1810"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-23DOI: 10.1109/LED.2024.3449243
Seung Won Lee;Hak Jun Ban;Jong Kyung Park;Dong Jin Ji;Seul Ki Hong
In FinFETs, the shape of the source/drain is crucial for performance, as it supplies charge and induces stress in the channel. Due to the 3D structure and numerous components of FinFETs, experimentally analyzing the performance impact of source/drain shapes is time-consuming and costly. This study employs machine learning and the SHAP method to analyze the influence of source/drain shapes on FinFET performance, focusing on growth height and lateral growth depth. These factors’ effects on key performance indicators such as on-current and threshold voltage are confirmed. SHAP analysis further substantiates the results’ reliability and significance. Our findings contribute to understanding and improving the performance of increasingly complex and miniaturized semiconductor device structures.
{"title":"Analyzing the Influence of Source/Drain Growth Height and Lateral Growth Depth in FinFETs Through XGBoost and SHAP","authors":"Seung Won Lee;Hak Jun Ban;Jong Kyung Park;Dong Jin Ji;Seul Ki Hong","doi":"10.1109/LED.2024.3449243","DOIUrl":"10.1109/LED.2024.3449243","url":null,"abstract":"In FinFETs, the shape of the source/drain is crucial for performance, as it supplies charge and induces stress in the channel. Due to the 3D structure and numerous components of FinFETs, experimentally analyzing the performance impact of source/drain shapes is time-consuming and costly. This study employs machine learning and the SHAP method to analyze the influence of source/drain shapes on FinFET performance, focusing on growth height and lateral growth depth. These factors’ effects on key performance indicators such as on-current and threshold voltage are confirmed. SHAP analysis further substantiates the results’ reliability and significance. Our findings contribute to understanding and improving the performance of increasingly complex and miniaturized semiconductor device structures.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1714-1716"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We develop a highly stretchable circuit by utilizing serpentine interconnects made of high-elasticity Cu-Be alloy. An elastic equivalent model of serpentine interconnect is used to optimize the geometric parameters, thereby enhancing its mechanical compatibility with the soft substrate. Furthermore, we propose a rapid fabrication method of highly stretchable circuits through the laser cutting and film transfer techniques. The results indicate that the elastic strain limit of the Cu-Be alloy serpentine interconnect is 4 times that of the Cu interconnect. The Cu-Be alloy serpentine circuit with optimized geometric parameters exhibits an excellent resistance stability under 1000 cycles of tensile testing at 90% strain without local delamination or failure. The light emitting diode (LED) array demonstrates an ultrahigh tensile strain limit of up to 200%. The proposed method can provide a novel and promising way for the fabrication of highly stretchable circuits for future wearable electronic devices.
{"title":"A Highly Stretchable Circuit Based on Metal-Elastomer Composite","authors":"Fankai Kong;Hu Tang;Peng Liu;Xiao Liu;Jiwei Zhao;Junjian Li;Jue Peng","doi":"10.1109/LED.2024.3449153","DOIUrl":"10.1109/LED.2024.3449153","url":null,"abstract":"We develop a highly stretchable circuit by utilizing serpentine interconnects made of high-elasticity Cu-Be alloy. An elastic equivalent model of serpentine interconnect is used to optimize the geometric parameters, thereby enhancing its mechanical compatibility with the soft substrate. Furthermore, we propose a rapid fabrication method of highly stretchable circuits through the laser cutting and film transfer techniques. The results indicate that the elastic strain limit of the Cu-Be alloy serpentine interconnect is 4 times that of the Cu interconnect. The Cu-Be alloy serpentine circuit with optimized geometric parameters exhibits an excellent resistance stability under 1000 cycles of tensile testing at 90% strain without local delamination or failure. The light emitting diode (LED) array demonstrates an ultrahigh tensile strain limit of up to 200%. The proposed method can provide a novel and promising way for the fabrication of highly stretchable circuits for future wearable electronic devices.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1937-1940"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The directly coupled hydrogen-terminated diamond FET logic (DCHDFL) circuit is fabricated. The E-mode and D-mode FETs are assigned as driver and load devices of the DCHDFL circuit to achieve inversion characteristics. The E-mode FET showcases high I DSmax of 53.3mA/mm, V TH of -0.8 V, low SS of 98 mV/dec and on/off ratio of 10 9 , which enable input/output logic level matching with a low drive/load ratio of 1.0. The peak gain of circuit increases from 12.57 to 36.3 V/V with V DD ranging from -5 V to -25 V, which is the highest gain achieved of diamond inverters, due to the high on/off ratio and low SS of E-mode FET. This circuit exhibits proper functions up to 200 °C, demonstrating a good thermal stability. These results indicate the great potential and possibilities for diamond smart power integrated circuit application.
制作了直接耦合氢端金刚石场效应晶体管逻辑（DCHDFL）电路。E 模式和 D 模式场效应晶体管分别用作 DCHDFL 电路的驱动器和负载器件，以实现反相特性。E 模式场效应晶体管具有 53.3mA/mm 的高 IDSmax、-0.8 V 的 VTH、98 mV/dec 的低 SS 和 109 的导通/关断比，从而能以 1.0 的低驱动/负载比实现输入/输出逻辑电平匹配。在 VDD 为 -5 V 至 -25 V 时，电路的峰值增益从 12.57 V/V 增至 36.3 V/V，这是菱形逆变器中实现的最高增益，原因是 E 模式场效应晶体管具有高导通/关断比和低 SS。该电路在高达 200 °C 的温度下仍能正常工作，显示出良好的热稳定性。这些结果表明了金刚石智能功率集成电路应用的巨大潜力和可能性。
{"title":"Directly Coupled Hydrogenated Diamond FET Logic Circuit With High Voltage Gain","authors":"Yuesong Liang;Wei Wang;Fang Lin;Tianlin Niu;Genqiang Chen;Fei Wang;Qi Li;Shi He;Minghui Zhang;Yanfeng Wang;Feng Wen;Hong-Xing Wang","doi":"10.1109/LED.2024.3448363","DOIUrl":"10.1109/LED.2024.3448363","url":null,"abstract":"The directly coupled hydrogen-terminated diamond FET logic (DCHDFL) circuit is fabricated. The E-mode and D-mode FETs are assigned as driver and load devices of the DCHDFL circuit to achieve inversion characteristics. The E-mode FET showcases high I\u0000<sub>DSmax</sub>\u0000 of 53.3mA/mm, V\u0000<sub>TH</sub>\u0000 of -0.8 V, low SS of 98 mV/dec and on/off ratio of 10\u0000<sup>9</sup>\u0000, which enable input/output logic level matching with a low drive/load ratio of 1.0. The peak gain of circuit increases from 12.57 to 36.3 V/V with V\u0000<sub>DD</sub>\u0000 ranging from -5 V to -25 V, which is the highest gain achieved of diamond inverters, due to the high on/off ratio and low SS of E-mode FET. This circuit exhibits proper functions up to 200 °C, demonstrating a good thermal stability. These results indicate the great potential and possibilities for diamond smart power integrated circuit application.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1698-1701"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-23DOI: 10.1109/LED.2024.3448452
Z. X. Su;J. C. Cai;P. C. Yin;D. C. Chen;J. Zhang;X. K. Zhang;C. Zhang;L. Zeng;J. Xu;L. N. Yue;H. R. Yin;Y. Xu;G. Q. Zhao;W. X. Wang;Y. Y. Wei
During the test of an S-band multibeam klystron (MBK) resonant cavity, an interesting experimental phenomenon was observed: the measured ohmic quality factor ( ${Q}_{{0}}$ ) of the cavity was surprisingly low (around 200, design value of 5090). This prompted an in-depth investigation, revealing that the low ${Q}_{{0}}$ was due to the presence of a small gap on the perimeter of the resonant cavity, which resulted from an inadvertent mechanical design. The topology of this assembly gap was similar to an extremely thin coaxial line. To further investigate the impact of such assembly gap, theoretical and numerical models were developed to quantitatively analyze the effect of concentric/eccentric assembly gap on the cavity ${Q}_{{0}}$ , field asymmetry, the shunt impedance, mode competition, etc. The analysis indicates that the primary factor affecting ${Q}_{{0}}$ is the length of the small gap. The concentricity and width mainly influence the symmetry and shunt impedance, respectively. The analysis showed good agreement with the experimental results. Based on the above findings, a new approach was proposed to conveniently reduce the ${Q}_{{0}}$ of the resonant cavity via employing an appropriately long, relatively narrow gap (1/1000 of its radii, to ensure concentricity even in the worst scenario), thereby facilitating the development of broadband klystrons.
{"title":"Investigation on the Effects of Assembly Gaps in the Resonant Cavity of Klystrons","authors":"Z. X. Su;J. C. Cai;P. C. Yin;D. C. Chen;J. Zhang;X. K. Zhang;C. Zhang;L. Zeng;J. Xu;L. N. Yue;H. R. Yin;Y. Xu;G. Q. Zhao;W. X. Wang;Y. Y. Wei","doi":"10.1109/LED.2024.3448452","DOIUrl":"10.1109/LED.2024.3448452","url":null,"abstract":"During the test of an S-band multibeam klystron (MBK) resonant cavity, an interesting experimental phenomenon was observed: the measured ohmic quality factor (\u0000<inline-formula> <tex-math>${Q}_{{0}}$ </tex-math></inline-formula>\u0000) of the cavity was surprisingly low (around 200, design value of 5090). This prompted an in-depth investigation, revealing that the low \u0000<inline-formula> <tex-math>${Q}_{{0}}$ </tex-math></inline-formula>\u0000 was due to the presence of a small gap on the perimeter of the resonant cavity, which resulted from an inadvertent mechanical design. The topology of this assembly gap was similar to an extremely thin coaxial line. To further investigate the impact of such assembly gap, theoretical and numerical models were developed to quantitatively analyze the effect of concentric/eccentric assembly gap on the cavity \u0000<inline-formula> <tex-math>${Q}_{{0}}$ </tex-math></inline-formula>\u0000, field asymmetry, the shunt impedance, mode competition, etc. The analysis indicates that the primary factor affecting \u0000<inline-formula> <tex-math>${Q}_{{0}}$ </tex-math></inline-formula>\u0000 is the length of the small gap. The concentricity and width mainly influence the symmetry and shunt impedance, respectively. The analysis showed good agreement with the experimental results. Based on the above findings, a new approach was proposed to conveniently reduce the \u0000<inline-formula> <tex-math>${Q}_{{0}}$ </tex-math></inline-formula>\u0000 of the resonant cavity via employing an appropriately long, relatively narrow gap (1/1000 of its radii, to ensure concentricity even in the worst scenario), thereby facilitating the development of broadband klystrons.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1985-1988"},"PeriodicalIF":4.1,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142222931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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