In this study, we demonstrate large-area, high-performance $beta $ -Ga2O3-based heterojunction PN diodes (PNDs) featuring a p-type chromium oxide (p-Cr2${mathrm {O}}_{{3}}text {)}$ layer deposited via magnetron sputtering and an optimized slanted-mesa edge termination (ET) for electric field management. The fabricated diodes exhibit an active area of 9 mm2 and achieve state-of-the-art electrical characteristics, including a high breakdown voltage (BV) of 1.78 kV, a forward current (IF) of 120 A, and an ultralow on-resistance (${mathrm {R}}_{text {on}}text {)}$ of 69 m$Omega $ . Notably, the slanted-mesa-ET PNDs show only a marginal reduction in forward current compared to their non-ET counterparts, while achieving a 36% enhancement in BV. This results in a power figure of merit (PFOM) of 0.511 GW/cm2, the highest reported to date for any large-area (>1 mm${}^{{2}}text {)} beta $ -Ga2O3 diode. This exceptional performance underscores the viability of $beta $ -Ga2O3 for next-generation high-power electronics, particularly through the introduction of novel p-type materials and edge termination designs.
在这项研究中，我们展示了大面积，高性能$beta $ - ga2o3基异质结PN二极管（PNDs），该二极管具有通过磁控溅射沉积的p型氧化铬（p-Cr2 ${mathrm {O}}_{{3}}text {)}$）层和优化的倾斜台面边缘端接（ET）用于电场管理。制造的二极管具有9 mm2的有效面积，并实现了最先进的电气特性，包括1.78 kV的高击穿电压（BV）， 120 a的正向电流（IF）和超低导通电阻（${mathrm {R}}_{text {on}}text {)}$ 69 m $Omega $）。值得注意的是，与非et的pnd相比，倾斜台面- et pnd仅显示正向电流的边际减少，而达到36% enhancement in BV. This results in a power figure of merit (PFOM) of 0.511 GW/cm2, the highest reported to date for any large-area (>1 mm ${}^{{2}}text {)} beta $ -Ga2O3 diode. This exceptional performance underscores the viability of $beta $ -Ga2O3 for next-generation high-power electronics, particularly through the introduction of novel p-type materials and edge termination designs.
{"title":"120 A/1.78 kV p-Cr2O3/n-β -Ga2O3 Heterojunction PN Diodes With Slanted Mesa Edge Termination","authors":"Yitao Feng;Hong Zhou;Junyi Ma;Hao Fang;Xiaorong Zhang;Yanbo Chen;Guotao Tian;Jun Yuan;Ruoshi Peng;Shaodong Xu;Yue Hao;Jincheng Zhang","doi":"10.1109/LED.2025.3598936","DOIUrl":"https://doi.org/10.1109/LED.2025.3598936","url":null,"abstract":"In this study, we demonstrate large-area, high-performance <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3-based heterojunction PN diodes (PNDs) featuring a p-type chromium oxide (p-Cr2<inline-formula> <tex-math>${mathrm {O}}_{{3}}text {)}$ </tex-math></inline-formula> layer deposited via magnetron sputtering and an optimized slanted-mesa edge termination (ET) for electric field management. The fabricated diodes exhibit an active area of 9 mm2 and achieve state-of-the-art electrical characteristics, including a high breakdown voltage (BV) of 1.78 kV, a forward current (IF) of 120 A, and an ultralow on-resistance (<inline-formula> <tex-math>${mathrm {R}}_{text {on}}text {)}$ </tex-math></inline-formula> of 69 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>. Notably, the slanted-mesa-ET PNDs show only a marginal reduction in forward current compared to their non-ET counterparts, while achieving a 36% enhancement in BV. This results in a power figure of merit (PFOM) of 0.511 GW/cm2, the highest reported to date for any large-area (>1 mm<inline-formula> <tex-math>${}^{{2}}text {)} beta $ </tex-math></inline-formula>-Ga2O3 diode. This exceptional performance underscores the viability of <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 for next-generation high-power electronics, particularly through the introduction of novel p-type materials and edge termination designs.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1705-1708"},"PeriodicalIF":4.5,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To address the challenges of low data processing efficiency, spatiotemporal information separation, and high energy consumption in traditional machine vision systems, this work proposes a bio-inspired ferroelectric adaptive transistor based on annealing-free HZO ferroelectric films. The FeTFT achieves the lowest fabrication temperature while demonstrating exceptional performance with a high ON/OFF ratio of ${3}.{8}times {10} ^{{9}}$ and a large memory window of 2.86 V. The FeTFT exhibits bio-synaptic optoelectronic co-response characteristics and implements biological adaptive functions through dynamic reconfiguration of ferroelectric polarization. By constructing a fire vision system based on the spatiotemporal fusion mechanism, the FeTFT achieves 100% motion direction recognition accuracy and three-level speed classification capability. This research establishes a novel paradigm for developing low-power, dynamically adaptable bio-inspired intelligent vision systems.
{"title":"Bio-Inspired Ferroelectric Adaptive Transistors for Intelligent Vision Systems","authors":"Yongkai Liu;Aolin Yuan;Ruihong Yuan;Pei Liu;Zhe Qu;Kangli Xu;Jiajie Yu;Zhenhai Li;Jialin Meng;Hao Zhu;Qingqing Sun;David Wei Zhang;Tianyu Wang;Lin Chen","doi":"10.1109/LED.2025.3597286","DOIUrl":"https://doi.org/10.1109/LED.2025.3597286","url":null,"abstract":"To address the challenges of low data processing efficiency, spatiotemporal information separation, and high energy consumption in traditional machine vision systems, this work proposes a bio-inspired ferroelectric adaptive transistor based on annealing-free HZO ferroelectric films. The FeTFT achieves the lowest fabrication temperature while demonstrating exceptional performance with a high ON/OFF ratio of <inline-formula> <tex-math>${3}.{8}times {10} ^{{9}}$ </tex-math></inline-formula> and a large memory window of 2.86 V. The FeTFT exhibits bio-synaptic optoelectronic co-response characteristics and implements biological adaptive functions through dynamic reconfiguration of ferroelectric polarization. By constructing a fire vision system based on the spatiotemporal fusion mechanism, the FeTFT achieves 100% motion direction recognition accuracy and three-level speed classification capability. This research establishes a novel paradigm for developing low-power, dynamically adaptable bio-inspired intelligent vision systems.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1901-1904"},"PeriodicalIF":4.5,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-06DOI: 10.1109/LED.2025.3596445
Eungkyun Kim;Yu-Hsin Chen;Keisuke Shinohara;Thai-Son Nguyen;Jimy Encomendero;Debdeep Jena;Huili G. Xing
We demonstrate AlN/GaN/AlN pseudomorphic high electron mobility transistors (pHEMTs) on bulk AlN substrates with silicon $delta $ -doping near the bottom of the 20-nm GaN channel. Our recent studies on epitaxy and low-field transport show that $delta $ -doping in pseudomorphic AlN/GaN/AlN heterostructures increases electron mobility and two-dimensional electron gas density while preserving the advantages of the thin GaN channel, compared to undoped counterparts. In this work, we present DC and RF characteristics of these pHEMTs with PECVD SiN passivation, exhibiting an average ${f}_{text {T}} cdot {L}_{text {G}}$ product of 12.5 GHz$cdot mu $ m, a representative output power density of 4.2 W/mm with an associated power-added efficiency of 41.5% at 10 GHz.
我们在大块AlN衬底上展示了AlN/GaN/AlN伪晶高电子迁移率晶体管（pHEMTs），并在20nm GaN通道底部附近掺杂了硅$delta $。我们最近对外延和低场输运的研究表明，$delta $掺杂在伪晶AlN/GaN/AlN异质结构中增加了电子迁移率和二维电子气体密度，同时保留了薄GaN通道的优势。在这项工作中，我们展示了这些经PECVD SiN钝化的phemt的直流和射频特性，其平均${f}_{text {T}} cdot {L}_{text {G}}$积为12.5 GHz $cdot mu $ m，代表性输出功率密度为4.2 W/mm，相关功率附加效率为41.5% at 10 GHz.
{"title":"4.2 W/mm at 10 GHz in Silicon Delta-Doped AlN/GaN/AlN Pseudomorphic HEMTs With PECVD SiN Passivation","authors":"Eungkyun Kim;Yu-Hsin Chen;Keisuke Shinohara;Thai-Son Nguyen;Jimy Encomendero;Debdeep Jena;Huili G. Xing","doi":"10.1109/LED.2025.3596445","DOIUrl":"https://doi.org/10.1109/LED.2025.3596445","url":null,"abstract":"We demonstrate AlN/GaN/AlN pseudomorphic high electron mobility transistors (pHEMTs) on bulk AlN substrates with silicon <inline-formula> <tex-math>$delta $ </tex-math></inline-formula>-doping near the bottom of the 20-nm GaN channel. Our recent studies on epitaxy and low-field transport show that <inline-formula> <tex-math>$delta $ </tex-math></inline-formula>-doping in pseudomorphic AlN/GaN/AlN heterostructures increases electron mobility and two-dimensional electron gas density while preserving the advantages of the thin GaN channel, compared to undoped counterparts. In this work, we present DC and RF characteristics of these pHEMTs with PECVD SiN passivation, exhibiting an average <inline-formula> <tex-math>${f}_{text {T}} cdot {L}_{text {G}}$ </tex-math></inline-formula> product of 12.5 GHz<inline-formula> <tex-math>$cdot mu $ </tex-math></inline-formula>m, a representative output power density of 4.2 W/mm with an associated power-added efficiency of 41.5% at 10 GHz.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1729-1732"},"PeriodicalIF":4.5,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-05DOI: 10.1109/LED.2025.3595384
C. Power;M. Moras;A. Sokolov;C. Rohrbacher;X. Wu;S. V. Amitonov;I. Kriekouki;A. Aprà;P. Giounanlis;M. Asker;M. Harkin;P. Hanos-Puskai;P. Bisiaux;I. Bashir;D. Redmond;D. Leipold;R. B. Staszewski;B. Barry;N. Samkharadze;E. Blokhina
Confining electrons or holes in quantum dots formed in the channel of industry-standard fully depleted silicon-on-insulator CMOS structures is a promising approach to scalable qubit architectures. In this communication, we present measurement results of a commercial nanostructure fabricated using the GlobalFoundries 22FDXTM industrial process. These quantum dots are formed in the device channel between polysilicon gates. We report precise control over inter-dot coupling, bias triangle formation, and single electron box sensing in a commercial process for the first time.
{"title":"Fully-Tunable Tunnel-Coupled Quantum Dots and Charge Sensing in a Commercial 22 nm FD-SOI Process","authors":"C. Power;M. Moras;A. Sokolov;C. Rohrbacher;X. Wu;S. V. Amitonov;I. Kriekouki;A. Aprà;P. Giounanlis;M. Asker;M. Harkin;P. Hanos-Puskai;P. Bisiaux;I. Bashir;D. Redmond;D. Leipold;R. B. Staszewski;B. Barry;N. Samkharadze;E. Blokhina","doi":"10.1109/LED.2025.3595384","DOIUrl":"https://doi.org/10.1109/LED.2025.3595384","url":null,"abstract":"Confining electrons or holes in quantum dots formed in the channel of industry-standard fully depleted silicon-on-insulator CMOS structures is a promising approach to scalable qubit architectures. In this communication, we present measurement results of a commercial nanostructure fabricated using the GlobalFoundries 22FDXTM industrial process. These quantum dots are formed in the device channel between polysilicon gates. We report precise control over inter-dot coupling, bias triangle formation, and single electron box sensing in a commercial process for the first time.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1913-1916"},"PeriodicalIF":4.5,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11107337","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-04DOI: 10.1109/LED.2025.3595404
Yunho Shin;Been Kwak;Ilho Myeong;Daewoong Kwon
This work proposes a common-drain engineering technique using Through-Silicon Metal (TSM) to improve electro-thermal performance in CFET architectures. After optimizing the Bottom Dielectric Isolation (BDI) thickness to 5 nm, the TSM-integrated CFET exhibits ~10% reduction in gate capacitance (Cgg: $0.580to 0.537$ fF) and ~12.5% lower nFET thermal resistance (Rth: $0.795to ~0.696$ K/$mu $ W) compared to the reference. In the TSM structure, although the common drain-to-metal contact area is reduced, SNMR degradation remains minimal (~2 mV). In addition, device lifetime shows significant improvement, with BTI and HCI projections extended by $sim 2times $ and $sim 1.6times $ , respectively. These results demonstrate that TSM enables effective electro-thermal co-optimization for future CFET logic integration.
本研究提出了一种使用透硅金属（TSM）的共漏工程技术来改善cet结构的电热性能。优化底部介电隔离（BDI）厚度至5 nm后，tsm集成的cfeet表现为10% reduction in gate capacitance (Cgg: $0.580to 0.537$ fF) and ~12.5% lower nFET thermal resistance (Rth: $0.795to ~0.696$ K/ $mu $ W) compared to the reference. In the TSM structure, although the common drain-to-metal contact area is reduced, SNMR degradation remains minimal (~2 mV). In addition, device lifetime shows significant improvement, with BTI and HCI projections extended by $sim 2times $ and $sim 1.6times $ , respectively. These results demonstrate that TSM enables effective electro-thermal co-optimization for future CFET logic integration.
{"title":"The Impact of Through Silicon Metal (TSM) Contact on Performance and Thermal Reliability in CFET","authors":"Yunho Shin;Been Kwak;Ilho Myeong;Daewoong Kwon","doi":"10.1109/LED.2025.3595404","DOIUrl":"https://doi.org/10.1109/LED.2025.3595404","url":null,"abstract":"This work proposes a common-drain engineering technique using Through-Silicon Metal (TSM) to improve electro-thermal performance in CFET architectures. After optimizing the Bottom Dielectric Isolation (BDI) thickness to 5 nm, the TSM-integrated CFET exhibits ~10% reduction in gate capacitance (Cgg: <inline-formula> <tex-math>$0.580to 0.537$ </tex-math></inline-formula> fF) and ~12.5% lower nFET thermal resistance (Rth: <inline-formula> <tex-math>$0.795to ~0.696$ </tex-math></inline-formula> K/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> W) compared to the reference. In the TSM structure, although the common drain-to-metal contact area is reduced, SNMR degradation remains minimal (~2 mV). In addition, device lifetime shows significant improvement, with BTI and HCI projections extended by <inline-formula> <tex-math>$sim 2times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$sim 1.6times $ </tex-math></inline-formula>, respectively. These results demonstrate that TSM enables effective electro-thermal co-optimization for future CFET logic integration.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1897-1900"},"PeriodicalIF":4.5,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-performance flexible HfO2-based ferroelectric devices with low thermal budget are essential for the large-scale integration and application of flexible electronic systems. In this work, the ferroelectricity of Hf0.5Zr0.5O2 (HZO) devices under a low annealing temperature of 400°C was enhanced by stress effect. Compared with Si-based HZO devices, flexible HZO devices exhibit a higher remanent polarization (Pr) value of $28.5~mu $ C/cm2 and superior endurance, with only a 5.6% degradation in Pr after 1010 cycles. Furthermore, the flexible HZO devices were annealed under bending, resulting in an increased Pr value of $31.4~mu $ C/cm2 and a reduced coercive field (2Ec) of 2.6 MV/cm. This work provides effective technical support for achieving high-performance flexible HZO devices.
{"title":"Stress-Enhanced Ferroelectric Properties in Flexible Hf0.5Zr0.5O2 Devices With Low Thermal Budget","authors":"Qimiao Zeng;Wei Wang;Shuo Han;Chuanzhi Liu;Jindong Liu;Yi Sun;Lidan Wang;Hui Xu;Qingjiang Li;Rongrong Cao;Shukai Duan","doi":"10.1109/LED.2025.3595286","DOIUrl":"https://doi.org/10.1109/LED.2025.3595286","url":null,"abstract":"High-performance flexible HfO2-based ferroelectric devices with low thermal budget are essential for the large-scale integration and application of flexible electronic systems. In this work, the ferroelectricity of Hf0.5Zr0.5O2 (HZO) devices under a low annealing temperature of 400°C was enhanced by stress effect. Compared with Si-based HZO devices, flexible HZO devices exhibit a higher remanent polarization (Pr) value of <inline-formula> <tex-math>$28.5~mu $ </tex-math></inline-formula>C/cm2 and superior endurance, with only a 5.6% degradation in Pr after 1010 cycles. Furthermore, the flexible HZO devices were annealed under bending, resulting in an increased Pr value of <inline-formula> <tex-math>$31.4~mu $ </tex-math></inline-formula>C/cm2 and a reduced coercive field (2Ec) of 2.6 MV/cm. This work provides effective technical support for achieving high-performance flexible HZO devices.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1885-1888"},"PeriodicalIF":4.5,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, we report the first p-type channel field-effect transistors (p-FETs) fabricated on single crystal GaN substrate. The p-GaN/u-GaN/AlN/AlGaN structure on GaN substrate exhibits excellent crystal quality and interface. Due to the decrease of threading dislocations (TDs), there is a significant reduction in N-vacancies. Fewer holes are compensated. The p-FET structure on GaN substrate features higher sheet hole density. Moreover, sharp interface reduces the interface roughness scattering, ensuring no degradation of mobility. The p-FETs based on GaN substrate have higher performance benefit from lower sheet resistivity. Specifically, the saturation current of the p-FET is boosted by 7 times compared to the p-FET on sapphire substrate. These results demonstrate the remarkable potential of GaN substrate for the realization of high-performance p-FET.
{"title":"First Experimental Realization of a p-FET Based on Single Crystal GaN Substrate","authors":"Xu Liu;Shengrui Xu;Huake Su;Hongchang Tao;Tao Zhang;Lei Xie;Yuan Gao;Xinhao Wang;Jincheng Zhang;Yue Hao","doi":"10.1109/LED.2025.3595206","DOIUrl":"https://doi.org/10.1109/LED.2025.3595206","url":null,"abstract":"In this study, we report the first p-type channel field-effect transistors (p-FETs) fabricated on single crystal GaN substrate. The p-GaN/u-GaN/AlN/AlGaN structure on GaN substrate exhibits excellent crystal quality and interface. Due to the decrease of threading dislocations (TDs), there is a significant reduction in N-vacancies. Fewer holes are compensated. The p-FET structure on GaN substrate features higher sheet hole density. Moreover, sharp interface reduces the interface roughness scattering, ensuring no degradation of mobility. The p-FETs based on GaN substrate have higher performance benefit from lower sheet resistivity. Specifically, the saturation current of the p-FET is boosted by 7 times compared to the p-FET on sapphire substrate. These results demonstrate the remarkable potential of GaN substrate for the realization of high-performance p-FET.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1701-1704"},"PeriodicalIF":4.5,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/LED.2025.3593224
Xi Wang;Yulei Zhang;Yuxi Wan;Juan Xiong;Lechen Liu;Xuhui Pu;Chao Zhang;Hongbin Pu;Zhiming Chen
A 1.2 kV 4H-SiC optically controlled transistor with reverse conducting performance was designed and fabricated as demo chip for pulsed characterization evaluation. A 355 nm UV laser was used to drive the transistor via optical fiber. The experimental results indicated that the SiC optically controlled transistor obtained a good pulsed characteristic. The full width at half maximum of output current pulse was all in 100 ns and there was no obvious current trailing phenomenon. When the biased voltage was 1000 V and the laser energy was $10mu $ J, the peak current and current rising rate of the device were 4.61 A and 1.0 kA/$mu $ s, which the corresponding peak current density and current density rising rate were 307.3 A/cm2 and 66.7 kA/(cm${}^{{2}}cdot mu $ s), respectively.
{"title":"Pulsed Characterization of 1.2 kV SiC Optically Controlled Transistor With Reverse Conducting Performance","authors":"Xi Wang;Yulei Zhang;Yuxi Wan;Juan Xiong;Lechen Liu;Xuhui Pu;Chao Zhang;Hongbin Pu;Zhiming Chen","doi":"10.1109/LED.2025.3593224","DOIUrl":"https://doi.org/10.1109/LED.2025.3593224","url":null,"abstract":"A 1.2 kV 4H-SiC optically controlled transistor with reverse conducting performance was designed and fabricated as demo chip for pulsed characterization evaluation. A 355 nm UV laser was used to drive the transistor via optical fiber. The experimental results indicated that the SiC optically controlled transistor obtained a good pulsed characteristic. The full width at half maximum of output current pulse was all in 100 ns and there was no obvious current trailing phenomenon. When the biased voltage was 1000 V and the laser energy was <inline-formula> <tex-math>$10mu $ </tex-math></inline-formula>J, the peak current and current rising rate of the device were 4.61 A and 1.0 kA/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>s, which the corresponding peak current density and current density rising rate were 307.3 A/cm2 and 66.7 kA/(cm<inline-formula> <tex-math>${}^{{2}}cdot mu $ </tex-math></inline-formula>s), respectively.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1713-1716"},"PeriodicalIF":4.5,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11098810","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, the gate oxide degradation of SiC MOSFETs induced by dynamic gate stress under total ionizing dose irradiation is investigated to accurately evaluate the impact of the gate oxide reliability on the real device operating conditions. The threshold voltage (${V}_{text {th}}text {)}$ drift of SiC MOSFETs under dynamic gate voltage (${V}_{text {gs}}text {)}$ is only 0.21 V when the irradiation dose reaches 1 Mrad, whereas negative ${V}_{text {th}}$ drifts of 1.80 V and 0.68 V are observed under constant ${V}_{text {gs}}$ of +15 V and -5 V, respectively. This indicates that a conventional constant gate bias test will overestimate the instability of the ${V}_{text {th}}$ during irradiation. Meanwhile, it is also found that the oxide breakdown time at the electrical field of 9.5 MV/cm is decreased from 5280 s (${V}_{text {gs}} = +15$ V), 4400 s (${V}_{text {gs}} =$ -5 V) to 430 s (dynamic gate bias) after the irradiation dose of 1 Mrad. The poor reliability of gate oxide and the relatively weak degradation of electrical properties after irradiation is mainly due to more electrons and holes trapped by oxide traps when a dynamic gate bias is applied. Based on the TDDB defect percolation model, widely distributed oxide charges can form potential conductive paths that accelerate defect percolation and gate oxide breakdown under high electric fields.
{"title":"Investigation on Gate Oxide Degradation of SiC MOSFETs Induced by Dynamic Gate Stress Under Total Ionizing Dose Irradiation","authors":"Jiahao Hu;Xiaochuan Deng;Tao Xu;Haibo Wu;Xing Zeng;Xu Li;Song Bai;Xuan Li;Bo Zhang","doi":"10.1109/LED.2025.3593039","DOIUrl":"https://doi.org/10.1109/LED.2025.3593039","url":null,"abstract":"In this letter, the gate oxide degradation of SiC MOSFETs induced by dynamic gate stress under total ionizing dose irradiation is investigated to accurately evaluate the impact of the gate oxide reliability on the real device operating conditions. The threshold voltage (<inline-formula> <tex-math>${V}_{text {th}}text {)}$ </tex-math></inline-formula> drift of SiC MOSFETs under dynamic gate voltage (<inline-formula> <tex-math>${V}_{text {gs}}text {)}$ </tex-math></inline-formula> is only 0.21 V when the irradiation dose reaches 1 Mrad, whereas negative <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> drifts of 1.80 V and 0.68 V are observed under constant <inline-formula> <tex-math>${V}_{text {gs}}$ </tex-math></inline-formula> of +15 V and -5 V, respectively. This indicates that a conventional constant gate bias test will overestimate the instability of the <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> during irradiation. Meanwhile, it is also found that the oxide breakdown time at the electrical field of 9.5 MV/cm is decreased from 5280 s (<inline-formula> <tex-math>${V}_{text {gs}} = +15$ </tex-math></inline-formula> V), 4400 s (<inline-formula> <tex-math>${V}_{text {gs}} =$ </tex-math></inline-formula> -5 V) to 430 s (dynamic gate bias) after the irradiation dose of 1 Mrad. The poor reliability of gate oxide and the relatively weak degradation of electrical properties after irradiation is mainly due to more electrons and holes trapped by oxide traps when a dynamic gate bias is applied. Based on the TDDB defect percolation model, widely distributed oxide charges can form potential conductive paths that accelerate defect percolation and gate oxide breakdown under high electric fields.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 10","pages":"1733-1736"},"PeriodicalIF":4.5,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-25DOI: 10.1109/LED.2025.3588288
{"title":"Wide Band Gap Semiconductors for Automotive Applications","authors":"","doi":"10.1109/LED.2025.3588288","DOIUrl":"https://doi.org/10.1109/LED.2025.3588288","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 8","pages":"1444-1445"},"PeriodicalIF":4.1,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11096961","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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