A novel CMOS-compatible artificial optoelectronic synapse with combing a photodiode-body-biased MOSFET (PD-MOS) with a floating-gate Transistor (FGT) is proposed. The PD-FGT exhibits a broad spectral response (300–1100 nm) with a peak responsivity of 1.8 × 103 A/W at 600 nm, and a large memory window from -1.4 V to 4.1 V. Its opto-electronic performance makes a great promise of enabling emulation of biological synaptic characteristics (Excitatory Postsynaptic Current and Paired Pulse Facilitation) via optical and electrical pulse modulation. An optoelectronic artificial neural network based on this device can potentially obtain 92% accuracy in handwritten digit recognition. This optoelectronic dual-modulated synaptic device opens new avenues for artificial vision systems and future in-sensor computing and storage, laying a foundation for large-scale visual neuromorphic computing hardware systems.
提出了一种将光电二极管体偏置MOSFET （PD-MOS）与浮栅晶体管（FGT）相结合的新型cmos兼容人工光电突触。PD-FGT具有较宽的光谱响应（300-1100 nm），在600 nm处的峰值响应率为1.8 × 103 a /W，在-1.4 V至4.1 V范围内具有较大的存储窗口。它的光电性能使得通过光脉冲和电脉冲调制来模拟生物突触特性（兴奋性突触后电流和成对脉冲促进）成为可能。基于该装置的光电人工神经网络在手写体数字识别中可达到92%的正确率。这种光电双调制突触器件为人工视觉系统和未来传感器内计算和存储开辟了新的途径，为大规模视觉神经形态计算硬件系统奠定了基础。
{"title":"CMOS-Compatible Artificial Optoelectronic Synapse for Neuromorphic Computing","authors":"Chao Gao;Zequn Zheng;Yihong Qi;Zhou Zhou;Xiaolin Liu;Qiang Chen;Jianchao Li;Xin Jin;Xiaoyang Qi;Binhong Wu;Kai Wang","doi":"10.1109/LED.2025.3643167","DOIUrl":"https://doi.org/10.1109/LED.2025.3643167","url":null,"abstract":"A novel CMOS-compatible artificial optoelectronic synapse with combing a photodiode-body-biased MOSFET (PD-MOS) with a floating-gate Transistor (FGT) is proposed. The PD-FGT exhibits a broad spectral response (300–1100 nm) with a peak responsivity of 1.8 × 10<sup>3</sup> A/W at 600 nm, and a large memory window from -1.4 V to 4.1 V. Its opto-electronic performance makes a great promise of enabling emulation of biological synaptic characteristics (Excitatory Postsynaptic Current and Paired Pulse Facilitation) via optical and electrical pulse modulation. An optoelectronic artificial neural network based on this device can potentially obtain 92% accuracy in handwritten digit recognition. This optoelectronic dual-modulated synaptic device opens new avenues for artificial vision systems and future in-sensor computing and storage, laying a foundation for large-scale visual neuromorphic computing hardware systems.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 2","pages":"415-418"},"PeriodicalIF":4.5,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146081997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-15DOI: 10.1109/LED.2025.3644685
Umer F. Ahmed;Andrew J. Flewitt
Electronic devices using nanomaterials have the potential to outperform equivalent devices using bulk materials, but only if nanoscale contacts can be made to the nanomaterial. This is achieved by a scalable process in this work through hydrothermal growth of horizontal ZnO nanowires (NWs) from a ZnO seed layer across a 40 nm nanogap created by adhesion lithography (A-lith). The asymmetric Ti and Au electrodes of the nanogap lead to the formation of Schottky diodes in the NWs, exhibiting rectification ratios >103. The addition of SiO2 dielectric around the NW improved the rectification ratio to almost 104 and allowed the addition of a bottom gate. The device demonstrated transistor-like behavior, most notably under reverse bias conditions. These characteristics are analogous to a source-gated transistor (SGT), with both accumulation and depletion modes of operation, demonstrating for the first time experimentally, SGTs with a size below 100 nm. This is significant as it opens up the possibility of nanoscale arrays of SGTs for ultra-high resolution displays or neuromorphic processors.
{"title":"ZnO Nanowire Gate-Tunable Schottky Diodes by Adhesion Lithography","authors":"Umer F. Ahmed;Andrew J. Flewitt","doi":"10.1109/LED.2025.3644685","DOIUrl":"https://doi.org/10.1109/LED.2025.3644685","url":null,"abstract":"Electronic devices using nanomaterials have the potential to outperform equivalent devices using bulk materials, but only if nanoscale contacts can be made to the nanomaterial. This is achieved by a scalable process in this work through hydrothermal growth of horizontal ZnO nanowires (NWs) from a ZnO seed layer across a 40 nm nanogap created by adhesion lithography (A-lith). The asymmetric Ti and Au electrodes of the nanogap lead to the formation of Schottky diodes in the NWs, exhibiting rectification ratios >10<sup>3</sup>. The addition of SiO<sub>2</sub> dielectric around the NW improved the rectification ratio to almost 10<sup>4</sup> and allowed the addition of a bottom gate. The device demonstrated transistor-like behavior, most notably under reverse bias conditions. These characteristics are analogous to a source-gated transistor (SGT), with both accumulation and depletion modes of operation, demonstrating for the first time experimentally, SGTs with a size below 100 nm. This is significant as it opens up the possibility of nanoscale arrays of SGTs for ultra-high resolution displays or neuromorphic processors.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 2","pages":"407-410"},"PeriodicalIF":4.5,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-05DOI: 10.1109/LED.2025.3640707
Shubham Kumar;Saikat Chakraborty;Yixin Qin;Moonyoung Jung;Kwangyou Seo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Vijaykrishnan Narayanan;Jaydeep P. Kulkarni;Kai Ni
Ferroelectric 3D vertical NAND offers attractive benefits such as lower stack height and reduced write voltage, but enabling erase-verify remains a significant challenge because the erase operation places all FeFETs into a high-threshold-voltage (HVT) state, suppressing electron conduction through the string. This makes conventional electron-based erase-verify schemes ineffective. In this work, we propose a GIDL-assisted hole-based erase-verify method that generates holes through band-to-band tunneling in the source-side transistor and uses their propagation to distinguish fully erased (all-HVT) strings from those containing fail-to-erase low-Vth (LVT) cells. TCAD simulations show that GIDL-generated holes can propagate across an all-HVT string, raising the bitline potential, while an LVT FeFET blocks hole transport, enabling robust verify sensing. We further analyze device-level reliability considerations and evaluate the impact of channel thickness on sense margin. The proposed GIDL-assisted approach provides a compact and architecture-compatible solution for erase-verify in FE-NAND without modifying channel type, adding p+ regions, or requiring incremental erase schemes.
{"title":"Erase-Verify Operation in Ferroelectric 3D Vertical NAND Storage","authors":"Shubham Kumar;Saikat Chakraborty;Yixin Qin;Moonyoung Jung;Kwangyou Seo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Vijaykrishnan Narayanan;Jaydeep P. Kulkarni;Kai Ni","doi":"10.1109/LED.2025.3640707","DOIUrl":"https://doi.org/10.1109/LED.2025.3640707","url":null,"abstract":"Ferroelectric 3D vertical NAND offers attractive benefits such as lower stack height and reduced write voltage, but enabling erase-verify remains a significant challenge because the erase operation places all FeFETs into a high-threshold-voltage (HVT) state, suppressing electron conduction through the string. This makes conventional electron-based erase-verify schemes ineffective. In this work, we propose a GIDL-assisted hole-based erase-verify method that generates holes through band-to-band tunneling in the source-side transistor and uses their propagation to distinguish fully erased (all-HVT) strings from those containing fail-to-erase low-Vth (LVT) cells. TCAD simulations show that GIDL-generated holes can propagate across an all-HVT string, raising the bitline potential, while an LVT FeFET blocks hole transport, enabling robust verify sensing. We further analyze device-level reliability considerations and evaluate the impact of channel thickness on sense margin. The proposed GIDL-assisted approach provides a compact and architecture-compatible solution for erase-verify in FE-NAND without modifying channel type, adding p+ regions, or requiring incremental erase schemes.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 2","pages":"395-398"},"PeriodicalIF":4.5,"publicationDate":"2025-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-04DOI: 10.1109/LED.2025.3629307
{"title":"IEEE Transactions on Electron Devices Table of Contents","authors":"","doi":"10.1109/LED.2025.3629307","DOIUrl":"https://doi.org/10.1109/LED.2025.3629307","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 12","pages":"2384-C3"},"PeriodicalIF":4.5,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11278121","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145665850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-04DOI: 10.1109/LED.2025.3629305
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/LED.2025.3629305","DOIUrl":"https://doi.org/10.1109/LED.2025.3629305","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 12","pages":"2382-2383"},"PeriodicalIF":4.5,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11278207","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145665736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-04DOI: 10.1109/LED.2025.3629283
{"title":"IEEE Electron Device Letters Information for Authors","authors":"","doi":"10.1109/LED.2025.3629283","DOIUrl":"https://doi.org/10.1109/LED.2025.3629283","url":null,"abstract":"","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 12","pages":"2381-2381"},"PeriodicalIF":4.5,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11278122","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145665779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the above article [1], we have found several minor formatting errors. Specifically, there are formatting errors in the display of three parameters in Table I. In addition, there is a black dot appearing at the top of Fig. 2(b), and two black dots at the top of Fig. 3(a). These issues are purely typographical and do not affect the experimental results, analyses, or conclusions presented in the article.TABLE I Parameters ValuesGyromagnetic ratio, $gamma $ $2.2117 times 10^{5} mathrm {~m} /(mathrm {A} cdot mathrm {s})$ PMA coefficient, $mathrm {K}_{mathrm {i}}$ $3.2 times 10^{-4} mathrm {~J} / mathrm {m}^{2}$ Exchange bias, $mathrm {H}_{mathrm {EX}}$ 20 OeSpin polarization, P 0.58TMR ratio, TMR 100VCMA coefficient, $beta $ $160 mathrm {fJ} / mathrm {V} cdot mathrm {m}^{[{21}]}$ Gilbert damping constant, $alpha $ 0.05Spin hall angle, $theta _{text {SH}~}$ 0.25Fig. 2. Fig. 3.
{"title":"Corrections to “A Novel P-bit Unit Based on VGSOT-MTJ for Reconfigurable Ising Machine With Fully Parallel Spin Updating Design”","authors":"Wentao Huang;Kaili Zhang;Junlin Wang;Yu Liu;Bolin Zhang;Youguang Zhang;Weisheng Zhao;Lang Zeng;Deming Zhang","doi":"10.1109/LED.2025.3626118","DOIUrl":"https://doi.org/10.1109/LED.2025.3626118","url":null,"abstract":"In the above article [1], we have found several minor formatting errors. Specifically, there are formatting errors in the display of three parameters in Table I. In addition, there is a black dot appearing at the top of Fig. 2(b), and two black dots at the top of Fig. 3(a). These issues are purely typographical and do not affect the experimental results, analyses, or conclusions presented in the article.TABLE I Parameters ValuesGyromagnetic ratio, $gamma $ $2.2117 times 10^{5} mathrm {~m} /(mathrm {A} cdot mathrm {s})$ PMA coefficient, $mathrm {K}_{mathrm {i}}$ $3.2 times 10^{-4} mathrm {~J} / mathrm {m}^{2}$ Exchange bias, $mathrm {H}_{mathrm {EX}}$ 20 OeSpin polarization, P 0.58TMR ratio, TMR 100VCMA coefficient, $beta $ $160 mathrm {fJ} / mathrm {V} cdot mathrm {m}^{[{21}]}$ Gilbert damping constant, $alpha $ 0.05Spin hall angle, $theta _{text {SH}~}$ 0.25Fig. 2. Fig. 3.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 12","pages":"2377-2378"},"PeriodicalIF":4.5,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11278124","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145665803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we propose a first-order anti-symmetric (A1) mode acoustic resonator and filter based on a 128째 YX-cut LiNbO3 (LN) solidly mounted resonator (SMR) structure. By adopting a non-periodic Bragg reflection layer structure, shear waves and longitudinal waves are effectively reflected at the designed frequency, reducing acoustic leakage loss and achieving a spurious-free resonator within the passband. Simulation results show that the frequency of the spurious-free A1 mode SMR can be adjusted in a wide-frequency range by optimizing the half period and metal ratio simultaneously, which is distinct from the conventional XBAR method that relies on LN film thinning. Then a 6th-order T-type A1 mode SMR filter was designed and fabricated, which exhibits a center frequency of 6.82 GHz, a minimum insertion loss of 2.2 dB, a 3dB bandwidth of 740 MHz, and out-of-band suppression exceeding 25 dB. This work demonstrates a SMR filter design method suitable for the A1 mode, and provides a feasible path and design ideas for engineering implementation of high-frequency acoustic filters.
{"title":"A1 Mode Lithium Niobate Solidly Mounted Filter for 5G NR and Wi-Fi 6E/7 Applications","authors":"Peiran Li;Bin Peng;Yuedong Wang;Wei Fan;Sijia Huo;Zijie Wei;Dahao Wu;Wenbo Luo;Yao Shuai;Xinqiang Pan;Chuangui Wu","doi":"10.1109/LED.2025.3640102","DOIUrl":"https://doi.org/10.1109/LED.2025.3640102","url":null,"abstract":"In this work, we propose a first-order anti-symmetric (A1) mode acoustic resonator and filter based on a 128째 YX-cut LiNbO<sub>3</sub> (LN) solidly mounted resonator (SMR) structure. By adopting a non-periodic Bragg reflection layer structure, shear waves and longitudinal waves are effectively reflected at the designed frequency, reducing acoustic leakage loss and achieving a spurious-free resonator within the passband. Simulation results show that the frequency of the spurious-free A1 mode SMR can be adjusted in a wide-frequency range by optimizing the half period and metal ratio simultaneously, which is distinct from the conventional XBAR method that relies on LN film thinning. Then a 6th-order T-type A1 mode SMR filter was designed and fabricated, which exhibits a center frequency of 6.82 GHz, a minimum insertion loss of 2.2 dB, a 3dB bandwidth of 740 MHz, and out-of-band suppression exceeding 25 dB. This work demonstrates a SMR filter design method suitable for the A1 mode, and provides a feasible path and design ideas for engineering implementation of high-frequency acoustic filters.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 2","pages":"419-422"},"PeriodicalIF":4.5,"publicationDate":"2025-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1109/LED.2025.3639367
Abu Shahir Md Khalid Hasan;Md Maksudul Hossain;Md Majharul Islam;Aireen Amir Jalal;Mohammad Dehan Rahman;Colin Shaw;Xiaoqing Song;H. Alan Mantooth
Gallium oxide (Ga2O3) holds significant potential to expand the boundaries of the wide bandgap (silicon carbide, gallium nitride and others) devices. The field plated structure of $beta $ -Ga2O3 lateral depletion mode MOSFETs has shown enhanced breakdown characteristics. In this work, a compact model describing channel current, resistances and non-linear capacitances has been developed for the $beta $ -Ga2O3 lateral MOSFETs. The model equations account for mobility, dielectric constant, voltage-dependent depletion region, and other physical factors. The DC characteristics are calibrated using experimental transfer and output data, while C-V characteristics are estimated through TCAD simulation of a 750V field-plated $beta $ -Ga2O3 MOSFET. The model aligns well with both DC and C-V characteristics, covering reverse transfer, output, and input capacitances. Temperature scaling is integrated to capture device behavior over a range of temperatures, and the model’s transfer characteristics show good agreement with experimental data up to 200°C.
{"title":"Compact Modeling of β-Ga2O3 Lateral Depletion Mode MOSFET","authors":"Abu Shahir Md Khalid Hasan;Md Maksudul Hossain;Md Majharul Islam;Aireen Amir Jalal;Mohammad Dehan Rahman;Colin Shaw;Xiaoqing Song;H. Alan Mantooth","doi":"10.1109/LED.2025.3639367","DOIUrl":"https://doi.org/10.1109/LED.2025.3639367","url":null,"abstract":"Gallium oxide (Ga<sub>2</sub>O<sub>3</sub>) holds significant potential to expand the boundaries of the wide bandgap (silicon carbide, gallium nitride and others) devices. The field plated structure of <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga<sub>2</sub>O<sub>3</sub> lateral depletion mode MOSFETs has shown enhanced breakdown characteristics. In this work, a compact model describing channel current, resistances and non-linear capacitances has been developed for the <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga<sub>2</sub>O<sub>3</sub> lateral MOSFETs. The model equations account for mobility, dielectric constant, voltage-dependent depletion region, and other physical factors. The DC characteristics are calibrated using experimental transfer and output data, while C-V characteristics are estimated through TCAD simulation of a 750V field-plated <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga<sub>2</sub>O<sub>3</sub> MOSFET. The model aligns well with both DC and C-V characteristics, covering reverse transfer, output, and input capacitances. Temperature scaling is integrated to capture device behavior over a range of temperatures, and the model’s transfer characteristics show good agreement with experimental data up to 200°C.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"47 2","pages":"399-402"},"PeriodicalIF":4.5,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146081992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：