Pub Date : 2024-09-02DOI: 10.1109/JEDS.2024.3453408
Hanqi Gao;Jing Jin;Jianjun Zhou
An extraction method to obtain the noise model parameter $T_{mathrm { d}}$ in deep submicron MOSFETs directly from radio frequency (RF) scattering parameters and noise figure measurements is presented. A simplified noise equivalent circuit, along with closed-form solutions to calculate the RF noise figure of MOSFET is developed. On-wafer experimental verification is presented and a comparison with tuner based method is given. Good agreement is obtained between simulated and measured results for $16times 1times 2{{mu }rm m}$ (number of gate fingers $times $ unit gatewidth $times $ cells) gatelength MOSFETs.
{"title":"An Approach to Determine Noise Model Parameter for Submicron MOSFET from RF Noise Figure Measurement","authors":"Hanqi Gao;Jing Jin;Jianjun Zhou","doi":"10.1109/JEDS.2024.3453408","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3453408","url":null,"abstract":"An extraction method to obtain the noise model parameter \u0000<inline-formula> <tex-math>$T_{mathrm { d}}$ </tex-math></inline-formula>\u0000 in deep submicron MOSFETs directly from radio frequency (RF) scattering parameters and noise figure measurements is presented. A simplified noise equivalent circuit, along with closed-form solutions to calculate the RF noise figure of MOSFET is developed. On-wafer experimental verification is presented and a comparison with tuner based method is given. Good agreement is obtained between simulated and measured results for \u0000<inline-formula> <tex-math>$16times 1times 2{{mu }rm m}$ </tex-math></inline-formula>\u0000 (number of gate fingers \u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 unit gatewidth \u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 cells) gatelength MOSFETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"692-697"},"PeriodicalIF":2.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663413","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142165101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-02DOI: 10.1109/JEDS.2024.3453122
Nan Wu;Zhi Jin;Jingtao Zhou;Haomiao Wei;Zhicheng Liu;Jianming Lin
The research on high power 190 GHz doubler based on the GaAs Schottky diodes is proposed in this paper. The frequency doubler comprises a improved diode configuration that increases the number of anodes by changing the diode arrangement to improve power handling capacity. Electromagnetic and thermal simulation is utilized to demonstrate that the doubler can carry more power. The input power is gradually pumping from 200 mW to 500 mW with an applied DC bias of −15 V. And the peak efficiency of the doubler is measured to be 17%, while the maximum output power is 85 mW at 190 GHz.
{"title":"High Power 190 GHz Frequency Doubler Based On GaAs Schottky Diode","authors":"Nan Wu;Zhi Jin;Jingtao Zhou;Haomiao Wei;Zhicheng Liu;Jianming Lin","doi":"10.1109/JEDS.2024.3453122","DOIUrl":"10.1109/JEDS.2024.3453122","url":null,"abstract":"The research on high power 190 GHz doubler based on the GaAs Schottky diodes is proposed in this paper. The frequency doubler comprises a improved diode configuration that increases the number of anodes by changing the diode arrangement to improve power handling capacity. Electromagnetic and thermal simulation is utilized to demonstrate that the doubler can carry more power. The input power is gradually pumping from 200 mW to 500 mW with an applied DC bias of −15 V. And the peak efficiency of the doubler is measured to be 17%, while the maximum output power is 85 mW at 190 GHz.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"717-722"},"PeriodicalIF":2.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663496","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-26DOI: 10.1109/JEDS.2024.3449798
Yatexu Patel;Pouya Valizadeh
In this manuscript, we have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the on-state breakdown voltage (BVon) of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. The results show that the downscaling of LGS and LG augments the electron velocity in the source-access region. Due to current conservation, the higher carrier velocity in the source-access region for the devices having shorter LGS and LG induces a higher electron density under the gated-channel. From what is theoretically observed, the presence of higher electron density close to the boundary with the velocity saturation region at the drain edge of the gate in devices having shorter LGS and LG does seem to initiate the device breakdown at lower drain voltages, leading to the deterioration of the on-state breakdown voltage.
在本手稿中，我们研究了栅-源长度（LGS）和栅长度（LG）的缩放对金属面 InAlN/AlN/GaN 异质结构场效应晶体管（HFET）导通击穿电压（BVon）的影响。结果表明，LGS 和 LG 的缩减提高了源极-汲极区域的电子速度。由于电流守恒，LGS 和 LG 较短的器件在源极接入区的载流子速度较高，从而导致栅极沟道下的电子密度较高。从理论上观察，在 LGS 和 LG 较短的器件中，靠近栅极漏极边缘速度饱和区边界的较高电子密度似乎会在较低的漏极电压下引发器件击穿，从而导致导通击穿电压恶化。
{"title":"Impact of the Scaling of LGS and LG on the On-State Breakdown Voltage of InAlN/GaN HFETs With Localized Fin Under the Gate Electrode","authors":"Yatexu Patel;Pouya Valizadeh","doi":"10.1109/JEDS.2024.3449798","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3449798","url":null,"abstract":"In this manuscript, we have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the on-state breakdown voltage (BVon) of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. The results show that the downscaling of LGS and LG augments the electron velocity in the source-access region. Due to current conservation, the higher carrier velocity in the source-access region for the devices having shorter LGS and LG induces a higher electron density under the gated-channel. From what is theoretically observed, the presence of higher electron density close to the boundary with the velocity saturation region at the drain edge of the gate in devices having shorter LGS and LG does seem to initiate the device breakdown at lower drain voltages, leading to the deterioration of the on-state breakdown voltage.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"645-650"},"PeriodicalIF":2.0,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10646346","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142137517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/JEDS.2024.3447149
Gerardo Malavena;Salvatore M. Amoroso;Andrew R. Brown;Plamen Asenov;Xi-Wei Lin;Victor Moroz;Mattia Giulianini;David Refaldi;Christian Monzio Compagnoni;Alessandro S. Spinelli
In this two-part article we discuss the difference between a continuous and a discrete approach to trap modeling in the simulation of 3-D NAND Flash memories with polysilicon channel. In Part I we focus on threshold voltage $({mathrm { V}}_{mathrm { T}})$ fluctuations induced by traps and show that lower values for the average and rms ${mathrm { V}}_{mathrm { T}}$ arise when the discrete nature of traps is accounted for. We explain such differences in terms of a stronger percolation that leads to a lower number of filled traps in the discrete-trap case, and investigate such differences as a function of cell parameters and temperature. Finally, we compare the two approaches showing that a continuous trap model cannot reproduce the correct dependences resulting from a discrete treatment.
{"title":"Discrete-Trap Effects on 3-D NAND Variability – Part I: Threshold Voltage","authors":"Gerardo Malavena;Salvatore M. Amoroso;Andrew R. Brown;Plamen Asenov;Xi-Wei Lin;Victor Moroz;Mattia Giulianini;David Refaldi;Christian Monzio Compagnoni;Alessandro S. Spinelli","doi":"10.1109/JEDS.2024.3447149","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3447149","url":null,"abstract":"In this two-part article we discuss the difference between a continuous and a discrete approach to trap modeling in the simulation of 3-D NAND Flash memories with polysilicon channel. In Part I we focus on threshold voltage \u0000<inline-formula> <tex-math>$({mathrm { V}}_{mathrm { T}})$ </tex-math></inline-formula>\u0000 fluctuations induced by traps and show that lower values for the average and rms \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { T}}$ </tex-math></inline-formula>\u0000 arise when the discrete nature of traps is accounted for. We explain such differences in terms of a stronger percolation that leads to a lower number of filled traps in the discrete-trap case, and investigate such differences as a function of cell parameters and temperature. Finally, we compare the two approaches showing that a continuous trap model cannot reproduce the correct dependences resulting from a discrete treatment.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"651-657"},"PeriodicalIF":2.0,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10643153","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142137553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/JEDS.2024.3447022
Qiang Chen;Y. Q. Chen;Chang Liu;Zhiyuan He;Yuan Chen;K. W. Geng;Y. J. He;W. Y. Chen
In this paper, we investigate the electrical characteristics of AlGaN/GaN HEMTs at the lowest temperature of 20 K. The measurement results indicate that the output current of the device decreases significantly with increasing temperature at temperature ranging from 40 K to 260 K, and the saturation drain current decreases by 19%. The gate leakage current rises slightly when the temperature increases. However, both the transfer and C-V characteristics indicate that the threshold voltage shift slightly in a negative direction as the temperature rises. In order to determine the physical mechanism of electrical characteristics change, the low-frequency noise (LFN) characteristics at different temperatures were measured and the density of traps was extracted. Finally, we consider that there are two competing mechanisms affecting the electrical characteristics of devices. The trap density reduction caused by temperature rise leads to threshold voltage’s negative shift, while the drop of 2DEG mobility is the main reason for the decrease of output current.
测量结果表明，在 40 K 至 260 K 的温度范围内，器件的输出电流随着温度的升高而显著减小，饱和漏极电流减小了 19%。温度升高时，栅极漏电流略有上升。然而，转移特性和 C-V 特性都表明，随着温度升高，阈值电压略微向负方向移动。为了确定电气特性变化的物理机制，我们测量了不同温度下的低频噪声（LFN）特性，并提取了陷阱密度。最后，我们认为有两种相互竞争的机制影响着器件的电气特性。温度升高引起的陷阱密度降低导致阈值电压负移，而二维电子元件迁移率下降则是输出电流降低的主要原因。
{"title":"Temperature-Dependent Electrical Characteristics and Low-Frequency Noise Analysis of AlGaN/GaN HEMTs","authors":"Qiang Chen;Y. Q. Chen;Chang Liu;Zhiyuan He;Yuan Chen;K. W. Geng;Y. J. He;W. Y. Chen","doi":"10.1109/JEDS.2024.3447022","DOIUrl":"10.1109/JEDS.2024.3447022","url":null,"abstract":"In this paper, we investigate the electrical characteristics of AlGaN/GaN HEMTs at the lowest temperature of 20 K. The measurement results indicate that the output current of the device decreases significantly with increasing temperature at temperature ranging from 40 K to 260 K, and the saturation drain current decreases by 19%. The gate leakage current rises slightly when the temperature increases. However, both the transfer and C-V characteristics indicate that the threshold voltage shift slightly in a negative direction as the temperature rises. In order to determine the physical mechanism of electrical characteristics change, the low-frequency noise (LFN) characteristics at different temperatures were measured and the density of traps was extracted. Finally, we consider that there are two competing mechanisms affecting the electrical characteristics of devices. The trap density reduction caused by temperature rise leads to threshold voltage’s negative shift, while the drop of 2DEG mobility is the main reason for the decrease of output current.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"698-702"},"PeriodicalIF":2.0,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10643171","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/JEDS.2024.3447150
Gerardo Malavena;Salvatore M. Amoroso;Andrew R. Brown;Plamen Asenov;Xi-Wei Lin;Victor Moroz;Mattia Giulianini;David Refaldi;Christian Monzio Compagnoni;Alessandro S. Spinelli
In Part II of this article we discuss the impact of a discrete treatment of traps on 3-D NAND Flash random telegraph noise (RTN). A higher RTN results when discrete traps are taken into account, that can only be explained by a stronger influence of the discrete charged traps on the current conduction, leading to more percolation. The effects are then investigated as a function of the cell parameters, showing that a continuous model for traps cannot reproduce the correct dependence.
{"title":"Discrete-Trap Effects on 3-D NAND Variability – Part II: Random Telegraph Noise","authors":"Gerardo Malavena;Salvatore M. Amoroso;Andrew R. Brown;Plamen Asenov;Xi-Wei Lin;Victor Moroz;Mattia Giulianini;David Refaldi;Christian Monzio Compagnoni;Alessandro S. Spinelli","doi":"10.1109/JEDS.2024.3447150","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3447150","url":null,"abstract":"In Part II of this article we discuss the impact of a discrete treatment of traps on 3-D NAND Flash random telegraph noise (RTN). A higher RTN results when discrete traps are taken into account, that can only be explained by a stronger influence of the discrete charged traps on the current conduction, leading to more percolation. The effects are then investigated as a function of the cell parameters, showing that a continuous model for traps cannot reproduce the correct dependence.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"658-661"},"PeriodicalIF":2.0,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10643403","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142137518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/JEDS.2024.3447032
Xiaoying Tang;Zhiqiang Li;Lang Zeng;Hongwei Zhou;Xiaoxu Cheng;Zhenjie Yao
Engineers used TCAD tools for semiconductor devices modeling. However, it is computationally expensive and time-consuming for advanced devices with smaller dimensions. Therefore, this work proposes a machine learning-based device modeling algorithm to capture the complex nonlinear relationship between parameters and electrical characteristics of gate-all-around (GAA) nanowire field-effect transistors (NWFETs) from technology computer-aided design (TCAD) simulation results. This method utilizes a densely connected deep neural networks (DenseDNN), which establishes direct connections between layers in the neural networks, provides stronger feature extraction and information transmission capabilities. By incorporating cost-sensitive learning methods, the proposed model focus more on the critical data that determines device characteristics, leading to accurate prediction of key device characteristics under various parameters. Experimental results on a test dataset of 116 NWFETs demonstrate the effectiveness of this method. The DenseDNN model with cost-sensitive learning exhibits better performance than traditional deep neural networks (DNN) with various widths and depths, with a prediction error below 1.62%. Moreover, compared to TCAD simulation results, the model can speedup $10^{6}times$ .
{"title":"Device Modeling Based on Cost-Sensitive Densely Connected Deep Neural Networks","authors":"Xiaoying Tang;Zhiqiang Li;Lang Zeng;Hongwei Zhou;Xiaoxu Cheng;Zhenjie Yao","doi":"10.1109/JEDS.2024.3447032","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3447032","url":null,"abstract":"Engineers used TCAD tools for semiconductor devices modeling. However, it is computationally expensive and time-consuming for advanced devices with smaller dimensions. Therefore, this work proposes a machine learning-based device modeling algorithm to capture the complex nonlinear relationship between parameters and electrical characteristics of gate-all-around (GAA) nanowire field-effect transistors (NWFETs) from technology computer-aided design (TCAD) simulation results. This method utilizes a densely connected deep neural networks (DenseDNN), which establishes direct connections between layers in the neural networks, provides stronger feature extraction and information transmission capabilities. By incorporating cost-sensitive learning methods, the proposed model focus more on the critical data that determines device characteristics, leading to accurate prediction of key device characteristics under various parameters. Experimental results on a test dataset of 116 NWFETs demonstrate the effectiveness of this method. The DenseDNN model with cost-sensitive learning exhibits better performance than traditional deep neural networks (DNN) with various widths and depths, with a prediction error below 1.62%. Moreover, compared to TCAD simulation results, the model can speedup \u0000<inline-formula> <tex-math>$10^{6}times$ </tex-math></inline-formula>\u0000.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"619-626"},"PeriodicalIF":2.0,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10643157","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-16DOI: 10.1109/JEDS.2024.3438210
Sunaina Priyadarshi;Abidur Rahaman;Mohammad Masum Billah;Sabiqun Nahar;Md. Redowan Mahmud Arnob;Jin Jang
This article intends to use a low-temperature poly-Si oxide (LTPO) level-down-shifter (LDS) to translate voltage signals with different amplitudes operating at various frequencies. The LTPO LDS is made of p-type low-temperature poly-Si and n-type a-InGaZnO thin-film transistors. The input voltage range of 2 V~10 V could be shifted to 1.2 V ~ 4.41 V output voltage. The rising and falling times are less than 400 ns at the operational frequency of 50 kHz. Also, the multiple output power supply of 6 V, 3 V, and 1.8 V for interface circuits has been possible with a single supply of 10 V. The proposed LDS shows a switching power consumption of 95.57 pW and area of 0.023 mm2.
本文旨在使用低温多晶硅氧化物（LTPO）电平降低转换器（LDS）来转换在不同频率下工作的不同幅度的电压信号。LTPO LDS 由 p 型低温多晶硅和 n 型 a-InGaZnO 薄膜晶体管组成。输入电压范围为 2 V~10 V，可转换为 1.2 V~4.41 V 的输出电压。在 50 kHz 的工作频率下，上升和下降时间小于 400 ns。此外，只需 10 V 单电源，即可为接口电路提供 6 V、3 V 和 1.8 V 的多路输出电源。
{"title":"High Speed Level-Down Shifter Using LTPO TFTs for Low Power and Interface Electronics","authors":"Sunaina Priyadarshi;Abidur Rahaman;Mohammad Masum Billah;Sabiqun Nahar;Md. Redowan Mahmud Arnob;Jin Jang","doi":"10.1109/JEDS.2024.3438210","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3438210","url":null,"abstract":"This article intends to use a low-temperature poly-Si oxide (LTPO) level-down-shifter (LDS) to translate voltage signals with different amplitudes operating at various frequencies. The LTPO LDS is made of p-type low-temperature poly-Si and n-type a-InGaZnO thin-film transistors. The input voltage range of 2 V~10 V could be shifted to 1.2 V ~ 4.41 V output voltage. The rising and falling times are less than 400 ns at the operational frequency of 50 kHz. Also, the multiple output power supply of 6 V, 3 V, and 1.8 V for interface circuits has been possible with a single supply of 10 V. The proposed LDS shows a switching power consumption of 95.57 pW and area of 0.023 mm2.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"587-593"},"PeriodicalIF":2.0,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10637919","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142013206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The motivation of this study was to solve the high $rm I_{D,off}$ problem in 8 Volt N-channel MOSFET. We experimented with implanting nitrogen into LDD at various doses. As a result, $rm I_{D,off}$ increases and $rm BV_{DSS}$ decreases as the dose increases. When it exceeds 1.0E15 cm $^{-2}$ , the occurrence of tail-type $rm I_{D,off}$ and $rm BV_{DSS}$ that deviate from the normal distribution increases. Implanted nitrogen enhances the diffusion of dopants in the LDD bulk but suppresses it on the silicon surface. As a result, the depletion curvature at the LDD edge becomes a negative shape and increases the electric field. We performed the same experiment on logic MOSFETs to comprehensively analyze other electrical effects. Nitrogen improves the HCI immunity of MOSFETs but degrades for 2.5 Volt and 8 Volt MOSFETs when the dose is above 1.0E15 cm $^{-2}$ . The short-channel effect of 2.5 Volt MOSFET is insensitive to nitrogen but is suppressed in CORE MOSFET when the dose is over 1.3E15 cm $^{-2}$ . Nitrogen changes $rm I_{D,sat}$ through interactions with co-implanted species and nitrogen dose. As a result, nitrogen co-implanted with phosphorus shows a parabolic-like $rm I_{D,sat}$ trend. However, in the case of CORE MOSFET implanted with arsenic, $rm I_{D,sat}$ does not show a parabolic-like trend but increases continuously. This experiment did not find much benefit from nitrogen implantation for 2.5 Volt and 8 Volt MOSFETs. For all MOSFETs, it is recommended that the nitrogen dosage not exceed 1.0E15 cm $^{-2}$ .
{"title":"Electrical Effect of Nitrogen Implanted Into LDD of MOSFETs","authors":"Yoo Seon Song;Markus Lenski;Mohammed F. Karim;Keith Flynn;Jan Hoentschel;Carsten Peters;Jens-Uwe Sachse;Ömür Işıl Aydin;Jun Wu;Bastian Haußdörfer;Mahesh Siddabathula;Konrad Semmler;Jürgen Daleiden","doi":"10.1109/JEDS.2024.3442474","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3442474","url":null,"abstract":"The motivation of this study was to solve the high \u0000<inline-formula> <tex-math>$rm I_{D,off}$ </tex-math></inline-formula>\u0000 problem in 8 Volt N-channel MOSFET. We experimented with implanting nitrogen into LDD at various doses. As a result, \u0000<inline-formula> <tex-math>$rm I_{D,off}$ </tex-math></inline-formula>\u0000 increases and \u0000<inline-formula> <tex-math>$rm BV_{DSS}$ </tex-math></inline-formula>\u0000 decreases as the dose increases. When it exceeds 1.0E15 cm\u0000<inline-formula> <tex-math>$^{-2}$ </tex-math></inline-formula>\u0000, the occurrence of tail-type \u0000<inline-formula> <tex-math>$rm I_{D,off}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$rm BV_{DSS}$ </tex-math></inline-formula>\u0000 that deviate from the normal distribution increases. Implanted nitrogen enhances the diffusion of dopants in the LDD bulk but suppresses it on the silicon surface. As a result, the depletion curvature at the LDD edge becomes a negative shape and increases the electric field. We performed the same experiment on logic MOSFETs to comprehensively analyze other electrical effects. Nitrogen improves the HCI immunity of MOSFETs but degrades for 2.5 Volt and 8 Volt MOSFETs when the dose is above 1.0E15 cm\u0000<inline-formula> <tex-math>$^{-2}$ </tex-math></inline-formula>\u0000. The short-channel effect of 2.5 Volt MOSFET is insensitive to nitrogen but is suppressed in CORE MOSFET when the dose is over 1.3E15 cm\u0000<inline-formula> <tex-math>$^{-2}$ </tex-math></inline-formula>\u0000. Nitrogen changes \u0000<inline-formula> <tex-math>$rm I_{D,sat}$ </tex-math></inline-formula>\u0000 through interactions with co-implanted species and nitrogen dose. As a result, nitrogen co-implanted with phosphorus shows a parabolic-like \u0000<inline-formula> <tex-math>$rm I_{D,sat}$ </tex-math></inline-formula>\u0000 trend. However, in the case of CORE MOSFET implanted with arsenic, \u0000<inline-formula> <tex-math>$rm I_{D,sat}$ </tex-math></inline-formula>\u0000 does not show a parabolic-like trend but increases continuously. This experiment did not find much benefit from nitrogen implantation for 2.5 Volt and 8 Volt MOSFETs. For all MOSFETs, it is recommended that the nitrogen dosage not exceed 1.0E15 cm\u0000<inline-formula> <tex-math>$^{-2}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"627-636"},"PeriodicalIF":2.0,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10634165","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-08DOI: 10.1109/JEDS.2024.3441389
Ziang Guo;Sergei Mistyuk;Arthur Carpenter;Charles E. Hunt
Design, fabrication, and measurement of vertical Germanium (Ge) Photodiodes for highspeed, hard X-Ray imaging is presented. The devices used atmospheric-pressure epitaxial absorption layers, varying absorption layer thicknesses (10 – 245 $mu$ m) over bulk-Ge substrates, fabricated in various sizes. Measurements include large-signal and transient-response from X-ray source between 6 keV and 28 keV. The results approach a 100% external quantum efficiency with 245 $mu$ m absorption regions and a 22% improvement in temporal response with 10 $mu$ m absorption region compared to an Si reference device of the same active area.
{"title":"High-Performance Germanium P-I-N Photodiodes for High-Speed, Hard X-Ray Imaging","authors":"Ziang Guo;Sergei Mistyuk;Arthur Carpenter;Charles E. Hunt","doi":"10.1109/JEDS.2024.3441389","DOIUrl":"10.1109/JEDS.2024.3441389","url":null,"abstract":"Design, fabrication, and measurement of vertical Germanium (Ge) Photodiodes for highspeed, hard X-Ray imaging is presented. The devices used atmospheric-pressure epitaxial absorption layers, varying absorption layer thicknesses (10 – 245 \u0000<inline-formula> <tex-math>$mu$ </tex-math></inline-formula>\u0000m) over bulk-Ge substrates, fabricated in various sizes. Measurements include large-signal and transient-response from X-ray source between 6 keV and 28 keV. The results approach a 100% external quantum efficiency with 245 \u0000<inline-formula> <tex-math>$mu$ </tex-math></inline-formula>\u0000m absorption regions and a 22% improvement in temporal response with 10 \u0000<inline-formula> <tex-math>$mu$ </tex-math></inline-formula>\u0000m absorption region compared to an Si reference device of the same active area.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"1051-1056"},"PeriodicalIF":2.0,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10632103","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141969057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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