Pub Date : 2025-06-10DOI: 10.1109/JEDS.2025.3572172
Ghader Darbandy;Malte Koch;Lukas M. Bongartz;Karl Leo;Hans Kleemann;Alexander Kloes
Presents corrections to the paper, (Erratum to “Charge-Based Compact Modeling of OECTs for Neuromorphic Applications”).
提出了对论文的更正，（对“神经形态应用中基于电荷的OECTs紧凑建模”的勘误）。
{"title":"Erratum to “Charge-Based Compact Modeling of OECTs for Neuromorphic Applications”","authors":"Ghader Darbandy;Malte Koch;Lukas M. Bongartz;Karl Leo;Hans Kleemann;Alexander Kloes","doi":"10.1109/JEDS.2025.3572172","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3572172","url":null,"abstract":"Presents corrections to the paper, (Erratum to “Charge-Based Compact Modeling of OECTs for Neuromorphic Applications”).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"471-471"},"PeriodicalIF":2.0,"publicationDate":"2025-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11029376","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144255648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-05DOI: 10.1109/JEDS.2025.3576507
{"title":"IEEE ELECTRON DEVICES SOCIETY","authors":"","doi":"10.1109/JEDS.2025.3576507","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3576507","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"C2-C2"},"PeriodicalIF":2.0,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11026857","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144219691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-05DOI: 10.1109/JEDS.2025.3576795
Minseung Kang;Mingi Kim;Jaehyeon Kang;Jongun Won;Hyeong Jun Seo;Changhoon Joe;Youngchae Roh;Yeaji Park;Sangbum Kim
Capacitor-based analog synaptic circuit arrays proposed so far typically required more than three transistors per synapse to enable selective updates for parallel backpropagation updates. For the first time, an innovative update scheme that enables selective updating without requiring additional transistors is demonstrated. This approach is experimentally validated through an all-InGaZnO (IGZO) thin-film transistor (TFT) 3-transistor 1-capacitor (3T1C) synaptic circuit. IGZO TFTs are specifically chosen for their ability to extend retention times due to extremely low leakage currents and their simplified fabrication processes at low temperatures. Fundamental synaptic operations, including controllable weight updates, long data retention, and stable programming endurance, are confirmed experimentally. Additionally, optimizing operational voltage conditions improves weight update behavior, which enhances network training performance. System-level analysis using a neural network hardware simulator with a derived weight update model demonstrates high training accuracy on the MNIST handwritten digit dataset and achieves maximum accuracy over 98%. With the proposed selection method and tunable weight updates, 3T1C synaptic circuit is a promising candidate for scalable large-scale deep neural network accelerators based on analog compute-in-memory technology.
{"title":"Enabling Selective and Tunable Weight Updates in All-InGaZnO 3-Transistor 1-Capacitor Synaptic Circuits for On-Chip Training","authors":"Minseung Kang;Mingi Kim;Jaehyeon Kang;Jongun Won;Hyeong Jun Seo;Changhoon Joe;Youngchae Roh;Yeaji Park;Sangbum Kim","doi":"10.1109/JEDS.2025.3576795","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3576795","url":null,"abstract":"Capacitor-based analog synaptic circuit arrays proposed so far typically required more than three transistors per synapse to enable selective updates for parallel backpropagation updates. For the first time, an innovative update scheme that enables selective updating without requiring additional transistors is demonstrated. This approach is experimentally validated through an all-InGaZnO (IGZO) thin-film transistor (TFT) 3-transistor 1-capacitor (3T1C) synaptic circuit. IGZO TFTs are specifically chosen for their ability to extend retention times due to extremely low leakage currents and their simplified fabrication processes at low temperatures. Fundamental synaptic operations, including controllable weight updates, long data retention, and stable programming endurance, are confirmed experimentally. Additionally, optimizing operational voltage conditions improves weight update behavior, which enhances network training performance. System-level analysis using a neural network hardware simulator with a derived weight update model demonstrates high training accuracy on the MNIST handwritten digit dataset and achieves maximum accuracy over 98%. With the proposed selection method and tunable weight updates, 3T1C synaptic circuit is a promising candidate for scalable large-scale deep neural network accelerators based on analog compute-in-memory technology.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"510-515"},"PeriodicalIF":2.0,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11026025","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144367074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-04DOI: 10.1109/JEDS.2025.3576359
Sai Shubham;Nikhilesh Myanapuri;Siddharth Mohanty;Sandip Lashkare
Oscillatory Neural Networks (ONN) are inevitable when it comes to solving combinatorial optimization problems. ONNs are also extremely energy efficient for AI workloads compared to conventional Deep Neural Networks (DNNs). Analysis of fault and failure tolerance of ONNs is crucial for understanding the reliability of the networks. This work illustrates the fault tolerance of the ONN in solving constraint optimization problems such as vertex coloring and digit recognition problems. For vertex coloring, a 4-node network across various configurations and different component failure levels has been analyzed using a device oscillator. The findings confirm that the network is highly robust to failures, demonstrating tolerance to variations in resistance of up to 40% and in capacitance of up to 60%. The analysis was then extended to bigger networks varying from 16-node network to 784-node network, using a digital oscillator for digit recognition of digits 0, 1, and 7. The results suggest that the tolerance shoots up rapidly as the network size increases, enhancing the stability of the ONN, making it highly robust. A saturation point exists beyond which the law of diminishing returns is observed. A tolerance of up to 99.9% in frequency fault and up to 59% in stuck-at fault is observed for extremely large networks of size 784 neurons.
{"title":"Fault Tolerance of Oscillatory Neural Network: Device Oscillator-Based Small Network to Digital Oscillator-Based Large Networks","authors":"Sai Shubham;Nikhilesh Myanapuri;Siddharth Mohanty;Sandip Lashkare","doi":"10.1109/JEDS.2025.3576359","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3576359","url":null,"abstract":"Oscillatory Neural Networks (ONN) are inevitable when it comes to solving combinatorial optimization problems. ONNs are also extremely energy efficient for AI workloads compared to conventional Deep Neural Networks (DNNs). Analysis of fault and failure tolerance of ONNs is crucial for understanding the reliability of the networks. This work illustrates the fault tolerance of the ONN in solving constraint optimization problems such as vertex coloring and digit recognition problems. For vertex coloring, a 4-node network across various configurations and different component failure levels has been analyzed using a device oscillator. The findings confirm that the network is highly robust to failures, demonstrating tolerance to variations in resistance of up to 40% and in capacitance of up to 60%. The analysis was then extended to bigger networks varying from 16-node network to 784-node network, using a digital oscillator for digit recognition of digits 0, 1, and 7. The results suggest that the tolerance shoots up rapidly as the network size increases, enhancing the stability of the ONN, making it highly robust. A saturation point exists beyond which the law of diminishing returns is observed. A tolerance of up to 99.9% in frequency fault and up to 59% in stuck-at fault is observed for extremely large networks of size 784 neurons.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"899-908"},"PeriodicalIF":2.4,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11023548","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-02DOI: 10.1109/JEDS.2025.3575706
Martin Ćalasan;Snežana Vujošević;Kristina Bakić
This paper highlights significant advancements in the creation and enhancement of equivalent circuit models for solar cells. First, two novel configurations are proposed to enhance the classic single-diode model: one adds a diode between the terminal connections, while the other inserts a diode and resistor in series between the same terminals. Second, original analytical expressions for the current-voltage (I-V) characteristics of each proposed circuit are derived using the Lambert W function. Third, the performance of these models is rigorously evaluated on a variety of solar cells under diverse environmental conditions. Results demonstrated the models’ accuracy and robustness, with Root Mean Square Error (RMSE) analysis showing superior alignment between simulated and experimental I-V curves compared to existing single-, double-, and triple-diode solar cell models from the literature. Finally, the proposed approach enhances the mathematical precision in modeling solar cell behavior and provides a reliable framework for optimizing solar energy systems, contributing to improved performance and efficiency in practical applications.
{"title":"Enhanced Single-Diode Solar Cell Model: Analytical Solutions Using Lambert W Function and Circuit Innovations","authors":"Martin Ćalasan;Snežana Vujošević;Kristina Bakić","doi":"10.1109/JEDS.2025.3575706","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3575706","url":null,"abstract":"This paper highlights significant advancements in the creation and enhancement of equivalent circuit models for solar cells. First, two novel configurations are proposed to enhance the classic single-diode model: one adds a diode between the terminal connections, while the other inserts a diode and resistor in series between the same terminals. Second, original analytical expressions for the current-voltage (I-V) characteristics of each proposed circuit are derived using the Lambert W function. Third, the performance of these models is rigorously evaluated on a variety of solar cells under diverse environmental conditions. Results demonstrated the models’ accuracy and robustness, with Root Mean Square Error (RMSE) analysis showing superior alignment between simulated and experimental I-V curves compared to existing single-, double-, and triple-diode solar cell models from the literature. Finally, the proposed approach enhances the mathematical precision in modeling solar cell behavior and provides a reliable framework for optimizing solar energy systems, contributing to improved performance and efficiency in practical applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"501-509"},"PeriodicalIF":2.0,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11020651","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable $Delta $ VSN boosting, with a record-high ratio ($Delta $ VSN/$Delta $ VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (>1500 s) and ultra-fast writing speed (< 10 ns). Under the synergistic effect of VTH compensation and $Delta $ VSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array.
{"title":"IGZO 2T0C DRAM With VTH Compensation Technique for Multi-Bit Applications","authors":"Kaifei Chen;Wendong Lu;Jiebin Niu;Menggan Liu;Fuxi Liao;Xuanming Zhang;Zihan Li;Naide Mao;Kaiping Zhang;Congyan Lu;Bok-Moon Kang;Jiawei Wang;Di Geng;Nianduan Lu;Guilei Wang;Zhengyong Zhu;Guanhua Yang;Chao Zhao;Arokia Nathan;Ling Li;Ming Liu","doi":"10.1109/JEDS.2025.3565658","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3565658","url":null,"abstract":"In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN boosting, with a record-high ratio (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN/<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (>1500 s) and ultra-fast writing speed (< 10 ns). Under the synergistic effect of VTH compensation and <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"439-443"},"PeriodicalIF":2.0,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10979978","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144090732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-28DOI: 10.1109/JEDS.2025.3562252
{"title":"Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/JEDS.2025.3562252","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562252","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1078-1079"},"PeriodicalIF":2.0,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10978963","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-25DOI: 10.1109/JEDS.2025.3564212
Muhammad Mainul Islam;Mohammad Adnaan;Sou-Chi Chang;Hai Li;Ian A. Young;Azad Naeemi
Here, we present a compact model based on multidomain phase-field approach that can capture the hysteresis loop and the transient negative capacitance (NC) regions in Metal-Antiferroelectric-Metal structures. The model solves time-dependent Ginzburg-Landau (TDGL) and Poisson equation self-consistently to evaluate the polarization and potential distribution, respectively. We also discuss the significance of a dynamic kinetic coefficient to accurately capture the NC effect in antiferroelectric (AFE) capacitors. The proposed model adeptly captures all four transient NC regions (two antiferroelectric to ferroelectric transitions and two ferroelectric to antiferroelectric transitions) observed during a full switching cycle of an antiferroelectric capacitor.
{"title":"Investigating the Switching Dynamics of Antiferroelectric Capacitor Using Multidomain Phase-Field Approach","authors":"Muhammad Mainul Islam;Mohammad Adnaan;Sou-Chi Chang;Hai Li;Ian A. Young;Azad Naeemi","doi":"10.1109/JEDS.2025.3564212","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3564212","url":null,"abstract":"Here, we present a compact model based on multidomain phase-field approach that can capture the hysteresis loop and the transient negative capacitance (NC) regions in Metal-Antiferroelectric-Metal structures. The model solves time-dependent Ginzburg-Landau (TDGL) and Poisson equation self-consistently to evaluate the polarization and potential distribution, respectively. We also discuss the significance of a dynamic kinetic coefficient to accurately capture the NC effect in antiferroelectric (AFE) capacitors. The proposed model adeptly captures all four transient NC regions (two antiferroelectric to ferroelectric transitions and two ferroelectric to antiferroelectric transitions) observed during a full switching cycle of an antiferroelectric capacitor.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"422-426"},"PeriodicalIF":2.0,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10977732","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143943783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-24DOI: 10.1109/JEDS.2025.3563981
K. Murawski;K. Majkowycz;K. Michalczewski;J. Jureńczyk;Ł. Kubiszyn;T. Manyk;M. Kopytko;B. Seredyński;P. Martyniuk
The paper presents an analysis of the miniband transitions of long- infrared (LWIR) interband cascade photodetectors (ICIP), with type-II superlattices (T2SLs), gallium-free (“Ga-free”) InAs/InAsSb (xSb ${=}0.39$ ) absorber, grown by molecular beam epitaxy (MBE) on a GaAs (001) substrate. The results collected based on the photoluminescence (PL) and spectral response (SR) measurements were combined with theoretical calculations using the ($8times 8$ Hamiltonian) k$cdot $ p model for both strained and strain-free structure. The temperature dependence of HH${_{{1}}} rightarrow $ C1, LH${_{{1}}} rightarrow $ C1, SO$rightarrow $ C1 and HH${_{{1}}} rightarrow $ C1 was determined. Their respective 300 K energies were 114 meV, 195 meV, 290 meV and 380 meV, respectively. Moreover, the Varshni parameters were determined. For the PL results, 85 meV was observed across the entire temperature range. Remarkably, at cryogenic temperatures additional blue-shifted 5 meV and 14 meV transitions within the energy gap (Eg) occurred, respectively.
{"title":"Analysis of InAs/InAsSb Superlattice Miniband Positions for a Cascade LWIR Detector","authors":"K. Murawski;K. Majkowycz;K. Michalczewski;J. Jureńczyk;Ł. Kubiszyn;T. Manyk;M. Kopytko;B. Seredyński;P. Martyniuk","doi":"10.1109/JEDS.2025.3563981","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3563981","url":null,"abstract":"The paper presents an analysis of the miniband transitions of long- infrared (LWIR) interband cascade photodetectors (ICIP), with type-II superlattices (T2SLs), gallium-free (“Ga-free”) InAs/InAsSb (xSb <inline-formula> <tex-math>${=}0.39$ </tex-math></inline-formula>) absorber, grown by molecular beam epitaxy (MBE) on a GaAs (001) substrate. The results collected based on the photoluminescence (PL) and spectral response (SR) measurements were combined with theoretical calculations using the (<inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula> Hamiltonian) k<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>p model for both strained and strain-free structure. The temperature dependence of HH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1, LH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1, SO<inline-formula> <tex-math>$rightarrow $ </tex-math></inline-formula>C1 and HH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1 was determined. Their respective 300 K energies were 114 meV, 195 meV, 290 meV and 380 meV, respectively. Moreover, the Varshni parameters were determined. For the PL results, 85 meV was observed across the entire temperature range. Remarkably, at cryogenic temperatures additional blue-shifted 5 meV and 14 meV transitions within the energy gap (Eg) occurred, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"390-395"},"PeriodicalIF":2.0,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10975787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-23DOI: 10.1109/JEDS.2025.3563644
Xiaotian Tang;Qimeng Jiang;Sen Huang;Xinhua Wang;Xinyu Liu
The lossless and accurate current sensing technology is highly desirable for feedback control, fast over-current protection, and diagnostics-prognostics development for high-frequency and high-efficiency power systems. The SenseFET technology, where a current sensor is monolithically integrated with a power transistor, has been widely used in power ICs due to its high precision and low cost. However, for a gallium nitride (GaN) lateral power device in multi-finger configurations, the non-uniform temperature distribution hinders its application in high-precision scenarios. This paper aims to address this issue through a design method of SenseFETs based on a lumped parameter electro-thermal network (LPETN) model. Based on the proposed model, the time-dependent temperature and conduction current distribution are obtained, and the optimized finger selection for the accurate current sense is performed. The thermal network part of the model is validated by the finite element method (FEM) results, and the electrical part is validated through LTSPICE simulation. Finally, taking a 50-finger GaN high electron mobility transistor (HEMT) device as an example, this model is used to select the fingers of a SenseFET for current sensing. Compared with the traditional method, the proposed approach significantly improves the accuracy of the SenseFET, which demonstrates its effectiveness.
{"title":"High-Precision GaN-Based-SenseFET Design Based on a Lumped Parameter Electro-Thermal Network Model","authors":"Xiaotian Tang;Qimeng Jiang;Sen Huang;Xinhua Wang;Xinyu Liu","doi":"10.1109/JEDS.2025.3563644","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3563644","url":null,"abstract":"The lossless and accurate current sensing technology is highly desirable for feedback control, fast over-current protection, and diagnostics-prognostics development for high-frequency and high-efficiency power systems. The SenseFET technology, where a current sensor is monolithically integrated with a power transistor, has been widely used in power ICs due to its high precision and low cost. However, for a gallium nitride (GaN) lateral power device in multi-finger configurations, the non-uniform temperature distribution hinders its application in high-precision scenarios. This paper aims to address this issue through a design method of SenseFETs based on a lumped parameter electro-thermal network (LPETN) model. Based on the proposed model, the time-dependent temperature and conduction current distribution are obtained, and the optimized finger selection for the accurate current sense is performed. The thermal network part of the model is validated by the finite element method (FEM) results, and the electrical part is validated through LTSPICE simulation. Finally, taking a 50-finger GaN high electron mobility transistor (HEMT) device as an example, this model is used to select the fingers of a SenseFET for current sensing. Compared with the traditional method, the proposed approach significantly improves the accuracy of the SenseFET, which demonstrates its effectiveness.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"414-421"},"PeriodicalIF":2.0,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10974612","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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