Pub Date : 2025-07-28DOI: 10.1109/JEDS.2025.3593374
Yi Jiang;Luping Wang;Kai Chen;Rui Su;Luyu Yang;Dawei Gao;Junkang Li;Ran Cheng;Rui Zhang
This study shows a novel dual-frequency charge-pumping method, developed to quantitatively characterize the frequency response characteristics of interface traps at the HfO2/Si interface. The response frequency of the interface traps ($f_{it}$ ), or their capture/emission time, has been accurately evaluated in the range of 5-100 MHz across different energy levels by modulating the charge-pumping voltage waveforms. The analysis of $f_{it}$ provides valuable insights into the 1/f noise behavior of MOS devices, as confirmed by the observed correlation between 1/f noise and $f_{it}$ in the typical HfO2/Si n-MOSFETs. Additionally, it was found that the gate oxide traps are predominantly generated at a distance of 0.45 nm away from the HfO2/Si interface, and at an energy of 0.33 eV below conduction band minimum ($E_{c}$ ), under a PBTI stress.
{"title":"The Response Frequency of Interface Traps Using a Dual-Frequency Charge-Pumping Method and Its Correlation With 1/f Noise","authors":"Yi Jiang;Luping Wang;Kai Chen;Rui Su;Luyu Yang;Dawei Gao;Junkang Li;Ran Cheng;Rui Zhang","doi":"10.1109/JEDS.2025.3593374","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3593374","url":null,"abstract":"This study shows a novel dual-frequency charge-pumping method, developed to quantitatively characterize the frequency response characteristics of interface traps at the HfO2/Si interface. The response frequency of the interface traps (<inline-formula> <tex-math>$f_{it}$ </tex-math></inline-formula>), or their capture/emission time, has been accurately evaluated in the range of 5-100 MHz across different energy levels by modulating the charge-pumping voltage waveforms. The analysis of <inline-formula> <tex-math>$f_{it}$ </tex-math></inline-formula> provides valuable insights into the 1/f noise behavior of MOS devices, as confirmed by the observed correlation between 1/f noise and <inline-formula> <tex-math>$f_{it}$ </tex-math></inline-formula> in the typical HfO2/Si n-MOSFETs. Additionally, it was found that the gate oxide traps are predominantly generated at a distance of 0.45 nm away from the HfO2/Si interface, and at an energy of 0.33 eV below conduction band minimum (<inline-formula> <tex-math>$E_{c}$ </tex-math></inline-formula>), under a PBTI stress.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"947-953"},"PeriodicalIF":2.4,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11098707","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144853509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-16DOI: 10.1109/JEDS.2025.3589680
Seongwoo Kim;Gunwook Yoon;Seungjae Baik;Myounggon Kang
In this paper, we analyze the retention characteristics of vertical NAND(V-NAND) with dimpled (convex and concave) structures considering the impact of adjacent cell states. Additionally, we assess the efficiency of the previously proposed dummy cell program (DMP) in improving retention characteristics. Our results indicate that when the adjacent cell is in the erased state, the retention characteristics of the target cell are affected by conduction band $(E_{C})$ variations due to trapped electrons. The concave structure shows the best retention characteristics, whereas the convex structure shows the most degradation. This difference becomes even more pronounced when the adjacent cell is in the programmed state. However, when DMP is applied to the convex structure, which exhibits the most degraded retention characteristics, the greatest improvement is observed due to significant changes in channel potential $(V_{ch})$ caused by the fast-programming speed.
{"title":"Retention Characteristics and DMP Efficiency in V-NAND With Dimple Structure","authors":"Seongwoo Kim;Gunwook Yoon;Seungjae Baik;Myounggon Kang","doi":"10.1109/JEDS.2025.3589680","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3589680","url":null,"abstract":"In this paper, we analyze the retention characteristics of vertical NAND(V-NAND) with dimpled (convex and concave) structures considering the impact of adjacent cell states. Additionally, we assess the efficiency of the previously proposed dummy cell program (DMP) in improving retention characteristics. Our results indicate that when the adjacent cell is in the erased state, the retention characteristics of the target cell are affected by conduction band <inline-formula> <tex-math>$(E_{C})$ </tex-math></inline-formula> variations due to trapped electrons. The concave structure shows the best retention characteristics, whereas the convex structure shows the most degradation. This difference becomes even more pronounced when the adjacent cell is in the programmed state. However, when DMP is applied to the convex structure, which exhibits the most degraded retention characteristics, the greatest improvement is observed due to significant changes in channel potential <inline-formula> <tex-math>$(V_{ch})$ </tex-math></inline-formula> caused by the fast-programming speed.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"655-658"},"PeriodicalIF":2.4,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11082327","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-16DOI: 10.1109/JEDS.2025.3583305
Bin Yin;Weizhe Cui;Chuanhan Lin;Shihao Fu;Aidong Shen;Bingsheng Li
The metal/semiconductor (M/S) contact plays a crucial role in carrier collection efficiency and is a key factor in photoelectric conversion. To optimize the M/S contact of Al and $beta $ -Ga2O3, several annealing procedures were explored, including low-temperature annealing, direct Sn layer deposition, and face-to-face annealing. Among these methods, the $beta $ -Ga2O3-based solar-blind photodetector fabricated using face-to-face annealing—incorporating an ultra-thin Sn-doped high-conductivity layer—demonstrated superior performance. This device achieved an exceptionally high light-to-dark current ratio of $1.71times 10{^{{8}}}$ , with a responsivity of 14.13 A/W and a detectivity of $1.87times 10^{16}$ Jones at a 10 V bias under 255 nm irradiation ($23.75~mu $ w/cm2 light intensity). Additionally, it is capable of providing quick signal feedback, with a decay time of 2.81 ms/72.46 ms. The enhanced performance of the face-to-face annealing method is attributed to the formation of a more uniform ultra-thin Sn-doped conductive layer. This layer effectively lowers the barrier height at the M/S interface, improves carrier migration, and reduces contact resistance. These findings highlight that interface engineering through Sn-doped conductive layers is a promising strategy for optimizing the performance of $beta $ -Ga2O3-based photodetectors.
金属/半导体（M/S）接触对载流子收集效率起着至关重要的作用，是光电转换的关键因素。为了优化Al与$beta $ -Ga2O3的M/S接触，研究了低温退火、直接沉积Sn层和面对面退火等退火工艺。在这些方法中，采用面对面退火制备的$beta $ - ga2o3基太阳盲光电探测器（包含超薄掺杂锡的高导电性层）表现出优异的性能。该器件实现了极高的明暗电流比$1.71times 10{^{{8}}}$，响应率为14.13 a /W，在255 nm照射（$23.75~mu $ W /cm2光强）下，10v偏置下的探测率为$1.87times 10^{16}$ Jones。此外，它能够提供快速的信号反馈，衰减时间为2.81 ms/72.46 ms。面对面退火方法的性能增强是由于形成了更均匀的超薄掺杂锡导电层。该层有效降低了M/S界面的势垒高度，促进了载流子迁移，降低了接触电阻。这些发现突出表明，通过掺锡导电层进行界面工程是优化$beta $ - ga2o3光电探测器性能的一种很有前途的策略。
{"title":"Performance Optimization of β-Ga₂O₃-Based Solar-Blind Photodetector by Introducing an Ultra-Thin Sn-Doped High Conductivity Layer","authors":"Bin Yin;Weizhe Cui;Chuanhan Lin;Shihao Fu;Aidong Shen;Bingsheng Li","doi":"10.1109/JEDS.2025.3583305","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3583305","url":null,"abstract":"The metal/semiconductor (M/S) contact plays a crucial role in carrier collection efficiency and is a key factor in photoelectric conversion. To optimize the M/S contact of Al and <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3, several annealing procedures were explored, including low-temperature annealing, direct Sn layer deposition, and face-to-face annealing. Among these methods, the <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3-based solar-blind photodetector fabricated using face-to-face annealing—incorporating an ultra-thin Sn-doped high-conductivity layer—demonstrated superior performance. This device achieved an exceptionally high light-to-dark current ratio of <inline-formula> <tex-math>$1.71times 10{^{{8}}}$ </tex-math></inline-formula>, with a responsivity of 14.13 A/W and a detectivity of <inline-formula> <tex-math>$1.87times 10^{16}$ </tex-math></inline-formula> Jones at a 10 V bias under 255 nm irradiation (<inline-formula> <tex-math>$23.75~mu $ </tex-math></inline-formula>w/cm2 light intensity). Additionally, it is capable of providing quick signal feedback, with a decay time of 2.81 ms/72.46 ms. The enhanced performance of the face-to-face annealing method is attributed to the formation of a more uniform ultra-thin Sn-doped conductive layer. This layer effectively lowers the barrier height at the M/S interface, improves carrier migration, and reduces contact resistance. These findings highlight that interface engineering through Sn-doped conductive layers is a promising strategy for optimizing the performance of <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3-based photodetectors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"577-581"},"PeriodicalIF":2.0,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11082297","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144687625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-15DOI: 10.1109/JEDS.2025.3588398
Young-Eun Choi;Woo-Seok Kim;Myoung Kim;Junyoung Park;Min Woo Ryu;Kyung Rok Kim
In this work, we present a tunneling based ternary CMOS (T-CMOS) compact model for low power ternary-SRAM (T-SRAM) design using CMOS technology. By designing compact model parameters of band-to-band tunneling current $(I_{mathrm { BTBT}})$ according to effective doping concentration of T-CMOS, more accurate current model has been obtained in comparison with the conventional $I_{mathrm { BTBT}}$ models. In addition, parasitic capacitance models are obtained for transient operation. Comparing model and experimental data, it enables the prediction of T-CMOS performance under various $V_{mathrm { DD}}$ conditions. The model is validated to be more suitable for T-CMOS with low power on-chip memory applications.
{"title":"Ternary CMOS Compact Model for Low Power On-Chip Memory Applications","authors":"Young-Eun Choi;Woo-Seok Kim;Myoung Kim;Junyoung Park;Min Woo Ryu;Kyung Rok Kim","doi":"10.1109/JEDS.2025.3588398","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588398","url":null,"abstract":"In this work, we present a tunneling based ternary CMOS (T-CMOS) compact model for low power ternary-SRAM (T-SRAM) design using CMOS technology. By designing compact model parameters of band-to-band tunneling current <inline-formula> <tex-math>$(I_{mathrm { BTBT}})$ </tex-math></inline-formula> according to effective doping concentration of T-CMOS, more accurate current model has been obtained in comparison with the conventional <inline-formula> <tex-math>$I_{mathrm { BTBT}}$ </tex-math></inline-formula> models. In addition, parasitic capacitance models are obtained for transient operation. Comparing model and experimental data, it enables the prediction of T-CMOS performance under various <inline-formula> <tex-math>$V_{mathrm { DD}}$ </tex-math></inline-formula> conditions. The model is validated to be more suitable for T-CMOS with low power on-chip memory applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"599-606"},"PeriodicalIF":2.4,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11079606","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-15DOI: 10.1109/JEDS.2025.3589195
J. K. Lian;Y. Q. Chen;C. Liu;X. Y. Zhang
In this paper, supercritical hydrogen treatment is used to passivate the defects of normally-on type AlGaN/GaN high electron mobility transistors. By comparing the electrical characteristics of devices before and after the experiment, the treated devices have shown larger on-state current, a negative shift of threshold voltage and shorter gate-lag. In addition, the reliability of the devices before and after treatment is tested by applying a DC reverse bias stress to the gate and the result indicates that the treated devices show less degradation after RB stress. At the same time, through the low-frequency noise test, it is further verified that the defect density near the 2DEG channel reduced from $1.25 times 10^{20}~ {mathrm {cm}}^{-3}{mathrm {eV}}^{-1}$ to $8.94 times 10^{18}~ {mathrm {cm}}^{-3}{mathrm {eV}}^{-1}$ . Based on the above results, a physical model is proposed to demonstrate the passivation mechanism. The original passivation layer and AlGaN barrier layer have many dangling bond defects that can capture electrons and cause virtual gate effect. Supercritical hydrogen penetrates into the material substrate and passivates the dangling bonds. The result of this experiment provides a significant reference for the research of improving the reliability of AlGaN/GaN HEMTs.
{"title":"Defects Passivation and Performance Enhancement of AlGaN/GaN HEMTs by Supercritical Hydrogen Treatment","authors":"J. K. Lian;Y. Q. Chen;C. Liu;X. Y. Zhang","doi":"10.1109/JEDS.2025.3589195","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3589195","url":null,"abstract":"In this paper, supercritical hydrogen treatment is used to passivate the defects of normally-on type AlGaN/GaN high electron mobility transistors. By comparing the electrical characteristics of devices before and after the experiment, the treated devices have shown larger on-state current, a negative shift of threshold voltage and shorter gate-lag. In addition, the reliability of the devices before and after treatment is tested by applying a DC reverse bias stress to the gate and the result indicates that the treated devices show less degradation after RB stress. At the same time, through the low-frequency noise test, it is further verified that the defect density near the 2DEG channel reduced from <inline-formula> <tex-math>$1.25 times 10^{20}~ {mathrm {cm}}^{-3}{mathrm {eV}}^{-1}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$8.94 times 10^{18}~ {mathrm {cm}}^{-3}{mathrm {eV}}^{-1}$ </tex-math></inline-formula>. Based on the above results, a physical model is proposed to demonstrate the passivation mechanism. The original passivation layer and AlGaN barrier layer have many dangling bond defects that can capture electrons and cause virtual gate effect. Supercritical hydrogen penetrates into the material substrate and passivates the dangling bonds. The result of this experiment provides a significant reference for the research of improving the reliability of AlGaN/GaN HEMTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"625-629"},"PeriodicalIF":2.4,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11080297","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-14DOI: 10.1109/JEDS.2025.3588862
Yi Wang;Xinqiang Pan;Qin Xie;Junde Tong;Yao Shuai;Wenbo Luo;Chuangui Wu;Wanli Zhang
As a novel device, memristors attracted great attention because of its potential in neural network computing. However, the nonideal factors of memristors, such as conductance drift and programming errors, limit their performance in practical applications. Single-crystalline LiNbO₃ thin film memristor (LN memristor) exhibited good characteristics for neural network computing, but few work about the nonideal factors of the memristor has been reported. This work aims to model these nonideal factors of the LN memristor and explore the influence of these nonideal factors on the memristor-based neural network computing. We extracted key nonideal parameters from the fabricated LN memristor and established the phenomenological model. The model results agree with the measured results, which proves the validity of the model. We embedded these models into the device simulation platform to evaluate the effects of different nonideal factors on memristor-based neural network. This study provides an efficient way to model the nonideal factors of the LN memristor, which can accurately capture the complex behavior of the LN memristor in practical applications. In addition, through the modelling and analysis, researchers can better understand the mechanism of the LN memristor, so as to optimize memristor design and improve memristor performance for the neural network computing.
{"title":"Phenomenological Modeling on the Nonideal Factors of Memristor Based on Single-Crystalline LiNbO₃ Thin Film","authors":"Yi Wang;Xinqiang Pan;Qin Xie;Junde Tong;Yao Shuai;Wenbo Luo;Chuangui Wu;Wanli Zhang","doi":"10.1109/JEDS.2025.3588862","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588862","url":null,"abstract":"As a novel device, memristors attracted great attention because of its potential in neural network computing. However, the nonideal factors of memristors, such as conductance drift and programming errors, limit their performance in practical applications. Single-crystalline LiNbO₃ thin film memristor (LN memristor) exhibited good characteristics for neural network computing, but few work about the nonideal factors of the memristor has been reported. This work aims to model these nonideal factors of the LN memristor and explore the influence of these nonideal factors on the memristor-based neural network computing. We extracted key nonideal parameters from the fabricated LN memristor and established the phenomenological model. The model results agree with the measured results, which proves the validity of the model. We embedded these models into the device simulation platform to evaluate the effects of different nonideal factors on memristor-based neural network. This study provides an efficient way to model the nonideal factors of the LN memristor, which can accurately capture the complex behavior of the LN memristor in practical applications. In addition, through the modelling and analysis, researchers can better understand the mechanism of the LN memristor, so as to optimize memristor design and improve memristor performance for the neural network computing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"587-592"},"PeriodicalIF":2.4,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11079929","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Heterosubstrates have been extensively studied as a method to improve the heat dissipation of Ga2O3 devices. In this simulation work, we propose a novel role for p-type available heterosubstrates, as a component of a reduced surface field (RESURF) structure in Ga2O3 lateral field-effect transistors (FETs). The RESURF structure can eliminate the electric field crowding and contribute to higher breakdown voltage. Using SiC as an example, the designing strategy for doping concentration and dimensions of the p-type region is systematically studied using TCAD modeling. Meanwhile, the interface charges and Al2O3 interlayer that could exist in realistic devices are mimicked in the simulation. Additionally, the feasibility of the RESURF structure for high-frequency switching operation is supported by the simulation on charging/discharging time the p-SiC depletion region. This study demonstrates the great potential of utilizing the electrical properties of heat-dissipating heterosubstrates to achieve a uniform electric field distribution in Ga2O3 FETs.
{"title":"RESURF Ga2O3-on-SiC Field Effect Transistors for Enhanced Breakdown Voltage","authors":"Junting Chen;Xiaohan Zhang;Junlei Zhao;Jin Wei;Mengyuan Hua","doi":"10.1109/JEDS.2025.3584977","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3584977","url":null,"abstract":"Heterosubstrates have been extensively studied as a method to improve the heat dissipation of Ga2O3 devices. In this simulation work, we propose a novel role for p-type available heterosubstrates, as a component of a reduced surface field (RESURF) structure in Ga2O3 lateral field-effect transistors (FETs). The RESURF structure can eliminate the electric field crowding and contribute to higher breakdown voltage. Using SiC as an example, the designing strategy for doping concentration and dimensions of the p-type region is systematically studied using TCAD modeling. Meanwhile, the interface charges and Al2O3 interlayer that could exist in realistic devices are mimicked in the simulation. Additionally, the feasibility of the RESURF structure for high-frequency switching operation is supported by the simulation on charging/discharging time the p-SiC depletion region. This study demonstrates the great potential of utilizing the electrical properties of heat-dissipating heterosubstrates to achieve a uniform electric field distribution in Ga2O3 FETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"570-576"},"PeriodicalIF":2.0,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11080126","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144671218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-14DOI: 10.1109/JEDS.2025.3588470
Yongzheng Li;Xiaoyu Weng;Kai-Da Xu
In this paper, two compact on-chip bandpass filters (BPFs) at millimeter-wave frequencies, i.e., single-band BPF and dual-band BPF, are proposed in gallium arsenide (GaAs) technology. To understand the working mechanism of the single-band BPF, a transmission line (TL) equivalent circuit model is presented and analyzed to estimate the position of the transmission zeros (TZs). Based on the single-band BPF structure, two additional metallic strips on M1 layer are placed beneath the pair of meander strips to construct a dual-band BPF. Consequently, a dual-band frequency response can be realized by introducing two TZs within the passband. For demonstration, two prototypes of the BPF are fabricated and tested to validate the proposed idea, whose simulated and measured results are in good agreement. Both of the single- and dual-band BPFs have the same chip size of only 0.29 mm $times 0$ .23 mm, excluding the feeding.
本文在砷化镓（GaAs）技术中提出了两种毫米波频率下的紧凑型片上带通滤波器（BPF），即单带带通滤波器和双带带通滤波器。为了理解单频段BPF的工作机理，提出并分析了传输线等效电路模型，以估计传输零点的位置。在单带BPF结构的基础上，在M1层上的两个额外的金属带放置在一对弯曲带的下方，以构建双带BPF。因此，可以通过在通带内引入两个TZs来实现双带频率响应。为了验证所提出的想法，制作了两个BPF原型并进行了测试，其模拟和测量结果很好地吻合。单频和双频bpf的芯片尺寸相同，仅为0.29 mm × 0.23 mm（不包括馈电）。
{"title":"Compact Millimeter-Wave Single- and Dual-Band On-Chip Bandpass Filters Using GaAs Technology","authors":"Yongzheng Li;Xiaoyu Weng;Kai-Da Xu","doi":"10.1109/JEDS.2025.3588470","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588470","url":null,"abstract":"In this paper, two compact on-chip bandpass filters (BPFs) at millimeter-wave frequencies, i.e., single-band BPF and dual-band BPF, are proposed in gallium arsenide (GaAs) technology. To understand the working mechanism of the single-band BPF, a transmission line (TL) equivalent circuit model is presented and analyzed to estimate the position of the transmission zeros (TZs). Based on the single-band BPF structure, two additional metallic strips on M1 layer are placed beneath the pair of meander strips to construct a dual-band BPF. Consequently, a dual-band frequency response can be realized by introducing two TZs within the passband. For demonstration, two prototypes of the BPF are fabricated and tested to validate the proposed idea, whose simulated and measured results are in good agreement. Both of the single- and dual-band BPFs have the same chip size of only 0.29 mm <inline-formula> <tex-math>$times 0$ </tex-math></inline-formula>.23 mm, excluding the feeding.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"649-654"},"PeriodicalIF":2.4,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11079645","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-14DOI: 10.1109/JEDS.2025.3588675
Soumen Deb;Amitava DasGupta;Nandita DasGupta
A physics based model for the off-state lateral electric field in the channel of an AlGaN/GaN High Electron Mobility Transistor (HEMT) is developed by solving 2-D Poison’s equation under the gate and considering piecewise linear approximation of the lateral electric field in the depletion region adjacent to the gate edge in drain access region. The model is used to calculate the impact ionisation factor and hence the breakdown voltage of the device. The results obtained from the model show an excellent match with simulation results obtained from Sentaurus TCAD for a wide range of design parameters of the device such as Al-mole fraction in AlGaN barrier layer, as well as gate and drain biases.
{"title":"Analytical Modeling for Off-State Lateral Electric Field and Breakdown Voltage of AlGaN/GaN HEMTs","authors":"Soumen Deb;Amitava DasGupta;Nandita DasGupta","doi":"10.1109/JEDS.2025.3588675","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588675","url":null,"abstract":"A physics based model for the off-state lateral electric field in the channel of an AlGaN/GaN High Electron Mobility Transistor (HEMT) is developed by solving 2-D Poison’s equation under the gate and considering piecewise linear approximation of the lateral electric field in the depletion region adjacent to the gate edge in drain access region. The model is used to calculate the impact ionisation factor and hence the breakdown voltage of the device. The results obtained from the model show an excellent match with simulation results obtained from Sentaurus TCAD for a wide range of design parameters of the device such as Al-mole fraction in AlGaN barrier layer, as well as gate and drain biases.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"615-624"},"PeriodicalIF":2.4,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11079609","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-14DOI: 10.1109/JEDS.2025.3588814
Jun-Yi Lin;Sung-Wei Huang;Jenn-Gwo Hwu
In this research, the steady-state and transient behavior of the p-type metal-insulator-semiconductor (MIS) tunnel-diodes (TD) with ultra-edge-thickened (UET) oxide was studied, utilizing experimental results and TCAD simulations. The investigation explores how the gate voltage (VG) influences the gate current (IG). Additionally, the impact of the thin oxide area under the gate (Athin) on IG is examined. When VG < VFB, which is in forward bias, IG is directly proportional to Athin, resulting in a larger |IG| for the planar devices with only thin oxide. Conversely, for V${}_{text {G}} gt $ 0 V, the UET devices exhibit a higher IG compared to the planar device due to more electrons supplied from the region outside the gate. The UET device, compared to the planar device, shows an enhancement of over one hundred times larger magnitude of transient current. Also, the UET devices featuring the larger Athin display a greater magnitude of transient current. However, the enhancement of transient current becomes saturated when the portions of thin and thick oxide are almost equal in area. The magnitudes of the transient currents of the UET devices are sampled at 60 ms after switching VG from write to 0 V. Endurance characteristic is also measured, revealing minimal changes after 1000 write and read cycles. To elucidate the mechanism behind the steady-state and transient current behavior, simulations are employed for both the steady-state and transient situations.
{"title":"Enhancement of the Transient Current Behavior of MIS Tunnel Diodes With Ultra-Edge-Thickened (UET) Oxide under the Consideration of Tunnel Oxide Areas","authors":"Jun-Yi Lin;Sung-Wei Huang;Jenn-Gwo Hwu","doi":"10.1109/JEDS.2025.3588814","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588814","url":null,"abstract":"In this research, the steady-state and transient behavior of the p-type metal-insulator-semiconductor (MIS) tunnel-diodes (TD) with ultra-edge-thickened (UET) oxide was studied, utilizing experimental results and TCAD simulations. The investigation explores how the gate voltage (VG) influences the gate current (IG). Additionally, the impact of the thin oxide area under the gate (Athin) on IG is examined. When VG < VFB, which is in forward bias, IG is directly proportional to Athin, resulting in a larger |IG| for the planar devices with only thin oxide. Conversely, for V<inline-formula> <tex-math>${}_{text {G}} gt $ </tex-math></inline-formula> 0 V, the UET devices exhibit a higher IG compared to the planar device due to more electrons supplied from the region outside the gate. The UET device, compared to the planar device, shows an enhancement of over one hundred times larger magnitude of transient current. Also, the UET devices featuring the larger Athin display a greater magnitude of transient current. However, the enhancement of transient current becomes saturated when the portions of thin and thick oxide are almost equal in area. The magnitudes of the transient currents of the UET devices are sampled at 60 ms after switching VG from write to 0 V. Endurance characteristic is also measured, revealing minimal changes after 1000 write and read cycles. To elucidate the mechanism behind the steady-state and transient current behavior, simulations are employed for both the steady-state and transient situations.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"607-614"},"PeriodicalIF":2.4,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11079924","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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