Pub Date : 2025-07-14DOI: 10.1109/JEDS.2025.3588862
Yi Wang;Xinqiang Pan;Qin Xie;Junde Tong;Yao Shuai;Wenbo Luo;Chuangui Wu;Wanli Zhang
As a novel device, memristors attracted great attention because of its potential in neural network computing. However, the nonideal factors of memristors, such as conductance drift and programming errors, limit their performance in practical applications. Single-crystalline LiNbO₃ thin film memristor (LN memristor) exhibited good characteristics for neural network computing, but few work about the nonideal factors of the memristor has been reported. This work aims to model these nonideal factors of the LN memristor and explore the influence of these nonideal factors on the memristor-based neural network computing. We extracted key nonideal parameters from the fabricated LN memristor and established the phenomenological model. The model results agree with the measured results, which proves the validity of the model. We embedded these models into the device simulation platform to evaluate the effects of different nonideal factors on memristor-based neural network. This study provides an efficient way to model the nonideal factors of the LN memristor, which can accurately capture the complex behavior of the LN memristor in practical applications. In addition, through the modelling and analysis, researchers can better understand the mechanism of the LN memristor, so as to optimize memristor design and improve memristor performance for the neural network computing.
{"title":"Phenomenological Modeling on the Nonideal Factors of Memristor Based on Single-Crystalline LiNbO₃ Thin Film","authors":"Yi Wang;Xinqiang Pan;Qin Xie;Junde Tong;Yao Shuai;Wenbo Luo;Chuangui Wu;Wanli Zhang","doi":"10.1109/JEDS.2025.3588862","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588862","url":null,"abstract":"As a novel device, memristors attracted great attention because of its potential in neural network computing. However, the nonideal factors of memristors, such as conductance drift and programming errors, limit their performance in practical applications. Single-crystalline LiNbO₃ thin film memristor (LN memristor) exhibited good characteristics for neural network computing, but few work about the nonideal factors of the memristor has been reported. This work aims to model these nonideal factors of the LN memristor and explore the influence of these nonideal factors on the memristor-based neural network computing. We extracted key nonideal parameters from the fabricated LN memristor and established the phenomenological model. The model results agree with the measured results, which proves the validity of the model. We embedded these models into the device simulation platform to evaluate the effects of different nonideal factors on memristor-based neural network. This study provides an efficient way to model the nonideal factors of the LN memristor, which can accurately capture the complex behavior of the LN memristor in practical applications. In addition, through the modelling and analysis, researchers can better understand the mechanism of the LN memristor, so as to optimize memristor design and improve memristor performance for the neural network computing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"587-592"},"PeriodicalIF":2.4,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11079929","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Heterosubstrates have been extensively studied as a method to improve the heat dissipation of Ga2O3 devices. In this simulation work, we propose a novel role for p-type available heterosubstrates, as a component of a reduced surface field (RESURF) structure in Ga2O3 lateral field-effect transistors (FETs). The RESURF structure can eliminate the electric field crowding and contribute to higher breakdown voltage. Using SiC as an example, the designing strategy for doping concentration and dimensions of the p-type region is systematically studied using TCAD modeling. Meanwhile, the interface charges and Al2O3 interlayer that could exist in realistic devices are mimicked in the simulation. Additionally, the feasibility of the RESURF structure for high-frequency switching operation is supported by the simulation on charging/discharging time the p-SiC depletion region. This study demonstrates the great potential of utilizing the electrical properties of heat-dissipating heterosubstrates to achieve a uniform electric field distribution in Ga2O3 FETs.
{"title":"RESURF Ga2O3-on-SiC Field Effect Transistors for Enhanced Breakdown Voltage","authors":"Junting Chen;Xiaohan Zhang;Junlei Zhao;Jin Wei;Mengyuan Hua","doi":"10.1109/JEDS.2025.3584977","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3584977","url":null,"abstract":"Heterosubstrates have been extensively studied as a method to improve the heat dissipation of Ga2O3 devices. In this simulation work, we propose a novel role for p-type available heterosubstrates, as a component of a reduced surface field (RESURF) structure in Ga2O3 lateral field-effect transistors (FETs). The RESURF structure can eliminate the electric field crowding and contribute to higher breakdown voltage. Using SiC as an example, the designing strategy for doping concentration and dimensions of the p-type region is systematically studied using TCAD modeling. Meanwhile, the interface charges and Al2O3 interlayer that could exist in realistic devices are mimicked in the simulation. Additionally, the feasibility of the RESURF structure for high-frequency switching operation is supported by the simulation on charging/discharging time the p-SiC depletion region. This study demonstrates the great potential of utilizing the electrical properties of heat-dissipating heterosubstrates to achieve a uniform electric field distribution in Ga2O3 FETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"570-576"},"PeriodicalIF":2.0,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11080126","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144671218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-14DOI: 10.1109/JEDS.2025.3588470
Yongzheng Li;Xiaoyu Weng;Kai-Da Xu
In this paper, two compact on-chip bandpass filters (BPFs) at millimeter-wave frequencies, i.e., single-band BPF and dual-band BPF, are proposed in gallium arsenide (GaAs) technology. To understand the working mechanism of the single-band BPF, a transmission line (TL) equivalent circuit model is presented and analyzed to estimate the position of the transmission zeros (TZs). Based on the single-band BPF structure, two additional metallic strips on M1 layer are placed beneath the pair of meander strips to construct a dual-band BPF. Consequently, a dual-band frequency response can be realized by introducing two TZs within the passband. For demonstration, two prototypes of the BPF are fabricated and tested to validate the proposed idea, whose simulated and measured results are in good agreement. Both of the single- and dual-band BPFs have the same chip size of only 0.29 mm $times 0$ .23 mm, excluding the feeding.
本文在砷化镓（GaAs）技术中提出了两种毫米波频率下的紧凑型片上带通滤波器（BPF），即单带带通滤波器和双带带通滤波器。为了理解单频段BPF的工作机理，提出并分析了传输线等效电路模型，以估计传输零点的位置。在单带BPF结构的基础上，在M1层上的两个额外的金属带放置在一对弯曲带的下方，以构建双带BPF。因此，可以通过在通带内引入两个TZs来实现双带频率响应。为了验证所提出的想法，制作了两个BPF原型并进行了测试，其模拟和测量结果很好地吻合。单频和双频bpf的芯片尺寸相同，仅为0.29 mm × 0.23 mm（不包括馈电）。
{"title":"Compact Millimeter-Wave Single- and Dual-Band On-Chip Bandpass Filters Using GaAs Technology","authors":"Yongzheng Li;Xiaoyu Weng;Kai-Da Xu","doi":"10.1109/JEDS.2025.3588470","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588470","url":null,"abstract":"In this paper, two compact on-chip bandpass filters (BPFs) at millimeter-wave frequencies, i.e., single-band BPF and dual-band BPF, are proposed in gallium arsenide (GaAs) technology. To understand the working mechanism of the single-band BPF, a transmission line (TL) equivalent circuit model is presented and analyzed to estimate the position of the transmission zeros (TZs). Based on the single-band BPF structure, two additional metallic strips on M1 layer are placed beneath the pair of meander strips to construct a dual-band BPF. Consequently, a dual-band frequency response can be realized by introducing two TZs within the passband. For demonstration, two prototypes of the BPF are fabricated and tested to validate the proposed idea, whose simulated and measured results are in good agreement. Both of the single- and dual-band BPFs have the same chip size of only 0.29 mm <inline-formula> <tex-math>$times 0$ </tex-math></inline-formula>.23 mm, excluding the feeding.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"649-654"},"PeriodicalIF":2.4,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11079645","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-14DOI: 10.1109/JEDS.2025.3588675
Soumen Deb;Amitava DasGupta;Nandita DasGupta
A physics based model for the off-state lateral electric field in the channel of an AlGaN/GaN High Electron Mobility Transistor (HEMT) is developed by solving 2-D Poison’s equation under the gate and considering piecewise linear approximation of the lateral electric field in the depletion region adjacent to the gate edge in drain access region. The model is used to calculate the impact ionisation factor and hence the breakdown voltage of the device. The results obtained from the model show an excellent match with simulation results obtained from Sentaurus TCAD for a wide range of design parameters of the device such as Al-mole fraction in AlGaN barrier layer, as well as gate and drain biases.
{"title":"Analytical Modeling for Off-State Lateral Electric Field and Breakdown Voltage of AlGaN/GaN HEMTs","authors":"Soumen Deb;Amitava DasGupta;Nandita DasGupta","doi":"10.1109/JEDS.2025.3588675","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588675","url":null,"abstract":"A physics based model for the off-state lateral electric field in the channel of an AlGaN/GaN High Electron Mobility Transistor (HEMT) is developed by solving 2-D Poison’s equation under the gate and considering piecewise linear approximation of the lateral electric field in the depletion region adjacent to the gate edge in drain access region. The model is used to calculate the impact ionisation factor and hence the breakdown voltage of the device. The results obtained from the model show an excellent match with simulation results obtained from Sentaurus TCAD for a wide range of design parameters of the device such as Al-mole fraction in AlGaN barrier layer, as well as gate and drain biases.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"615-624"},"PeriodicalIF":2.4,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11079609","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-14DOI: 10.1109/JEDS.2025.3588814
Jun-Yi Lin;Sung-Wei Huang;Jenn-Gwo Hwu
In this research, the steady-state and transient behavior of the p-type metal-insulator-semiconductor (MIS) tunnel-diodes (TD) with ultra-edge-thickened (UET) oxide was studied, utilizing experimental results and TCAD simulations. The investigation explores how the gate voltage (VG) influences the gate current (IG). Additionally, the impact of the thin oxide area under the gate (Athin) on IG is examined. When VG < VFB, which is in forward bias, IG is directly proportional to Athin, resulting in a larger |IG| for the planar devices with only thin oxide. Conversely, for V${}_{text {G}} gt $ 0 V, the UET devices exhibit a higher IG compared to the planar device due to more electrons supplied from the region outside the gate. The UET device, compared to the planar device, shows an enhancement of over one hundred times larger magnitude of transient current. Also, the UET devices featuring the larger Athin display a greater magnitude of transient current. However, the enhancement of transient current becomes saturated when the portions of thin and thick oxide are almost equal in area. The magnitudes of the transient currents of the UET devices are sampled at 60 ms after switching VG from write to 0 V. Endurance characteristic is also measured, revealing minimal changes after 1000 write and read cycles. To elucidate the mechanism behind the steady-state and transient current behavior, simulations are employed for both the steady-state and transient situations.
{"title":"Enhancement of the Transient Current Behavior of MIS Tunnel Diodes With Ultra-Edge-Thickened (UET) Oxide under the Consideration of Tunnel Oxide Areas","authors":"Jun-Yi Lin;Sung-Wei Huang;Jenn-Gwo Hwu","doi":"10.1109/JEDS.2025.3588814","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588814","url":null,"abstract":"In this research, the steady-state and transient behavior of the p-type metal-insulator-semiconductor (MIS) tunnel-diodes (TD) with ultra-edge-thickened (UET) oxide was studied, utilizing experimental results and TCAD simulations. The investigation explores how the gate voltage (VG) influences the gate current (IG). Additionally, the impact of the thin oxide area under the gate (Athin) on IG is examined. When VG < VFB, which is in forward bias, IG is directly proportional to Athin, resulting in a larger |IG| for the planar devices with only thin oxide. Conversely, for V<inline-formula> <tex-math>${}_{text {G}} gt $ </tex-math></inline-formula> 0 V, the UET devices exhibit a higher IG compared to the planar device due to more electrons supplied from the region outside the gate. The UET device, compared to the planar device, shows an enhancement of over one hundred times larger magnitude of transient current. Also, the UET devices featuring the larger Athin display a greater magnitude of transient current. However, the enhancement of transient current becomes saturated when the portions of thin and thick oxide are almost equal in area. The magnitudes of the transient currents of the UET devices are sampled at 60 ms after switching VG from write to 0 V. Endurance characteristic is also measured, revealing minimal changes after 1000 write and read cycles. To elucidate the mechanism behind the steady-state and transient current behavior, simulations are employed for both the steady-state and transient situations.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"607-614"},"PeriodicalIF":2.4,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11079924","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-11DOI: 10.1109/JEDS.2025.3588210
Pingyu Cao;Kepeng Zhao;Yihao Xu;Harm Van Zalinge;Sang Lam;Ping Zhang;Miao Cui;Fei Xue
A monolithically integrated voltage reference based on p-GaN HEMT technology is demonstrated in this work. The proposed two-stage structure can improve the stability of the generated reference voltage over a wide range of the supply voltage and temperature. The static and dynamic performance was measured at various temperatures. Experimental results indicate that the output voltage is stable at 1.3 V when the supply voltage rises from 2.8 V to 40 V, with a line sensitivity of 0.035%/V at room temperature. When the measurement temperature increases to $250~{^{circ }}$ C, the generated reference voltage slightly decreases to 1.25 V with a temperature coefficient of −22.1 ppm/°C. The power supply rejection ratio of this work is competitive, as the power supply rejection ratio changes from −46.64 dB to −56.2 dB, in which the noise frequency varies from 10 Hz to 5 MHz. The voltage variation of the generated reference voltage is relatively small when the frequency exceeds 5 MHz. The results show that the proposed work is particularly suitable for all-GaN monolithic integration circuits that require thermally stable bias voltages with high immunity to the supply voltage variation.
{"title":"A p-GaN HEMT Voltage Reference With High Line Sensitivity and Power Supply Rejection Ratio","authors":"Pingyu Cao;Kepeng Zhao;Yihao Xu;Harm Van Zalinge;Sang Lam;Ping Zhang;Miao Cui;Fei Xue","doi":"10.1109/JEDS.2025.3588210","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588210","url":null,"abstract":"A monolithically integrated voltage reference based on p-GaN HEMT technology is demonstrated in this work. The proposed two-stage structure can improve the stability of the generated reference voltage over a wide range of the supply voltage and temperature. The static and dynamic performance was measured at various temperatures. Experimental results indicate that the output voltage is stable at 1.3 V when the supply voltage rises from 2.8 V to 40 V, with a line sensitivity of 0.035%/V at room temperature. When the measurement temperature increases to <inline-formula> <tex-math>$250~{^{circ }}$ </tex-math></inline-formula>C, the generated reference voltage slightly decreases to 1.25 V with a temperature coefficient of −22.1 ppm/°C. The power supply rejection ratio of this work is competitive, as the power supply rejection ratio changes from −46.64 dB to −56.2 dB, in which the noise frequency varies from 10 Hz to 5 MHz. The voltage variation of the generated reference voltage is relatively small when the frequency exceeds 5 MHz. The results show that the proposed work is particularly suitable for all-GaN monolithic integration circuits that require thermally stable bias voltages with high immunity to the supply voltage variation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"630-637"},"PeriodicalIF":2.4,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11078414","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-11DOI: 10.1109/JEDS.2025.3588180
Taeyoung Cho;Jesun Park;Sungyeop Jung;Myounggon Kang
This paper analyzes the intrinsic capacitance of enhancement-mode (e-mode) Gallium Nitridebased High Electron Mobility Transistor (GaN HEMTs). The intrinsic capacitance was measured using $C_{i s s}$ (input capacitance), $C_{o s s}$ (output capacitance), and $C_{r s s}$ (reverse transfer capacitance). The $C_{o s s}$ was also analyzed. Based on depletion-mode (d-mode) measurement data from the MIT virtual source GaN HEMT (MVSG) compact model, a measurement circuit for $C_{i s s}, C_{o s s}$ and $C_{r s s}$ was constructed and calibrated for reliability. Subsequently, the circuit, initially configured for d-mode GaN HEMT intrinsic capacitance measurements, was optimized for e-mode GaN HEMT, upon which intrinsic capacitance was measured. The influence on the graph was analyzed by varying parameters in the measured capacitance data, leading to the modeling of intrinsic capacitance.
分析了增强型氮化镓基高电子迁移率晶体管（GaN HEMTs）的本征电容。本征电容采用$C_{i s s}$（输入电容）、$C_{o s}$（输出电容）和$C_{r s s}$（反向传递电容）测量。对$C_{0 s}$也进行了分析。基于MIT虚拟源GaN HEMT （MVSG）紧凑模型的耗尽模式（d-mode）测量数据，构建了$C_{i s s}、$C_{o s s}$和$C_{r s s}$的测量电路，并对其进行了可靠性校准。随后，将最初配置用于d模GaN HEMT固有电容测量的电路优化为用于e模GaN HEMT，并在此基础上测量固有电容。通过改变测量电容数据中的参数来分析对图形的影响，从而建立本征电容的模型。
{"title":"Analysis and Modeling of Intrinsic Capacitance in Enhancement Mode GaN HEMT","authors":"Taeyoung Cho;Jesun Park;Sungyeop Jung;Myounggon Kang","doi":"10.1109/JEDS.2025.3588180","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588180","url":null,"abstract":"This paper analyzes the intrinsic capacitance of enhancement-mode (e-mode) Gallium Nitridebased High Electron Mobility Transistor (GaN HEMTs). The intrinsic capacitance was measured using <inline-formula> <tex-math>$C_{i s s}$ </tex-math></inline-formula> (input capacitance), <inline-formula> <tex-math>$C_{o s s}$ </tex-math></inline-formula> (output capacitance), and <inline-formula> <tex-math>$C_{r s s}$ </tex-math></inline-formula> (reverse transfer capacitance). The <inline-formula> <tex-math>$C_{o s s}$ </tex-math></inline-formula> was also analyzed. Based on depletion-mode (d-mode) measurement data from the MIT virtual source GaN HEMT (MVSG) compact model, a measurement circuit for <inline-formula> <tex-math>$C_{i s s}, C_{o s s}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$C_{r s s}$ </tex-math></inline-formula> was constructed and calibrated for reliability. Subsequently, the circuit, initially configured for d-mode GaN HEMT intrinsic capacitance measurements, was optimized for e-mode GaN HEMT, upon which intrinsic capacitance was measured. The influence on the graph was analyzed by varying parameters in the measured capacitance data, leading to the modeling of intrinsic capacitance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"638-641"},"PeriodicalIF":2.4,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11078449","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-03DOI: 10.1109/JEDS.2025.3585619
Bo Chen;Yifan Wu;Yuwei Qu;Anlin Liu;Yuzhe Hu;Pengpeng Sang;Jixuan Wu;Xuepeng Zhan;Jiezhi Chen
Hardware neural networks based on emerging nonvolatile memory are promising candidates to overcome the Von Neumann computing bottleneck. This study investigates the device characteristics and reliability of ferroelectric field-effect transistors (FeFETs) with a focus on their temperature-dependent performance. At 300 K, the FeFET demonstrates a 6.2 V memory window (MW) with 26.4% endurance degradation after 107 program/erase (P/E) cycles and 92.39% retention after 104 s. The accelerated charge trapping/detrapping dynamics enable superior short-term memory (STM) functionality. Remarkably, cryogenic operation at 77 K enhances the MW to 8 V while achieving exceptional stability with merely 0.4% degradation after 107 cycles and 99.02% retention at 104 seconds. The enhanced characteristics make it ideal for long-term memory (LTM) applications. Moreover, a reservoir computing (RC) network is proposed based on the cross-temperature FeFETs. By integrating the STM properties at 300 K and the LTM benefits at 77 K, the proposed RC network achieves a classification accuracy of 76.73% on the CIFAR-10 image recognition task. This surpasses the standalone results of 41.65% and 23.69% of 300 K and 77 K conditions, respectively. The findings highlight the potential to develop highly energy-efficient FeFET-based neuromorphic computing with varying temperature systems.
{"title":"Cross-Temperature FeFETs Enabling Long- and Short-Term Memory for Reservoir Computing Network","authors":"Bo Chen;Yifan Wu;Yuwei Qu;Anlin Liu;Yuzhe Hu;Pengpeng Sang;Jixuan Wu;Xuepeng Zhan;Jiezhi Chen","doi":"10.1109/JEDS.2025.3585619","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3585619","url":null,"abstract":"Hardware neural networks based on emerging nonvolatile memory are promising candidates to overcome the Von Neumann computing bottleneck. This study investigates the device characteristics and reliability of ferroelectric field-effect transistors (FeFETs) with a focus on their temperature-dependent performance. At 300 K, the FeFET demonstrates a 6.2 V memory window (MW) with 26.4% endurance degradation after 107 program/erase (P/E) cycles and 92.39% retention after 104 s. The accelerated charge trapping/detrapping dynamics enable superior short-term memory (STM) functionality. Remarkably, cryogenic operation at 77 K enhances the MW to 8 V while achieving exceptional stability with merely 0.4% degradation after 107 cycles and 99.02% retention at 104 seconds. The enhanced characteristics make it ideal for long-term memory (LTM) applications. Moreover, a reservoir computing (RC) network is proposed based on the cross-temperature FeFETs. By integrating the STM properties at 300 K and the LTM benefits at 77 K, the proposed RC network achieves a classification accuracy of 76.73% on the CIFAR-10 image recognition task. This surpasses the standalone results of 41.65% and 23.69% of 300 K and 77 K conditions, respectively. The findings highlight the potential to develop highly energy-efficient FeFET-based neuromorphic computing with varying temperature systems.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"582-586"},"PeriodicalIF":2.0,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11067954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144671149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-01DOI: 10.1109/JEDS.2025.3584809
Neng-Da Li;Yueh-Chin Lin;Kai-Wen Chen;Heng-Tung Hsu;Yi-Fan Tsao;Edward Yi Chang
In this study, AlGaN/GaN high-electron-mobility-transistor (HEMTs) with a small gate length were fabricated using a stepper. Additionally, a novel gate fabrication process was conducted to shrink the gate head, thus reducing the parasitic capacitance of the device to achieve high-power amplifier performance. The device performance in the research demonstrated a steady-state current density (Idss) of 975 mA/mm and a maximum transconductance (gm) of 369 mS/mm at a 20 V bias. Moreover, the cut-off frequency (fT) reached 50.6 GHz, and the maximum oscillation frequency (fmax) achieved 161 GHz as measured by S-parameter measurement. In the load-pull system, the frequency operation is under 28 GHz. For the $2times 50~mu $ m device at a drain bias of 20 V, it exhibits a maximum output power density (Pout) of 2.83 W/mm with a maximum 24.97% power-added efficiency (PAE). Additionally, for the $8times 50~mu $ m device at a drain bias of 32V, it achieves a $mathrm { P_{out}}$ of 1.27 W (3.18 W/mm). This work demonstrates that the novel gate fabrication process of shrinking gate head by using $mathrm { SiN_{x}}$ shield achieves high-frequency and high-output power characteristics for Ka-band application.
{"title":"Novel Gate Fabrication Process Enhancing High-Frequency Operation in AlGaN/GaN HEMTs for Ka-Band Applications","authors":"Neng-Da Li;Yueh-Chin Lin;Kai-Wen Chen;Heng-Tung Hsu;Yi-Fan Tsao;Edward Yi Chang","doi":"10.1109/JEDS.2025.3584809","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3584809","url":null,"abstract":"In this study, AlGaN/GaN high-electron-mobility-transistor (HEMTs) with a small gate length were fabricated using a stepper. Additionally, a novel gate fabrication process was conducted to shrink the gate head, thus reducing the parasitic capacitance of the device to achieve high-power amplifier performance. The device performance in the research demonstrated a steady-state current density (Idss) of 975 mA/mm and a maximum transconductance (gm) of 369 mS/mm at a 20 V bias. Moreover, the cut-off frequency (fT) reached 50.6 GHz, and the maximum oscillation frequency (fmax) achieved 161 GHz as measured by S-parameter measurement. In the load-pull system, the frequency operation is under 28 GHz. For the <inline-formula> <tex-math>$2times 50~mu $ </tex-math></inline-formula>m device at a drain bias of 20 V, it exhibits a maximum output power density (Pout) of 2.83 W/mm with a maximum 24.97% power-added efficiency (PAE). Additionally, for the <inline-formula> <tex-math>$8times 50~mu $ </tex-math></inline-formula>m device at a drain bias of 32V, it achieves a <inline-formula> <tex-math>$mathrm { P_{out}}$ </tex-math></inline-formula> of 1.27 W (3.18 W/mm). This work demonstrates that the novel gate fabrication process of shrinking gate head by using <inline-formula> <tex-math>$mathrm { SiN_{x}}$ </tex-math></inline-formula> shield achieves high-frequency and high-output power characteristics for Ka-band application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"593-598"},"PeriodicalIF":2.4,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11062583","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Avalanche photodiodes (APDs) based on InGaAs/InP are pivotal for applications in low-light detection, yet their performance is often hindered by edge breakdown and high dark currents. This study systematically optimizes guard ring structures to address these challenges, focusing on attached guard rings (AGRs) and floating guard rings (FGRs) through a synergistic approach combining simulation-guided design, fabrication, and experimental validation. We analyze the impact of Zn diffusion depth, AGR/FGR geometries, and electric field distribution on device performance. Experimental results demonstrate that optimized AGR structures reduce dark currents by 70% and enhance quantum efficiency (QE) by 43%, while FGR structures achieve an order-of-magnitude reduction in dark current and a 90% QE improvement compared to non-guarded devices. The breakdown voltage increases by 2.5 V (AGR) and 4 V (FGR), leading to enhanced gain. These advancements highlight the critical role of guard ring optimization in effectively mitigating edge breakdown, offering a pathway to high-sensitivity InGaAs/InP APDs for photon detection technologies.
基于InGaAs/InP的雪崩光电二极管（apd）在低光检测应用中至关重要，但其性能经常受到边缘击穿和高暗电流的阻碍。本研究系统地优化了保护环结构以应对这些挑战，重点研究了附着保护环（agr）和浮动保护环（fgr），通过结合仿真指导设计、制造和实验验证的协同方法。我们分析了锌扩散深度、AGR/FGR几何形状和电场分布对器件性能的影响。实验结果表明，优化后的AGR结构减少了70%的暗电流，提高了43%的量子效率（QE），而FGR结构与非保护器件相比，暗电流减少了一个数量级，量子效率提高了90%。击穿电压增加2.5 V （AGR）和4 V (FGR)，导致增益增强。这些进展突出了保护环优化在有效减轻边缘击穿方面的关键作用，为光子探测技术的高灵敏度InGaAs/InP apd提供了一条途径。
{"title":"Optimization of Guard Ring Structures for Superior Dark Current Reduction and Improved Quantum Efficiency in InGaAs/InP APDs","authors":"Zefang Xu;Yu Chang;Kai Qiao;Liyu Liu;Linmeng Xu;Mengyan Fang;Chang Su;Fei Yin;Jieying Wang;Tianye Liu;Ming Li;Dian Wang;Lizhi Sheng;Xing Wang","doi":"10.1109/JEDS.2025.3583669","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3583669","url":null,"abstract":"Avalanche photodiodes (APDs) based on InGaAs/InP are pivotal for applications in low-light detection, yet their performance is often hindered by edge breakdown and high dark currents. This study systematically optimizes guard ring structures to address these challenges, focusing on attached guard rings (AGRs) and floating guard rings (FGRs) through a synergistic approach combining simulation-guided design, fabrication, and experimental validation. We analyze the impact of Zn diffusion depth, AGR/FGR geometries, and electric field distribution on device performance. Experimental results demonstrate that optimized AGR structures reduce dark currents by 70% and enhance quantum efficiency (QE) by 43%, while FGR structures achieve an order-of-magnitude reduction in dark current and a 90% QE improvement compared to non-guarded devices. The breakdown voltage increases by 2.5 V (AGR) and 4 V (FGR), leading to enhanced gain. These advancements highlight the critical role of guard ring optimization in effectively mitigating edge breakdown, offering a pathway to high-sensitivity InGaAs/InP APDs for photon detection technologies.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"551-557"},"PeriodicalIF":2.0,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11053970","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144598038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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