Pub Date : 2024-06-17DOI: 10.1109/JEDS.2024.3405552
{"title":"Special Issue on Intelligent Sensor Systems for the IEEE Journal of Electron Devices","authors":"","doi":"10.1109/JEDS.2024.3405552","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3405552","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10558801","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141334027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-17DOI: 10.1109/JEDS.2024.3412339
{"title":"Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers","authors":"","doi":"10.1109/JEDS.2024.3412339","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3412339","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10558802","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141333957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-17DOI: 10.1109/JEDS.2024.3369770
{"title":"Call for Nominations Editor-in-Chief IEEE Transactions on Device and Materials Reliability","authors":"","doi":"10.1109/JEDS.2024.3369770","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3369770","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10558850","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141334003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, a partially isolated dual work function (PIDWF) gate In-Ga-Zn-O (IGZO) thin-film transistor (TFT) is proposed to reduce the off-state current (Ioff) obviously, which also provides a feasible integration method for stacking IGZO TFT on Si-based devices. It is found that compared with the general back gate IGZO TFT structure, the Ioff of the proposed IGZO TFT reduces from $2.57times 10{^{-}14 }$ A/ $mu $ m to $7.57times 10{^{-}16 }$ A/ $mu $ m, achieving two orders of magnitude improvement. This breakthrough has the potential to increase the retention time of DRAM applications by nearly 100 times. Moreover, the pronounced novel structure has mitigated parasitic capacitance, thereby leading to a notable 47.7% reduction in write latency within dynamic-random-access-memory (DRAM) circuits. The relevant operation mechanism is carefully demonstrated and verified by the simulation of the electric field and potential barrier results by technical computer-aided design (TCAD). Furthermore, the impacts of the dual gate work function level, the length, and the type of isolation dielectric between dual work function gates are systematically investigated. The results show that the off-state leakage is further reduced by increasing the difference of the work function levels between in dual gates, the dielectric length (LD) and using the isolation layer with a lower dielectric constant. The PIDWF gate IGZO TFT exhibits scalability and is capable of achieving an 84.6% reduction in leakage current even with ultra-short channel lengths, which offers a promising application for future 3D DRAM applications with little extra cost.
本文提出了一种部分隔离双功函数（PIDWF）栅In-Ga-Zn-O（IGZO）薄膜晶体管（TFT），以明显降低关态电流（Ioff），这也为在硅基器件上堆叠IGZO TFT提供了一种可行的集成方法。研究发现，与一般的背栅IGZO TFT结构相比，所提出的IGZO TFT的Ioff从2.57倍10{^{-}14 }$ A/ $mu $ m降低到7.57倍10{^{-}16 }$ A/ $mu $ m，实现了两个数量级的提升。这一突破有望将 DRAM 应用的保留时间延长近 100 倍。此外，这种明显的新型结构还减轻了寄生电容，从而使动态随机存取存储器（DRAM）电路的写入延迟显著减少了 47.7%。通过技术计算机辅助设计（TCAD）对电场和势垒结果的模拟，对相关的运行机制进行了仔细的论证和验证。此外，还系统地研究了双栅极工作函数水平、长度以及双工作函数栅极之间隔离电介质类型的影响。结果表明，通过增大双栅极之间的功函数级差、介质长度（LD）和使用介电常数较低的隔离层，可以进一步降低离态漏电。PIDWF 栅极 IGZO TFT 具有可扩展性，即使在超短沟道长度的情况下也能将漏电流降低 84.6%，这为未来的 3D DRAM 应用提供了前景广阔的应用前景，而且只需很少的额外成本。
{"title":"Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMs","authors":"Yunjiao Bao;Gangping Yan;Lei Cao;Chuqiao Niu;Qingkun Li;Guanqiao Sang;Lianlian Li;Yanzhao Wei;Xuexiang Zhang;Jie Luo;Yanyu Yang;Gaobo Xu;Huaxiang Yin","doi":"10.1109/JEDS.2024.3414469","DOIUrl":"10.1109/JEDS.2024.3414469","url":null,"abstract":"In this article, a partially isolated dual work function (PIDWF) gate In-Ga-Zn-O (IGZO) thin-film transistor (TFT) is proposed to reduce the off-state current (Ioff) obviously, which also provides a feasible integration method for stacking IGZO TFT on Si-based devices. It is found that compared with the general back gate IGZO TFT structure, the Ioff of the proposed IGZO TFT reduces from \u0000<inline-formula> <tex-math>$2.57times 10{^{-}14 }$ </tex-math></inline-formula>\u0000 A/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m to \u0000<inline-formula> <tex-math>$7.57times 10{^{-}16 }$ </tex-math></inline-formula>\u0000 A/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m, achieving two orders of magnitude improvement. This breakthrough has the potential to increase the retention time of DRAM applications by nearly 100 times. Moreover, the pronounced novel structure has mitigated parasitic capacitance, thereby leading to a notable 47.7% reduction in write latency within dynamic-random-access-memory (DRAM) circuits. The relevant operation mechanism is carefully demonstrated and verified by the simulation of the electric field and potential barrier results by technical computer-aided design (TCAD). Furthermore, the impacts of the dual gate work function level, the length, and the type of isolation dielectric between dual work function gates are systematically investigated. The results show that the off-state leakage is further reduced by increasing the difference of the work function levels between in dual gates, the dielectric length (LD) and using the isolation layer with a lower dielectric constant. The PIDWF gate IGZO TFT exhibits scalability and is capable of achieving an 84.6% reduction in leakage current even with ultra-short channel lengths, which offers a promising application for future 3D DRAM applications with little extra cost.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10557586","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study investigates the DC and RF performance of RF GaN High Electron Mobility Transistors (HEMTs) subjected to surface pretreatments by N 2 and N 2 O plasma. The filling of nitrogen vacancies or the passivation effect introduced by the thin GaON layer result in enhanced DC characteristics and RF performance for devices treated with nitrogen-based plasma. Compared to the untreated device, the device treated with N 2 plasma exhibited a significant improvement in performance, i.e., the saturated current increased by approximately 16%, the characteristic frequency (f T ) had an increase of 27.6 GHz, the maximum oscillating frequency (f max ) increased by 60.4 GHz. Furthermore, the breakdown voltage had a 10.7% increase, and the dynamic/static on-resistance ratio decreased from 1.34 to 1.18. These results highlight the potential of nitrogen-based plasma treatments in improving the performance of RF GaN HEMTs.
{"title":"Investigation of Nitrogen-Based Plasma Passivation on GaN RF HEMTs Using Various Precursors","authors":"Qiaoyu Hu;Wei-Chih Cheng;Xiguang Chen;Chenkai Deng;Lina Liao;Wenmao Li;Yang Jiang;Jiaqi He;Yi Zhang;Chuying Tang;Peiran Wang;Kangyao Wen;Fangzhou Du;Yifan Cui;Mujun Li;Wenyue Yu;Robert Sokolovskij;Nick Tao;Qing Wang;Hongyu Yu","doi":"10.1109/JEDS.2024.3412186","DOIUrl":"10.1109/JEDS.2024.3412186","url":null,"abstract":"This study investigates the DC and RF performance of RF GaN High Electron Mobility Transistors (HEMTs) subjected to surface pretreatments by N\u0000<sub>2</sub>\u0000 and N\u0000<sub>2</sub>\u0000O plasma. The filling of nitrogen vacancies or the passivation effect introduced by the thin GaON layer result in enhanced DC characteristics and RF performance for devices treated with nitrogen-based plasma. Compared to the untreated device, the device treated with N\u0000<sub>2</sub>\u0000 plasma exhibited a significant improvement in performance, i.e., the saturated current increased by approximately 16%, the characteristic frequency (f\u0000<sub>T</sub>\u0000) had an increase of 27.6 GHz, the maximum oscillating frequency (f\u0000<sub>max</sub>\u0000) increased by 60.4 GHz. Furthermore, the breakdown voltage had a 10.7% increase, and the dynamic/static on-resistance ratio decreased from 1.34 to 1.18. These results highlight the potential of nitrogen-based plasma treatments in improving the performance of RF GaN HEMTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10552704","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-05DOI: 10.1109/JEDS.2024.3409579
Rhaycen R. Prates;Sylvain Barraud;Mikael Cassé;Maud Vinet;Olivier Faynot;Marcelo A. Pavanello
This work aims to perform a comprehensive comparison of the electrical properties of junctionless and inversion-mode nanowires MOSFETS, fabricated with similar gate stack and state-of-art process, in the temperature range from 300 K to 580 K. The comparative analysis is performed through the main electrical parameters of the devices, such as the threshold voltage, subthreshold current and slope, DIBL, conduction current, mobility, and maximum transconductance extracted from experimental data. Devices with different fin widths are compared. It is demonstrated that the inversion-mode nanowire transistors present higher performance with three times higher maximum transconductance and conduction current and twice higher low field mobility than the junctionless’ with a fin width of 10 nm at a fixed temperature. On the other hand, the junctionless nanowire transistors presented higher thermal stability of their electrical parameters with a 75% lower variation of maximum transconductance with temperature, 77% lower maximum transconductance variation with temperature, and 22% lower temperature coefficient of mobility.
本研究旨在全面比较无结和反转模式纳米线 MOSFETS 在 300 K 至 580 K 温度范围内的电气特性，这两种器件均采用类似的栅极堆栈和最先进的工艺制造而成。对不同鳍片宽度的器件进行了比较。结果表明，在固定温度下，反转模式纳米线晶体管具有更高的性能，其最大跨导和传导电流比翅片宽度为 10 纳米的无结晶体管高出三倍，低场迁移率高出两倍。另一方面，无结纳米线晶体管的电气参数具有更高的热稳定性，最大跨导随温度的变化降低了 75%，最大跨导随温度的变化降低了 77%，迁移率的温度系数降低了 22%。
{"title":"Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures","authors":"Rhaycen R. Prates;Sylvain Barraud;Mikael Cassé;Maud Vinet;Olivier Faynot;Marcelo A. Pavanello","doi":"10.1109/JEDS.2024.3409579","DOIUrl":"10.1109/JEDS.2024.3409579","url":null,"abstract":"This work aims to perform a comprehensive comparison of the electrical properties of junctionless and inversion-mode nanowires MOSFETS, fabricated with similar gate stack and state-of-art process, in the temperature range from 300 K to 580 K. The comparative analysis is performed through the main electrical parameters of the devices, such as the threshold voltage, subthreshold current and slope, DIBL, conduction current, mobility, and maximum transconductance extracted from experimental data. Devices with different fin widths are compared. It is demonstrated that the inversion-mode nanowire transistors present higher performance with three times higher maximum transconductance and conduction current and twice higher low field mobility than the junctionless’ with a fin width of 10 nm at a fixed temperature. On the other hand, the junctionless nanowire transistors presented higher thermal stability of their electrical parameters with a 75% lower variation of maximum transconductance with temperature, 77% lower maximum transconductance variation with temperature, and 22% lower temperature coefficient of mobility.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10549873","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-04DOI: 10.1109/JEDS.2024.3409572
Chanwoo Park;Hyunbo Cho;Jungwoo Lee
Neural Compact Models (NCMs) have emerged as a crucial tool to meet the stringent demands of Design-Technology Co-Optimization (DTCO) and to overcome the complexities and prolonged development cycles encountered in traditional compact model creation. Despite their efficiency in simulating electronic devices, a significant barrier to the widespread adoption of NCMs in the industry remains: the lack of interpretability. In the semiconductor sector, where inaccuracies or failures can lead to considerable financial consequences, it is critical to ensure that the model’s predictions are both understandable and reliable. This study aims to enhance the interpretability of NCMs used for I-V and C-V characterizations by clarifying the physical significance of latent vectors. A regularization technique is employed to disentangle features within the latent space, and interpolation is used to visualize and elucidate each dimension’s physical impact. Our approach, which offers interpretable insights into the model’s functionality, seeks to encourage broader implementation of NCMs in the industry, thus accelerating advancements in DTCO.
{"title":"Enhancing Interpretability of Neural Compact Models: Toward Reliable Device Modeling","authors":"Chanwoo Park;Hyunbo Cho;Jungwoo Lee","doi":"10.1109/JEDS.2024.3409572","DOIUrl":"10.1109/JEDS.2024.3409572","url":null,"abstract":"Neural Compact Models (NCMs) have emerged as a crucial tool to meet the stringent demands of Design-Technology Co-Optimization (DTCO) and to overcome the complexities and prolonged development cycles encountered in traditional compact model creation. Despite their efficiency in simulating electronic devices, a significant barrier to the widespread adoption of NCMs in the industry remains: the lack of interpretability. In the semiconductor sector, where inaccuracies or failures can lead to considerable financial consequences, it is critical to ensure that the model’s predictions are both understandable and reliable. This study aims to enhance the interpretability of NCMs used for I-V and C-V characterizations by clarifying the physical significance of latent vectors. A regularization technique is employed to disentangle features within the latent space, and interpolation is used to visualize and elucidate each dimension’s physical impact. Our approach, which offers interpretable insights into the model’s functionality, seeks to encourage broader implementation of NCMs in the industry, thus accelerating advancements in DTCO.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10547540","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-03DOI: 10.1109/JEDS.2024.3407098
Fan Li;Shiqiang Wu;Ang Li;Yuhao Zhu;Miao Cui;Jiangmin Gu;Ping Zhang;Yinchao Zhao;Huiqing Wen;Wen Liu
This study demonstrates the first work that achieves accurate modeling of Hydrogen plasmatreated (H-treated) p-GaN gate devices with the ASM-GaN model, facilitating simulations for applications in monolithic integrated circuit (IC) design. The workflow for ASM-GaN model parameter extraction and optimization using IC-CAP is proposed. The I-V characteristics of both Enhancement / Depletion (E/D) mode devices are modeled and fitted. The impact of device capacitance on the dynamic properties of monolithic IC is investigated through the ASM model. The results demonstrate that Cds, Cgd, and Cgs have different effects on the monolithic logic circuit performances. The high-level fitting of experimental data and circuit simulation of Inverter, NAND, and Comparator circuits proves the credibility of the modeling workflow and device capacitance modulation. This work provides a method to speed up the GaN monolithic IC design by accurate modeling with fast parameter extraction workflow regardless of the fabrication process. The reliable prediction of the circuit’s dynamic performance will lay the foundation for designing and scaling up the GaN monolithic IC application.
{"title":"Investigation on the Dynamic Characteristics of Hydrogen Plasma Treated p-GaN HEMTs Circuit Using ASM-GaN Model","authors":"Fan Li;Shiqiang Wu;Ang Li;Yuhao Zhu;Miao Cui;Jiangmin Gu;Ping Zhang;Yinchao Zhao;Huiqing Wen;Wen Liu","doi":"10.1109/JEDS.2024.3407098","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3407098","url":null,"abstract":"This study demonstrates the first work that achieves accurate modeling of Hydrogen plasmatreated (H-treated) p-GaN gate devices with the ASM-GaN model, facilitating simulations for applications in monolithic integrated circuit (IC) design. The workflow for ASM-GaN model parameter extraction and optimization using IC-CAP is proposed. The I-V characteristics of both Enhancement / Depletion (E/D) mode devices are modeled and fitted. The impact of device capacitance on the dynamic properties of monolithic IC is investigated through the ASM model. The results demonstrate that Cds, Cgd, and Cgs have different effects on the monolithic logic circuit performances. The high-level fitting of experimental data and circuit simulation of Inverter, NAND, and Comparator circuits proves the credibility of the modeling workflow and device capacitance modulation. This work provides a method to speed up the GaN monolithic IC design by accurate modeling with fast parameter extraction workflow regardless of the fabrication process. The reliable prediction of the circuit’s dynamic performance will lay the foundation for designing and scaling up the GaN monolithic IC application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10543269","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-05-16DOI: 10.1109/jeds.2024.3401852
Antonio J. García-Loureiro, Natalia Seoane, Julian G. Fernández, Enrique Comesaña
{"title":"A General Toolkit for Advanced Semiconductor Transistors: From Simulation to Machine Learning","authors":"Antonio J. García-Loureiro, Natalia Seoane, Julian G. Fernández, Enrique Comesaña","doi":"10.1109/jeds.2024.3401852","DOIUrl":"https://doi.org/10.1109/jeds.2024.3401852","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141058923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-05-06DOI: 10.1109/jeds.2024.3397005
Anyi Zhu, Lei Jin, Jianquan Jia, Tianchun Ye, Ming Zeng, Zongliang Huo
{"title":"HCMS: A Hybrid Conductance Modulation Scheme Based on Cell-to-Cell Z-Interference for 3D NAND Neuromorphic Computing","authors":"Anyi Zhu, Lei Jin, Jianquan Jia, Tianchun Ye, Ming Zeng, Zongliang Huo","doi":"10.1109/jeds.2024.3397005","DOIUrl":"https://doi.org/10.1109/jeds.2024.3397005","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140882740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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