Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159772
Nakisa Shams, A. Abbasi, F. Nabki
This paper presents a differential wideband low noise amplifier (LNA) targeting 5G applications in 130 nm TSMC CMOS technology. The proposed LNA is based on the capacitive cross-coupled common-gate (CCC-CG) push-pull architecture. The LNA utilizes inductors for wideband input matching that resonate with the input parasitic capacitors. The CCC-CG structure along with a current-reuse PMOS and NMOS technique enhances transconductance, reducing noise figure (NF) and increasing voltage gain. Post-layout simulation results show that the differential LNA achieves a gain of 21 ±1.5 dB, NF of less than 4 dB and IIP3 of higher than −2.5 dBm over the bandwidth of 3.5 to 7 GHz. The LNA consumes 2.4 mA from 1 V supply, and occupies an active area of 0.24 mm2.
{"title":"A 3.5 to 7 GHz Wideband Differential LNA with gm Enhancement for 5G Applications","authors":"Nakisa Shams, A. Abbasi, F. Nabki","doi":"10.1109/newcas49341.2020.9159772","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159772","url":null,"abstract":"This paper presents a differential wideband low noise amplifier (LNA) targeting 5G applications in 130 nm TSMC CMOS technology. The proposed LNA is based on the capacitive cross-coupled common-gate (CCC-CG) push-pull architecture. The LNA utilizes inductors for wideband input matching that resonate with the input parasitic capacitors. The CCC-CG structure along with a current-reuse PMOS and NMOS technique enhances transconductance, reducing noise figure (NF) and increasing voltage gain. Post-layout simulation results show that the differential LNA achieves a gain of 21 ±1.5 dB, NF of less than 4 dB and IIP3 of higher than −2.5 dBm over the bandwidth of 3.5 to 7 GHz. The LNA consumes 2.4 mA from 1 V supply, and occupies an active area of 0.24 mm2.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121087959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159785
A. Abbasi, Nakisa Shams, Amin Pourvali Kakhki, F. Nabki
A low-power wideband receiver front-end is proposed for the narrow-band internet of things (NB-IoT) wireless standard to cover frequency bands from 0.6GHz to 1.4GHz. The front-end receiver integrates a programmable gain quadrature RF-to-baseband (BB) current-reuse receiver (CRR) architecture using conventional double-balanced passive-mixer with 25% duty-cycle local oscillator (LO) followed by a passive polyphase filter (PPF), high pass filter (HPF), programmable gain $g_{m}-C$ filter and RC-low pass filter (LPF). Low-power consumption is achieved by employing RF-to-BB CRR that shares a single supply with a wideband transconductor and a transimpedance amplifier (TIA). Moreover, power consumption is reduced by employing a single path PPF and $g_{m}-C$ filter to attenuate the blocker frequency at 7.5MHz above the intermediate frequency (IF). The proposed architecture is post-layout simulated in TSMC 130-nm CMOS technology. It achieves a voltage gain of 59.4dB, a noise figure (NF) of 4.9dB and a out-of-band IIP3 of −34.2dBm at 900MHz while consuming 1.8mW from a 1.2V supply at the maximum gain setting. In addition, the input matching covers several NB-IoT frequency-bands.
{"title":"A Low-Power Wideband Receiver Front-End for NB-IoT Applications","authors":"A. Abbasi, Nakisa Shams, Amin Pourvali Kakhki, F. Nabki","doi":"10.1109/newcas49341.2020.9159785","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159785","url":null,"abstract":"A low-power wideband receiver front-end is proposed for the narrow-band internet of things (NB-IoT) wireless standard to cover frequency bands from 0.6GHz to 1.4GHz. The front-end receiver integrates a programmable gain quadrature RF-to-baseband (BB) current-reuse receiver (CRR) architecture using conventional double-balanced passive-mixer with 25% duty-cycle local oscillator (LO) followed by a passive polyphase filter (PPF), high pass filter (HPF), programmable gain $g_{m}-C$ filter and RC-low pass filter (LPF). Low-power consumption is achieved by employing RF-to-BB CRR that shares a single supply with a wideband transconductor and a transimpedance amplifier (TIA). Moreover, power consumption is reduced by employing a single path PPF and $g_{m}-C$ filter to attenuate the blocker frequency at 7.5MHz above the intermediate frequency (IF). The proposed architecture is post-layout simulated in TSMC 130-nm CMOS technology. It achieves a voltage gain of 59.4dB, a noise figure (NF) of 4.9dB and a out-of-band IIP3 of −34.2dBm at 900MHz while consuming 1.8mW from a 1.2V supply at the maximum gain setting. In addition, the input matching covers several NB-IoT frequency-bands.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129835138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159815
R. Bostani, J. Hasani, K. El-Sankary
In this paper, a new topology is proposed for a three-stage LC ring oscillator. First, it is shown that the conventional ring oscillator can be represented as a configuration of a star connection of inductors. Next, in the proposed topology, the star connection is replaced with a star-delta connection to increase the inductance value for a given oscillation frequency. This is desirable in millimeter-wave band frequencies, where the inductance value is very small and severely affected by parasitic and may entail limitations in foundry design kits. By using the delta connection of the inductors, a higher oscillation frequency is achieved for a given inductance. Analytic equations are presented to calculate the oscillation condition and frequency of oscillation in the proposed topology. Moreover, the proposed structure has a better phase noise performance at higher frequencies in comparison to conventional topology. The advantages of the proposed topology are examined by simulations using TSMC 0.18 um RF-CMOS technology. Simulations and analysis results show a 38.36% increase of oscillation frequency in the proposed topology compared to the conventional one with the same components and similar conditions.
本文提出了一种新的三级LC环形振荡器拓扑结构。首先，证明了传统的环形振荡器可以表示为电感星形连接的结构。接下来，在提出的拓扑结构中，星形连接被星形三角形连接取代，以增加给定振荡频率的电感值。这在毫米波频带频率中是理想的，在毫米波频带中，电感值非常小，并且受到寄生的严重影响，并且可能导致铸造设计套件的限制。通过使用电感的三角连接，对于给定的电感可以获得更高的振荡频率。给出了计算该拓扑结构振荡条件和振荡频率的解析方程。此外，与传统拓扑结构相比，该结构在更高频率下具有更好的相位噪声性能。采用台积电0.18 um RF-CMOS技术进行仿真，验证了所提出拓扑结构的优点。仿真和分析结果表明，在相同元件和相似条件下，该拓扑结构的振荡频率比传统拓扑结构提高了38.36%。
{"title":"Star-Delta Connection Three-Stage Millimeter Wave Band LC Ring Oscillator","authors":"R. Bostani, J. Hasani, K. El-Sankary","doi":"10.1109/newcas49341.2020.9159815","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159815","url":null,"abstract":"In this paper, a new topology is proposed for a three-stage LC ring oscillator. First, it is shown that the conventional ring oscillator can be represented as a configuration of a star connection of inductors. Next, in the proposed topology, the star connection is replaced with a star-delta connection to increase the inductance value for a given oscillation frequency. This is desirable in millimeter-wave band frequencies, where the inductance value is very small and severely affected by parasitic and may entail limitations in foundry design kits. By using the delta connection of the inductors, a higher oscillation frequency is achieved for a given inductance. Analytic equations are presented to calculate the oscillation condition and frequency of oscillation in the proposed topology. Moreover, the proposed structure has a better phase noise performance at higher frequencies in comparison to conventional topology. The advantages of the proposed topology are examined by simulations using TSMC 0.18 um RF-CMOS technology. Simulations and analysis results show a 38.36% increase of oscillation frequency in the proposed topology compared to the conventional one with the same components and similar conditions.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132520400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159761
K. Taya, N. Kuroki, Naoto Takeda, T. Hirose, M. Numa
Often, digital pictures are used as evidence in criminal investigations. Therefore, it is essential to check whether they have been tampered with or not. In this study, we propose a method for detecting the tampered region in a JPEG image by using a convolutional neural network (CNN). In the proposed method, DCT coefficients are input to the CNN. The output is a binary segmented image in which the tampered and non-tampered regions are represented using white and black pixels, respectively. In our experiment, 45 types of CNN models were created and compared with one another. The detection accuracy of the best model was 0.63 in terms of the F-measure, which is approximately 2.3 times that achieved using our preliminary method, which was based on a support vector machine.
{"title":"Detecting tampered regions in JPEG images via CNN","authors":"K. Taya, N. Kuroki, Naoto Takeda, T. Hirose, M. Numa","doi":"10.1109/newcas49341.2020.9159761","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159761","url":null,"abstract":"Often, digital pictures are used as evidence in criminal investigations. Therefore, it is essential to check whether they have been tampered with or not. In this study, we propose a method for detecting the tampered region in a JPEG image by using a convolutional neural network (CNN). In the proposed method, DCT coefficients are input to the CNN. The output is a binary segmented image in which the tampered and non-tampered regions are represented using white and black pixels, respectively. In our experiment, 45 types of CNN models were created and compared with one another. The detection accuracy of the best model was 0.63 in terms of the F-measure, which is approximately 2.3 times that achieved using our preliminary method, which was based on a support vector machine.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116569334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159766
Antonio Lopez-Angulo, A. Ginés, E. Peralías
This work introduces a digital technique to measure and correct the mismatch between capacitors in SAR ADCs with split capacitor-based DAC (CDAC), including the bridge capacitor impairments. The method takes advantage of redundancy for calibration with negligible impact on the analog section. It reuses some of the capacitors in the array to also compensate the comparison offset, preventing redundancy interval saturation during the error measurement phase. The effectiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit split-CDAC SAR ADC case study.
这项工作介绍了一种数字技术来测量和纠正SAR adc中基于分裂电容的DAC (CDAC)中电容之间的不匹配，包括桥式电容损伤。该方法利用冗余进行校准，对模拟部分的影响可以忽略不计。它重用阵列中的一些电容来补偿比较偏移，防止在误差测量阶段冗余间隔饱和。通过对一个12位分路cdac SAR ADC的实际行为仿真，验证了该方法的有效性。
{"title":"Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy","authors":"Antonio Lopez-Angulo, A. Ginés, E. Peralías","doi":"10.1109/newcas49341.2020.9159766","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159766","url":null,"abstract":"This work introduces a digital technique to measure and correct the mismatch between capacitors in SAR ADCs with split capacitor-based DAC (CDAC), including the bridge capacitor impairments. The method takes advantage of redundancy for calibration with negligible impact on the analog section. It reuses some of the capacitors in the array to also compensate the comparison offset, preventing redundancy interval saturation during the error measurement phase. The effectiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit split-CDAC SAR ADC case study.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116536682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159782
Ximing Fu, K. El-Sankary, Yadong Yin
This paper presents a new technique for minimizing spurs in charge-pump phase-locked loop (PLL) using pulse injection (PI) technique. The proposed background calibration uses pulse injection in parallel with the normal operation of the PLL during its unlocked phase to extract the charge pump current mismatch error. The mismatch extraction is implemented using an error integrator and a successive approximation register (SAR) controller configured in a negative feedback to perform background calibration during the normal operation of the PLL. A windowing clock is used to extract only the error caused by the injected pulses and maintain the control voltage dc level outside of the window. Upon completion of calibration, the injection pulses are stopped and the PLL continues its operation in the lock state with minimized spur. The proposed technique successfully achieves fast calibration without interrupting the normal operation of the PLL. The simulation results show good improvements of spur reduction stemmed from the charge-pump.
{"title":"A Pulse injection background calibration technique for charge pump PLLs","authors":"Ximing Fu, K. El-Sankary, Yadong Yin","doi":"10.1109/newcas49341.2020.9159782","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159782","url":null,"abstract":"This paper presents a new technique for minimizing spurs in charge-pump phase-locked loop (PLL) using pulse injection (PI) technique. The proposed background calibration uses pulse injection in parallel with the normal operation of the PLL during its unlocked phase to extract the charge pump current mismatch error. The mismatch extraction is implemented using an error integrator and a successive approximation register (SAR) controller configured in a negative feedback to perform background calibration during the normal operation of the PLL. A windowing clock is used to extract only the error caused by the injected pulses and maintain the control voltage dc level outside of the window. Upon completion of calibration, the injection pulses are stopped and the PLL continues its operation in the lock state with minimized spur. The proposed technique successfully achieves fast calibration without interrupting the normal operation of the PLL. The simulation results show good improvements of spur reduction stemmed from the charge-pump.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123857610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159797
Alaa Safwat, A. Ismail
A new energy-efficient single-slope capacitance-to-digital interface circuit is proposed. The proposed interface circuit is a general purpose interface that can be adapted for multi-sensors IoT applications. This interface utilizes a new iterative charge sharing technique, which can be easily configures for different capacitive sensor ranges. The interface employs a switched capacitor circuit followed by a low-power dynamic comparator and a digital controller with a counter to generate the digital output, corresponding to the input capacitance of the sensor. The simplicity of the proposed capacitance-to-digital converter (CDC) architecture leads to an energy efficient interface. Detailed analysis of the proposed CDC architecture with emphasis on the linearity, conversion time, and noise are presented and verified by the simulation. The proposed CDC achieves a resolution of 8.4 bit and a figure-of-merit (FoM) of 1.56pJ for a capacitor sensor range of 8pF and a supply voltage of 1.2V in $0.18mu mathrm{m}$ CMOS technology node.
{"title":"A General Purpose Single-Slope MEMS Capacitive Sensors Interface Circuit For IoT Applications","authors":"Alaa Safwat, A. Ismail","doi":"10.1109/newcas49341.2020.9159797","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159797","url":null,"abstract":"A new energy-efficient single-slope capacitance-to-digital interface circuit is proposed. The proposed interface circuit is a general purpose interface that can be adapted for multi-sensors IoT applications. This interface utilizes a new iterative charge sharing technique, which can be easily configures for different capacitive sensor ranges. The interface employs a switched capacitor circuit followed by a low-power dynamic comparator and a digital controller with a counter to generate the digital output, corresponding to the input capacitance of the sensor. The simplicity of the proposed capacitance-to-digital converter (CDC) architecture leads to an energy efficient interface. Detailed analysis of the proposed CDC architecture with emphasis on the linearity, conversion time, and noise are presented and verified by the simulation. The proposed CDC achieves a resolution of 8.4 bit and a figure-of-merit (FoM) of 1.56pJ for a capacitor sensor range of 8pF and a supply voltage of 1.2V in $0.18mu mathrm{m}$ CMOS technology node.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124118824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159788
Gabriel P. Lachance, Shimwe Dominique Niyonambaza, Élodie Boisselier, M. Boukadoum, A. Miled
Neurotransmitter sensing is an importance component of biomedical research, and optoelectronic sensors play an important role in it. In particular, visible-light photo-spectrometers can be very useful for molecular detection and measurement. This work evaluates two optical design modes for the conception of a Czerny- Turner spectrometer. The system was designed at first using the non-sequential mode and then remade using the sequential mode. By comparing the same design made using both modes, the sequential mode had shown superior optimization potential.
{"title":"Critical Comparison of Sequential and Non-sequential Modes Usage for the Design of a Czerny-Turner Spectrometer","authors":"Gabriel P. Lachance, Shimwe Dominique Niyonambaza, Élodie Boisselier, M. Boukadoum, A. Miled","doi":"10.1109/newcas49341.2020.9159788","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159788","url":null,"abstract":"Neurotransmitter sensing is an importance component of biomedical research, and optoelectronic sensors play an important role in it. In particular, visible-light photo-spectrometers can be very useful for molecular detection and measurement. This work evaluates two optical design modes for the conception of a Czerny- Turner spectrometer. The system was designed at first using the non-sequential mode and then remade using the sequential mode. By comparing the same design made using both modes, the sequential mode had shown superior optimization potential.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131007145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159765
Adil Brik, L. Labrak, I. O’Connor, D. Saias
Predictive models based on Pareto fronts are key tools to understand and leverage tradeoffs in electronic circuit and system design. These predictive models are mostly used to accelerate design and enforce reuse [4]. The main drawback is that their generation requires a huge time which depends on both simulation and multi objective optimization time. This paper presents an efficient method to build predictive models with more speed and accuracy employing macro models simulation tool (Tactyle) and optimization software (MIDACO). Starting from system predictive model, we developed a Top-down flow which propagate the system constraints to lower level blocks, so we can design the sub-blocks in order to meet the system specifications. This approach is applied to a buck converter circuit
{"title":"Fast hierarchical system synthesis based on predictive models","authors":"Adil Brik, L. Labrak, I. O’Connor, D. Saias","doi":"10.1109/newcas49341.2020.9159765","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159765","url":null,"abstract":"Predictive models based on Pareto fronts are key tools to understand and leverage tradeoffs in electronic circuit and system design. These predictive models are mostly used to accelerate design and enforce reuse [4]. The main drawback is that their generation requires a huge time which depends on both simulation and multi objective optimization time. This paper presents an efficient method to build predictive models with more speed and accuracy employing macro models simulation tool (Tactyle) and optimization software (MIDACO). Starting from system predictive model, we developed a Top-down flow which propagate the system constraints to lower level blocks, so we can design the sub-blocks in order to meet the system specifications. This approach is applied to a buck converter circuit","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123281550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159807
H. Sadreazami, G. Mitsis
This work proposes a method for motor task recognition in brain computer interfaces (BCI). The proposed method is realized by EEG signals classification using time-dependent regularized common spatial patterns and deep residual networks. Unlike other existing methods, the proposed method relies on both the spectral and temporal features by preserving the temporal resolution of the spatially-filtered EEG signals. These features are projected onto an image representation and fed into a residual network for a hierarchical feature learning and classification. Experiments are carried out on benchmark datasets taken from BCI competitions to evaluate the performance of the proposed method and to compare it with other existing methods. The binary classification results of the proposed method demonstrate a superior performance in classification accuracy compared to other existing methods.
{"title":"Motor Task Learning in Brain Computer Interfaces using Time-Dependent Regularized Common Spatial Patterns and Residual Networks","authors":"H. Sadreazami, G. Mitsis","doi":"10.1109/newcas49341.2020.9159807","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159807","url":null,"abstract":"This work proposes a method for motor task recognition in brain computer interfaces (BCI). The proposed method is realized by EEG signals classification using time-dependent regularized common spatial patterns and deep residual networks. Unlike other existing methods, the proposed method relies on both the spectral and temporal features by preserving the temporal resolution of the spatially-filtered EEG signals. These features are projected onto an image representation and fed into a residual network for a hierarchical feature learning and classification. Experiments are carried out on benchmark datasets taken from BCI competitions to evaluate the performance of the proposed method and to compare it with other existing methods. The binary classification results of the proposed method demonstrate a superior performance in classification accuracy compared to other existing methods.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114273347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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