Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159781
Nam Ly, N. Aimaier, A. Alameh, Y. Blaquière, G. Cowan, N. Constantin
Intended to be the core design of a configurable and flexible high voltage power system for aerospace applications, the gate driver in this work is capable of driving a wide range of GaN devices of different sizes, in half-bridge configuration, with configurable driving strength and dead-time. These features eliminate the need for discrete gate resistors and allow for higher density designs, such as SiP integration. The on-the-fly reconfigurability enables local efficiency optimization and EMI reduction, which is essential in safety-critical applications. The proposed IC was fabricated using XFAB's 0.18 $mu mathrm{m}$ HV SOI CMOS process (xt018). Measurement results show that the chip can drive targeted GaN HEMTs from smallest to largest size at the desired turn-on and turn-off speeds, as fast as 1.46/1.18 ns of rise/fall-time. The measured dead-time is from 4.5 ns to 58 ns with an input voltage up to 86 V. The parameters can be reconfigured on-the-fly at a pulse width modulation frequency up to 20 MHz.
{"title":"A High Voltage Multi-Purpose On-the-fly Reconfigurable Half-Bridge Gate Driver for GaN HEMTs in 0.18-μm HV SOI CMOS Technology","authors":"Nam Ly, N. Aimaier, A. Alameh, Y. Blaquière, G. Cowan, N. Constantin","doi":"10.1109/newcas49341.2020.9159781","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159781","url":null,"abstract":"Intended to be the core design of a configurable and flexible high voltage power system for aerospace applications, the gate driver in this work is capable of driving a wide range of GaN devices of different sizes, in half-bridge configuration, with configurable driving strength and dead-time. These features eliminate the need for discrete gate resistors and allow for higher density designs, such as SiP integration. The on-the-fly reconfigurability enables local efficiency optimization and EMI reduction, which is essential in safety-critical applications. The proposed IC was fabricated using XFAB's 0.18 $mu mathrm{m}$ HV SOI CMOS process (xt018). Measurement results show that the chip can drive targeted GaN HEMTs from smallest to largest size at the desired turn-on and turn-off speeds, as fast as 1.46/1.18 ns of rise/fall-time. The measured dead-time is from 4.5 ns to 58 ns with an input voltage up to 86 V. The parameters can be reconfigured on-the-fly at a pulse width modulation frequency up to 20 MHz.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122333163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159839
R. Feitoza, M. Barragán, A. Ginés, S. Mir
This work presents a reduced-code strategy for the static linearity self-testing of $V_{cm}$ -based successive-approximation analog to digital converters (SAR ADCs). These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the application of these techniques for the $V_{cm}$ -based SAR ADC topology and present a practical BIST implementation based on an embedded incremental ADC. Electrical simulation results at transistor level are presented to validate the feasibility of the proposed on-chip reduced-code static linearity test.
{"title":"Static linearity BIST for $V_{cm}$-based switching SAR ADCs using a reduced-code measurement technique","authors":"R. Feitoza, M. Barragán, A. Ginés, S. Mir","doi":"10.1109/newcas49341.2020.9159839","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159839","url":null,"abstract":"This work presents a reduced-code strategy for the static linearity self-testing of $V_{cm}$ -based successive-approximation analog to digital converters (SAR ADCs). These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the application of these techniques for the $V_{cm}$ -based SAR ADC topology and present a practical BIST implementation based on an embedded incremental ADC. Electrical simulation results at transistor level are presented to validate the feasibility of the proposed on-chip reduced-code static linearity test.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122195826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159806
P. Afanasyev, A. Grebennikov, R. Farrell, J. Dooley
This work proposes a new approach for designing broadband class-E power amplifier (PA) with shunt filter. The approach is based on the double reactance compensation technique. Using this technique reactance variation of loaded Q-factor of a shunt filter and parameters of L-shaped matching circuit are adjusted to minimize variation of load impedance at the device drain across frequency range. Based on this concept, a 10W output power class-E PA was designed, optimized in circuit simulator Keysight ADS and fabricated using GaN HEMT transistor. The manufactured PA has compact output circuit and provides drain efficiency over 65% across frequency range 1.7 - 2.8 GHz and over 60% drain efficiency across frequency range 1.4 - 2.8 Hz. The measured output power variation is 2 dB.
{"title":"Broadband Operation of Class-E Power Amplifier with Shunt Filter","authors":"P. Afanasyev, A. Grebennikov, R. Farrell, J. Dooley","doi":"10.1109/NEWCAS49341.2020.9159806","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159806","url":null,"abstract":"This work proposes a new approach for designing broadband class-E power amplifier (PA) with shunt filter. The approach is based on the double reactance compensation technique. Using this technique reactance variation of loaded Q-factor of a shunt filter and parameters of L-shaped matching circuit are adjusted to minimize variation of load impedance at the device drain across frequency range. Based on this concept, a 10W output power class-E PA was designed, optimized in circuit simulator Keysight ADS and fabricated using GaN HEMT transistor. The manufactured PA has compact output circuit and provides drain efficiency over 65% across frequency range 1.7 - 2.8 GHz and over 60% drain efficiency across frequency range 1.4 - 2.8 Hz. The measured output power variation is 2 dB.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122227916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159789
Mostafa Amer, Mohamed Ali, Ahmed Abuelnasr, Ahmad Hassan, Morteza Nabavi, Y. Savaria, M. Sawan
This paper presents a power sensor interface (PSI) driving a wide range of load valves with coil resistance ranging from 5 $Omega$ to 62.5 $Omega$. It can sustain voltage surges up to 115 V. An integrated high-voltage (HV) dual-channel gate driver with 8.7 ns deadtime (DT) is implemented to efficiently drive e-GaN FETs in a synchronous DC-DC buck converter. In addition, an area-optimization technique of on-chip passive components is proposed to enable full-integration of voltage-mode controller with 87% reduction in area. The achieved peak efficiency is 98.7% @ 4.67 A load. The feedback bandwidth is ~100 kHz to maintain fast transient response at 1MHz switching frequency. The settling time is < 70 $mumathrm{s}$ and < 100 $mumathrm{s}$ at load changes of −5.2 A and 5.2 A respectively. Overshoot (OS) and undershoot (US) voltages are within 2% of nominal VOUT. The layout of the gate driver and feedback control is implemented in $0.35-mumathrm{m}$ HV CMOS process with active die area of 0.75 mm2.
本文提出了一种功率传感器接口(PSI)驱动各种负载阀，线圈电阻范围从5 $Omega$到62.5 $Omega$。它可以承受高达115 V的电压浪涌。为了有效驱动同步DC-DC降压变换器中的e-GaN场效应管，设计了一种具有8.7 ns死区时间(DT)的集成高压双通道栅极驱动器。此外，还提出了一种片上无源元件面积优化技术，以实现电压型控制器与87的完全集成% reduction in area. The achieved peak efficiency is 98.7% @ 4.67 A load. The feedback bandwidth is ~100 kHz to maintain fast transient response at 1MHz switching frequency. The settling time is < 70 $mumathrm{s}$ and < 100 $mumathrm{s}$ at load changes of −5.2 A and 5.2 A respectively. Overshoot (OS) and undershoot (US) voltages are within 2% of nominal VOUT. The layout of the gate driver and feedback control is implemented in $0.35-mumathrm{m}$ HV CMOS process with active die area of 0.75 mm2.
{"title":"Fully Integrated Dual-Channel Gate Driver and Area Efficient PID Compensator for Surge Tolerant Power Sensor Interface","authors":"Mostafa Amer, Mohamed Ali, Ahmed Abuelnasr, Ahmad Hassan, Morteza Nabavi, Y. Savaria, M. Sawan","doi":"10.1109/newcas49341.2020.9159789","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159789","url":null,"abstract":"This paper presents a power sensor interface (PSI) driving a wide range of load valves with coil resistance ranging from 5 $Omega$ to 62.5 $Omega$. It can sustain voltage surges up to 115 V. An integrated high-voltage (HV) dual-channel gate driver with 8.7 ns deadtime (DT) is implemented to efficiently drive e-GaN FETs in a synchronous DC-DC buck converter. In addition, an area-optimization technique of on-chip passive components is proposed to enable full-integration of voltage-mode controller with 87% reduction in area. The achieved peak efficiency is 98.7% @ 4.67 A load. The feedback bandwidth is ~100 kHz to maintain fast transient response at 1MHz switching frequency. The settling time is < 70 $mumathrm{s}$ and < 100 $mumathrm{s}$ at load changes of −5.2 A and 5.2 A respectively. Overshoot (OS) and undershoot (US) voltages are within 2% of nominal VOUT. The layout of the gate driver and feedback control is implemented in $0.35-mumathrm{m}$ HV CMOS process with active die area of 0.75 mm2.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124002139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159778
A. Pen, M. Roy, R. Lababidi, D. L. Jeune, A. Pérennec, J. Issler, K. Elis, A. Gay, J.-H. Corre
This paper presents and compares four different antenna topologies dedicated to Full-Duplex (FD) applications. The proposed architectures are able to operate simultaneously for transmitting TX and receiving RX radiating elements along broadside direction, contrarily to most of state of the art FD RF front-ends that also rely on destructive wave's concept to get Self-Interference Cancellation (SIC). The four prototypes make use of three SIC stages and the common first level is obtained using orthogonal linear polarization between TX and RX. Step-by-step improvements are introduced from one to another topology in order to increase the SIC level and to reduce both side lobe levels and antenna size. Simulated and experimental results are provided, compared and discussed at the center frequency of 2.4 GHz as a proof of concept. The isolation obtained between TX and RX paths is higher than 80 dB in simulation and 60 dB in measurement. These results pave the way to an implementation of a high gain Full-Duplex Ka-band antenna for Nanosat Intersatellite Link
{"title":"Broadside FD Antenna Topologies for Nanosat Intersatellite Link","authors":"A. Pen, M. Roy, R. Lababidi, D. L. Jeune, A. Pérennec, J. Issler, K. Elis, A. Gay, J.-H. Corre","doi":"10.1109/newcas49341.2020.9159778","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159778","url":null,"abstract":"This paper presents and compares four different antenna topologies dedicated to Full-Duplex (FD) applications. The proposed architectures are able to operate simultaneously for transmitting TX and receiving RX radiating elements along broadside direction, contrarily to most of state of the art FD RF front-ends that also rely on destructive wave's concept to get Self-Interference Cancellation (SIC). The four prototypes make use of three SIC stages and the common first level is obtained using orthogonal linear polarization between TX and RX. Step-by-step improvements are introduced from one to another topology in order to increase the SIC level and to reduce both side lobe levels and antenna size. Simulated and experimental results are provided, compared and discussed at the center frequency of 2.4 GHz as a proof of concept. The isolation obtained between TX and RX paths is higher than 80 dB in simulation and 60 dB in measurement. These results pave the way to an implementation of a high gain Full-Duplex Ka-band antenna for Nanosat Intersatellite Link","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132543778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159813
W. Khaddour, W. Uhring, F. Dadouche, V. Frick, M. Madec
This work presents a Fluorescence Life-Time (FLT) measurement system for real-time microfluidic droplet sorting in high throughput conditions. This system is implemented using a low cost System-on-Chip (SoC) Field-Programmable Gate Array (FPGA) platform, that combines a Cyclone V FPGA with a dual-core ARM Cortex-a9 Hard Processor System (HPS). A time-correlated single photon counting system is implemented in the FPGA part and the data are transferred to the SDRAM of the HPS part to be processed by a developed bare-metal C program to extract the FLT of each droplet passing through the detection spot. According to the droplet's measured FLT, an action could be taken to sort this droplet. The system automatically detects the droplets and extracts their FLT values at different simulated droplet flow rates; from a few droplets up to 1 thousand droplets per second. Thanks to the use of a maximum Likelihood-based algorithm, the standard deviation of the measured FLTs of simulated droplets of the same material is only 30% above the theoretical quantum photon shot noise limit.
本工作提出了一种在高通量条件下实时微流控液滴分选的荧光寿命(FLT)测量系统。该系统采用低成本的片上系统(SoC)现场可编程门阵列(FPGA)平台实现，该平台结合了Cyclone V FPGA和双核ARM Cortex-a9硬处理器系统(HPS)。FPGA部分实现了时间相关单光子计数系统，将数据传输到HPS部分的SDRAM中，由开发的裸机C程序进行处理，提取通过检测点的每个液滴的FLT。根据测量到的液滴的FLT，可以采取措施对液滴进行分类。系统自动检测液滴并提取不同模拟液滴流速下的FLT值;从几滴到每秒1000滴。由于使用了基于极大似然的算法，相同材料的模拟液滴的测量FLTs的标准偏差仅比理论量子光子散粒噪声极限高30%。
{"title":"Time-Resolved fluorescence measurement system for real-time high-throughput microfluidic droplet sorting","authors":"W. Khaddour, W. Uhring, F. Dadouche, V. Frick, M. Madec","doi":"10.1109/newcas49341.2020.9159813","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159813","url":null,"abstract":"This work presents a Fluorescence Life-Time (FLT) measurement system for real-time microfluidic droplet sorting in high throughput conditions. This system is implemented using a low cost System-on-Chip (SoC) Field-Programmable Gate Array (FPGA) platform, that combines a Cyclone V FPGA with a dual-core ARM Cortex-a9 Hard Processor System (HPS). A time-correlated single photon counting system is implemented in the FPGA part and the data are transferred to the SDRAM of the HPS part to be processed by a developed bare-metal C program to extract the FLT of each droplet passing through the detection spot. According to the droplet's measured FLT, an action could be taken to sort this droplet. The system automatically detects the droplets and extracts their FLT values at different simulated droplet flow rates; from a few droplets up to 1 thousand droplets per second. Thanks to the use of a maximum Likelihood-based algorithm, the standard deviation of the measured FLTs of simulated droplets of the same material is only 30% above the theoretical quantum photon shot noise limit.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131893872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159814
Mehdi Ahmadi, S. Vakili, J. Langlois
Convolutional Neural Networks (CNNs) are often the first choice for visual recognition systems due to their high, even superhuman, recognition accuracy. The memory configuration of CNN accelerators highly impacts their area and energy efficiency, and employing on-chip memories such as SRAMs is unavoidable. SRAMs can reduce the number of energy-hungry DRAM accesses by storing a large amount of data locally. In this paper, we propose a new on-chip memory configuration, for a certain class of CNN accelerators that divides the memories into two groups. The first group consists of shallow but wide SRAMs into which parallel computational units accumulate intermediate results. The second group includes narrow but deep SRAMs shared between adjacent computational units to store then transfer final results to the external DRAM without interrupting the computation process. Implementation results show that the proposed configuration reduces the area by 21 % and improves the energy efficiency by 18% compared to designs which use an ordinary ping-pong structure for SRAM-DRAM data transfer.
{"title":"Heterogeneous Distributed SRAM Configuration for Energy-Efficient Deep CNN Accelerators","authors":"Mehdi Ahmadi, S. Vakili, J. Langlois","doi":"10.1109/newcas49341.2020.9159814","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159814","url":null,"abstract":"Convolutional Neural Networks (CNNs) are often the first choice for visual recognition systems due to their high, even superhuman, recognition accuracy. The memory configuration of CNN accelerators highly impacts their area and energy efficiency, and employing on-chip memories such as SRAMs is unavoidable. SRAMs can reduce the number of energy-hungry DRAM accesses by storing a large amount of data locally. In this paper, we propose a new on-chip memory configuration, for a certain class of CNN accelerators that divides the memories into two groups. The first group consists of shallow but wide SRAMs into which parallel computational units accumulate intermediate results. The second group includes narrow but deep SRAMs shared between adjacent computational units to store then transfer final results to the external DRAM without interrupting the computation process. Implementation results show that the proposed configuration reduces the area by 21 % and improves the energy efficiency by 18% compared to designs which use an ordinary ping-pong structure for SRAM-DRAM data transfer.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159804
Yoann Seauve, M. Vigier, Thomas Pilloix, G. Sicard
Galium nitride (GaN) based Light-emitting diodes (LEDs) are known for their high brightness and high-speed commutation capability. Not surprisingly, GaN μLEDs are often used in LED based visible light communication (VLC) systems, due to the large modulation bandwidth they can offer. Although VLC emitters are commonly built with a single LED, using a matrix of μLED as the light source can have some advantages as higher linearity. In this paper, the design of a fast GaN μLED pixel driver dedicated to matrix emitters is discussed. This pixel driver can reach a 333 Mhz frame rate with its maximum bias current of 384 $mumathrm{A}$.
{"title":"Fast GaN μLED Pixel for Visible Light Communication Matrix Emitter","authors":"Yoann Seauve, M. Vigier, Thomas Pilloix, G. Sicard","doi":"10.1109/NEWCAS49341.2020.9159804","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159804","url":null,"abstract":"Galium nitride (GaN) based Light-emitting diodes (LEDs) are known for their high brightness and high-speed commutation capability. Not surprisingly, GaN μLEDs are often used in LED based visible light communication (VLC) systems, due to the large modulation bandwidth they can offer. Although VLC emitters are commonly built with a single LED, using a matrix of μLED as the light source can have some advantages as higher linearity. In this paper, the design of a fast GaN μLED pixel driver dedicated to matrix emitters is discussed. This pixel driver can reach a 333 Mhz frame rate with its maximum bias current of 384 $mumathrm{A}$.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122836024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159836
N. Gaoding, Jean-François Bousquet
This paper reports a fourth-order continuous-time (CT) delta-sigma modulator (DSM) that features a single biquad integrator, a passive integrator and an active integrator. A benefit is the low power consumption using only two opamps in comparison to 4 power-hungry opamps in the conventional fourth-order DSM. The proposed CT-DSM employs two Miller compensation opamps to satisfy the gain bandwidth (GBW) requirement and the loop gain requirement. In this design, the GBW is only 1.65 times higher than the sampling frequency and the open loop DC gain is much higher than the oversampling rate. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to complete the CT DSM including the feedback paths. The effective number of bits of the proposed CT-DSM is 14 bits with a peak SNR of 90.5 dB. The proposed design has a maximum bandwidth of 2 MHz with a power consumption less than 3 mW. Thus, it achieves an excellent figure of merit around 175 dB compared to existing state-of-the-art.
{"title":"A Hybrid 4th-Order 4-Bit Continuous-Time ΔΣ Modulator in 65-nm CMOS Technology","authors":"N. Gaoding, Jean-François Bousquet","doi":"10.1109/newcas49341.2020.9159836","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159836","url":null,"abstract":"This paper reports a fourth-order continuous-time (CT) delta-sigma modulator (DSM) that features a single biquad integrator, a passive integrator and an active integrator. A benefit is the low power consumption using only two opamps in comparison to 4 power-hungry opamps in the conventional fourth-order DSM. The proposed CT-DSM employs two Miller compensation opamps to satisfy the gain bandwidth (GBW) requirement and the loop gain requirement. In this design, the GBW is only 1.65 times higher than the sampling frequency and the open loop DC gain is much higher than the oversampling rate. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to complete the CT DSM including the feedback paths. The effective number of bits of the proposed CT-DSM is 14 bits with a peak SNR of 90.5 dB. The proposed design has a maximum bandwidth of 2 MHz with a power consumption less than 3 mW. Thus, it achieves an excellent figure of merit around 175 dB compared to existing state-of-the-art.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120845435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159838
Masaya Nishi, Kaori Matsumoto, N. Kuroki, M. Numa, Hikaru Sebe, R. Matsuzuka, O. Maida, D. Kanemoto, T. Hirose
A ring oscillator (ROSC) for extremely low-voltage thermoelectric energy generators is presented. The ROSC is composed of dedicated low-voltage stacked body bias inverters (SBBIs) that are based on the conventional self-bias inverter (SBI) and stacked inverter (SI). The proposed SBBI employs the advantages of both SBI and SI to oscillate at extremely low supply voltage $(V_{mathrm{D}mathrm{D}})$. The voltage gain $vert A_{mathrm{I}mathrm{N}mathrm{V}}vert$ of our proposed SBBI is improved and enhanced by controlling main inverter's supply $(V_{mathrm{D}mathrm{D}}$ and Gnd) and body-bias voltages, by using stacked and feedback inverters. Simulated results using a standard 0.18 $mu mathrm{m}$ CMOS process with deep N-well option showed that our proposed ROSC could oscillate at extremely low $V_{mathrm{D}mathrm{D}}$ of 34 mV and generate a clock pulse with a 88% voltage swing from an input $V_{mathrm{D}mathrm{D}}$ of 50 mV.
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