Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159771
Lucas F. S. Cambuim, Severino J. B. Júnior, Edna Barros
The CPU-FPGA heterogeneous architectures became an attractive option for developing hardware accelerators to process computer vision algorithms. In this paper, we improve the support for streaming processing on the Intel HARPv2 platform by proposing strategies such as data ordering, double buffer, and management of multiple memory addresses. We demonstrate the feasibility of this new strategy by a case study with a hardware implementation of the Semi-Global Matching (SGM) algorithm for stereo vision. With these strategies, we can process depth images with a resolution of 1920×1080 pixels achieving a processing rate of about 48 FPS. The processing performance overcomes the state-of-art CPU-FPGA heterogeneous architectures results for processing of the promissing SGM technique.
{"title":"A Strategy to Support Streaming Communication using the Intel HARPv2 Platform: A Case Study in Stereo Vision Application","authors":"Lucas F. S. Cambuim, Severino J. B. Júnior, Edna Barros","doi":"10.1109/newcas49341.2020.9159771","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159771","url":null,"abstract":"The CPU-FPGA heterogeneous architectures became an attractive option for developing hardware accelerators to process computer vision algorithms. In this paper, we improve the support for streaming processing on the Intel HARPv2 platform by proposing strategies such as data ordering, double buffer, and management of multiple memory addresses. We demonstrate the feasibility of this new strategy by a case study with a hardware implementation of the Semi-Global Matching (SGM) algorithm for stereo vision. With these strategies, we can process depth images with a resolution of 1920×1080 pixels achieving a processing rate of about 48 FPS. The processing performance overcomes the state-of-art CPU-FPGA heterogeneous architectures results for processing of the promissing SGM technique.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129957623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159846
Markus Stadelmayer, Tim Schumacher, Thomas Faseth, H. Pretl
A wide-frequency-range low-power synthesizer based on an eight-stage differential ring oscillator (RO) regulated by a phase locked loop (PLL) is introduced. It is specially designed to be used in edge-combining transmitters and fabricated in a 180nm 1P6M CMOS process. It provides 16 symmetrical phase-shifted outputs for up to 8-times frequency-multiplication using an external edge-combiner. The oscillator is implemented as current-starved RO. It includes a biasing network with threshold regulation for close to 50% duty cycle and equal time delay in all RO stages. The lower corner-frequency is 5 bit adjustable (50MHz to 300 MHz) and the oscillator offers an additional 5 bit trimmable tuning range (20.3MHz to 97.2 MHz). The structure is optimized to operate at 216MHz and shows a phase noise of −96 dBc/Hz at 1MHz offset as well as −76 dBc/Hz in-band phase noise (with locked PLL below 100 kHz offset). With its low power demand of 1.3mW, the frequency synthesizer is suited to be used in low-power transmitters.
{"title":"A 1.2-V 180-nm CMOS Low-Power Multi-Band Ring Oscillator based Frequency Synthesizer for Edge-Combining Transmitters","authors":"Markus Stadelmayer, Tim Schumacher, Thomas Faseth, H. Pretl","doi":"10.1109/newcas49341.2020.9159846","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159846","url":null,"abstract":"A wide-frequency-range low-power synthesizer based on an eight-stage differential ring oscillator (RO) regulated by a phase locked loop (PLL) is introduced. It is specially designed to be used in edge-combining transmitters and fabricated in a 180nm 1P6M CMOS process. It provides 16 symmetrical phase-shifted outputs for up to 8-times frequency-multiplication using an external edge-combiner. The oscillator is implemented as current-starved RO. It includes a biasing network with threshold regulation for close to 50% duty cycle and equal time delay in all RO stages. The lower corner-frequency is 5 bit adjustable (50MHz to 300 MHz) and the oscillator offers an additional 5 bit trimmable tuning range (20.3MHz to 97.2 MHz). The structure is optimized to operate at 216MHz and shows a phase noise of −96 dBc/Hz at 1MHz offset as well as −76 dBc/Hz in-band phase noise (with locked PLL below 100 kHz offset). With its low power demand of 1.3mW, the frequency synthesizer is suited to be used in low-power transmitters.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127626888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159799
S. Bourdel, Ekta Sharma, L. Gomes, E. Pistono, A. A. L. Souza, P. Ferrari
This paper presents the design of a voltage controlled Standing-Wave Oscillator for applications in the E-band. A high quality factor tuneable Slow-wave Coplanar Stripline is used for the resonator. Varactors are distributed along the transmission line to mitigate the effect of their low Q-factor on the losses of the resonator. The Slow-wave Coplanar Stripline is asymmetrically sized to maximise the tuning range. The VCO achieves a measured phase noise of −114.9dBc at 80 GHz with 15mW power consumption and 3.3% continuous frequency tuning range.
{"title":"77.8 GHz Standing-wave Oscillator Based on a Tuneable Slow-wave Coplanar Stripline Resonator","authors":"S. Bourdel, Ekta Sharma, L. Gomes, E. Pistono, A. A. L. Souza, P. Ferrari","doi":"10.1109/newcas49341.2020.9159799","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159799","url":null,"abstract":"This paper presents the design of a voltage controlled Standing-Wave Oscillator for applications in the E-band. A high quality factor tuneable Slow-wave Coplanar Stripline is used for the resonator. Varactors are distributed along the transmission line to mitigate the effect of their low Q-factor on the losses of the resonator. The Slow-wave Coplanar Stripline is asymmetrically sized to maximise the tuning range. The VCO achieves a measured phase noise of −114.9dBc at 80 GHz with 15mW power consumption and 3.3% continuous frequency tuning range.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133992511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159775
S. Jeong, Juseop Lee
In this paper, the design approach for an absorptive bandpass filter with a pair of transmission zeros is introduced. The design is based on using dangling resonators coupled to the output port. One of the unique features of the proposed design approach is that the resonant frequencies of the dangling resonators determine the locations of the transmission zeros. In addition, the design method allows us to relocate the transmission zeros without degrading a reflectionless response at the input port. For verification, we have designed three third-order microstrip line filters centered at 3 GHz having 10 % bandwidth. The filters have been designed to have one transmission zero in the lower stopband and one in the upper stopband. For demonstrating the relocation facility, the filters have been designed to have different sets of transmission zeros. The filters have been fabricated and measured for verifying the presented design method.
{"title":"Absorptive Bandpass Filter with a Pair of Transmission Zeros","authors":"S. Jeong, Juseop Lee","doi":"10.1109/newcas49341.2020.9159775","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159775","url":null,"abstract":"In this paper, the design approach for an absorptive bandpass filter with a pair of transmission zeros is introduced. The design is based on using dangling resonators coupled to the output port. One of the unique features of the proposed design approach is that the resonant frequencies of the dangling resonators determine the locations of the transmission zeros. In addition, the design method allows us to relocate the transmission zeros without degrading a reflectionless response at the input port. For verification, we have designed three third-order microstrip line filters centered at 3 GHz having 10 % bandwidth. The filters have been designed to have one transmission zero in the lower stopband and one in the upper stopband. For demonstrating the relocation facility, the filters have been designed to have different sets of transmission zeros. The filters have been fabricated and measured for verifying the presented design method.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131870874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159811
Valentín Gutiérrez, G. Léger
Single Event Transients have become a serious issue in safety-critical applications of Analog and Mixed-Signal (AMS) circuits. Therefore, an evaluation must be carried out in order to diagnose the critical nodes but also to get an idea of the global sensitivity of the circuit, as a proxy to its experimental cross-section. In this work we evaluate two different top-down approaches considering or not the biasing of the impacted transistor to compute the injected charge. Performing an exhaustive evaluation campaign on a high performance buffer as a case of study, it will be shown that the error committed by the charge difference is greater than the one committed by simulating with the simple schematic without layout parasitics. However, the correlation between both approaches is high, so the critical nodes appear in the same order.
{"title":"On the importance of bias-dependent charge injection for SET evaluation in AMS Circuits","authors":"Valentín Gutiérrez, G. Léger","doi":"10.1109/newcas49341.2020.9159811","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159811","url":null,"abstract":"Single Event Transients have become a serious issue in safety-critical applications of Analog and Mixed-Signal (AMS) circuits. Therefore, an evaluation must be carried out in order to diagnose the critical nodes but also to get an idea of the global sensitivity of the circuit, as a proxy to its experimental cross-section. In this work we evaluate two different top-down approaches considering or not the biasing of the impacted transistor to compute the injected charge. Performing an exhaustive evaluation campaign on a high performance buffer as a case of study, it will be shown that the error committed by the charge difference is greater than the one committed by simulating with the simple schematic without layout parasitics. However, the correlation between both approaches is high, so the critical nodes appear in the same order.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124232199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159817
Antoine Back, Paul Chollet, Olivier Fercoq, P. Desgreys
One of the main challenges in the field of wireless sensors is to increase their battery life. Analog-to-feature (A2F) conversion is an acquisition method thought for IoT devices, that perform classification tasks at sub-Nyquist rate, by extracting relevant features in the analog domain and then performing the classification step in the digital domain. Current A2F solutions are designed for a specific application, this paper proposes a method to design a generic A2F converter usable for several signal types. In order to extract information for classification task, we propose to use non uniform wavelet sampling, its drawback is that it brings redundancy and irrelevant information. To reach our goal of decreasing power consumption, we need to extract a small set of relevant features for classification. To achieve this, several features selection algorithms are tested for electrocardiogram (ECG) anomalies detection. We demonstrate that the detection rate of ECG anomalies can reach 98% with less than 10 features extracted.
{"title":"Feature selection algorithms for flexible analog-to-feature converter","authors":"Antoine Back, Paul Chollet, Olivier Fercoq, P. Desgreys","doi":"10.1109/NEWCAS49341.2020.9159817","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159817","url":null,"abstract":"One of the main challenges in the field of wireless sensors is to increase their battery life. Analog-to-feature (A2F) conversion is an acquisition method thought for IoT devices, that perform classification tasks at sub-Nyquist rate, by extracting relevant features in the analog domain and then performing the classification step in the digital domain. Current A2F solutions are designed for a specific application, this paper proposes a method to design a generic A2F converter usable for several signal types. In order to extract information for classification task, we propose to use non uniform wavelet sampling, its drawback is that it brings redundancy and irrelevant information. To reach our goal of decreasing power consumption, we need to extract a small set of relevant features for classification. To achieve this, several features selection algorithms are tested for electrocardiogram (ECG) anomalies detection. We demonstrate that the detection rate of ECG anomalies can reach 98% with less than 10 features extracted.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116975093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159764
A. Gusev, Dmitry Osipov, S. Paul
A new SAR ADC architecture is proposed. The described circuit uses an additional low-resolution capacitive-DAC instead of MSB-capacitors switching in the conventional binary weighted DAC. The use of an additional DAC decreases the MSB capacitors size, therefore improves the energy efficiency and allows to achieve faster operation speed. The circuit operates using a 4-input comparator. The sampling capacitance is 98.4% reduced compared to conventional SAR ADC. The DAC switching energy saving of the proposed circuit is 97.2% compared to a conventional one. The 20 MS/s 10 bit SAR ADC based on the proposed architecture was simulated on transistor level. The power consumption and the Walden FOM are 70.88 uW and 3.71 fJ/conv.-step respectively.
{"title":"An Energy Efficient SAR ADC Architecture with DAC Separation","authors":"A. Gusev, Dmitry Osipov, S. Paul","doi":"10.1109/newcas49341.2020.9159764","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159764","url":null,"abstract":"A new SAR ADC architecture is proposed. The described circuit uses an additional low-resolution capacitive-DAC instead of MSB-capacitors switching in the conventional binary weighted DAC. The use of an additional DAC decreases the MSB capacitors size, therefore improves the energy efficiency and allows to achieve faster operation speed. The circuit operates using a 4-input comparator. The sampling capacitance is 98.4% reduced compared to conventional SAR ADC. The DAC switching energy saving of the proposed circuit is 97.2% compared to a conventional one. The 20 MS/s 10 bit SAR ADC based on the proposed architecture was simulated on transistor level. The power consumption and the Walden FOM are 70.88 uW and 3.71 fJ/conv.-step respectively.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115272710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159829
M. Margalef-Rovira, A. Saadi, S. Bourdel, M. Barragán, E. Pistono, C. Gaquière, P. Ferrari
In this paper, an innovative millimeter-wave (mm-wave) through-load switch for in-situ reflectometers and on-wafer calibration is proposed. This two-port device can switch between two states: (i) a through connection or (ii) a 50 Ω load for both of its ports. The through-load switch is composed of a 3-dB directional coupler and two nMOS transistors controlled through a biasing voltage applied to their gate. Measurement results of a 120-GHz 3-dB directional coupler are provided up to 145 GHz together with EM simulations and circuit-level simulations up to 220 GHz of the through-load switch. A wide bandwidth is obtained, from 73 GHz to 179 GHz, with limited insertion loss of 2 dB.
{"title":"mm-Wave Through-Load Switch for in-situ Vector Network Analyzer on a 55-nm BiCMOS Technology","authors":"M. Margalef-Rovira, A. Saadi, S. Bourdel, M. Barragán, E. Pistono, C. Gaquière, P. Ferrari","doi":"10.1109/newcas49341.2020.9159829","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159829","url":null,"abstract":"In this paper, an innovative millimeter-wave (mm-wave) through-load switch for in-situ reflectometers and on-wafer calibration is proposed. This two-port device can switch between two states: (i) a through connection or (ii) a 50 Ω load for both of its ports. The through-load switch is composed of a 3-dB directional coupler and two nMOS transistors controlled through a biasing voltage applied to their gate. Measurement results of a 120-GHz 3-dB directional coupler are provided up to 145 GHz together with EM simulations and circuit-level simulations up to 220 GHz of the through-load switch. A wide bandwidth is obtained, from 73 GHz to 179 GHz, with limited insertion loss of 2 dB.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115526753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159768
Jing Zeng, Jun Lin, Zhongfeng Wang
As an important part of massive Multi-Input Multi-Output (MIMO) technologies, signal detection has been studied in the literature in recent years. The detection complexity grows significantly as the number of antennas increases in the system. Maximum-likelihood (ML) has the optimal performance with the highest complexity, which is prohibitive for implementation. In this work, we propose a serial ML (SML) algorithm, which changes the way of detection from parallel multi-dimensional searching to serial single-dimensional searching to reduce detection complexity. Besides, we employ a valid initial value for the proposed algorithm to obtain a faster convergence. Based on the simulation results, for the system with 128 receive antennas, the proposed SML algorithm outperforms the Minimum Mean Square Error (MMSE) method under different numbers of users and modulation schemes. When achieving a similar performance, the complexity of serial ML is almost a half of that of low complexity Message Passing Detection algorithm in the system with 16QAM and 16 or 32 users. It is demonstrated that our proposed SML method is more suitable for signal detection when the system adopts low order modulation schemes and serves larger number of users.
{"title":"A Serial Maximum-likelihood Detection Algorithm for Massive MIMO Systems","authors":"Jing Zeng, Jun Lin, Zhongfeng Wang","doi":"10.1109/newcas49341.2020.9159768","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159768","url":null,"abstract":"As an important part of massive Multi-Input Multi-Output (MIMO) technologies, signal detection has been studied in the literature in recent years. The detection complexity grows significantly as the number of antennas increases in the system. Maximum-likelihood (ML) has the optimal performance with the highest complexity, which is prohibitive for implementation. In this work, we propose a serial ML (SML) algorithm, which changes the way of detection from parallel multi-dimensional searching to serial single-dimensional searching to reduce detection complexity. Besides, we employ a valid initial value for the proposed algorithm to obtain a faster convergence. Based on the simulation results, for the system with 128 receive antennas, the proposed SML algorithm outperforms the Minimum Mean Square Error (MMSE) method under different numbers of users and modulation schemes. When achieving a similar performance, the complexity of serial ML is almost a half of that of low complexity Message Passing Detection algorithm in the system with 16QAM and 16 or 32 users. It is demonstrated that our proposed SML method is more suitable for signal detection when the system adopts low order modulation schemes and serves larger number of users.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123493008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159844
S. Azimi, C. D. Sio, Weitao Yang, L. Sterpone
Radiation-induced soft errors have become a significant reliability challenge in modern CMOS logic. The main concern for safety-critical applications such aerospace is due to Single Event Transient (SET) effects. SETs are exacerbated by the technology scaling of modern technologies especially when they are adopted in harsh environments. This paper evaluates the SET sensitivity of state-of-the-art floating gate configurable logic circuit and proposes a novel methodology for filtering a SET pulse generated inside the logic cells by increasing the charge sharing effect on the sensitive node of a cell due to remapping of its configurable switches. Experimental results, performed with radiation particle simulation on several benchmark circuits implemented in a 130nm floating-gate device demonstrate an improvement in filtering SET effects of more than 24% on the average with negligible delay degradation.
{"title":"A New Single Event Transient Hardened Floating Gate Configurable Logic Circuit","authors":"S. Azimi, C. D. Sio, Weitao Yang, L. Sterpone","doi":"10.1109/newcas49341.2020.9159844","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159844","url":null,"abstract":"Radiation-induced soft errors have become a significant reliability challenge in modern CMOS logic. The main concern for safety-critical applications such aerospace is due to Single Event Transient (SET) effects. SETs are exacerbated by the technology scaling of modern technologies especially when they are adopted in harsh environments. This paper evaluates the SET sensitivity of state-of-the-art floating gate configurable logic circuit and proposes a novel methodology for filtering a SET pulse generated inside the logic cells by increasing the charge sharing effect on the sensitive node of a cell due to remapping of its configurable switches. Experimental results, performed with radiation particle simulation on several benchmark circuits implemented in a 130nm floating-gate device demonstrate an improvement in filtering SET effects of more than 24% on the average with negligible delay degradation.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130585017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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