Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159786
A. Ragni, G. Sciortino, M. Sampietro, G. Ferrari, A. Cadena, F. Vernuccio, G. Cerullo, D. Polli
Broadband coherent Raman is a non-invasive and non-destructive spectroscopic technique with growing applications in the analysis of molecules and biological compounds. This paper presents the first 32-ch modular platform for highspeed Broadband Raman Imaging, able to simultaneously acquire and process 32 wavelengths of the spectrum with a multichannel pseudo-differential lock-in structure for the compensation of the excess noise given by the laser source. The system is based on a custom integrated CMOS front-end, specifically designed for Broadband Raman applications, and a Xilinx Artix-7 FPGA for the parallel acquisition and real-time data elaboration. Experimental results show that the system is able to reach the shot noise limit and acquire a Raman image with a pixel dwell time of 100μs.
{"title":"High-Speed and Low-Noise Multichannel System for Broadband Coherent Raman Imaging","authors":"A. Ragni, G. Sciortino, M. Sampietro, G. Ferrari, A. Cadena, F. Vernuccio, G. Cerullo, D. Polli","doi":"10.1109/newcas49341.2020.9159786","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159786","url":null,"abstract":"Broadband coherent Raman is a non-invasive and non-destructive spectroscopic technique with growing applications in the analysis of molecules and biological compounds. This paper presents the first 32-ch modular platform for highspeed Broadband Raman Imaging, able to simultaneously acquire and process 32 wavelengths of the spectrum with a multichannel pseudo-differential lock-in structure for the compensation of the excess noise given by the laser source. The system is based on a custom integrated CMOS front-end, specifically designed for Broadband Raman applications, and a Xilinx Artix-7 FPGA for the parallel acquisition and real-time data elaboration. Experimental results show that the system is able to reach the shot noise limit and acquire a Raman image with a pixel dwell time of 100μs.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131047200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159779
Julian Potschka, J. Zuber, Katharina Kolb, Tim Maiwald, M. Dietz, A. Hagelauer, K. Aufinger, R. Weigel
In this paper, a switchable, passively tuneable 28 GHz to 39 GHz upconversion link for a 5G repeater is proposed and investigated. The upconversion link features an ultra efficient method for output power level adjustment as well as a size efficient broadside coupler for control signal extraction. A tuning range of 7 dB is realized at almost no additional layout effort and zero power consumption. The design yields a measured large signal power gain of 13.8 dB and an input-referred 1 dB compression point of −7.1 dBm; a linearity improvement of 4 dB is achieved by using analog predistortion. For the broadside coupler an insertion loss of −2.2 dB and a coupling of −14 dB is realized. The broadside coupler consumes an area of $340 mumathrm{m} times 220mumathrm{m}$.
{"title":"A Switchable, Passively Tuneable 28 GHz to 39 GHz Upconversion Link for a 5G Repeater using a Broadside Coupler and Analog Predistortion in a 130 nm BiCMOS Technology","authors":"Julian Potschka, J. Zuber, Katharina Kolb, Tim Maiwald, M. Dietz, A. Hagelauer, K. Aufinger, R. Weigel","doi":"10.1109/newcas49341.2020.9159779","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159779","url":null,"abstract":"In this paper, a switchable, passively tuneable 28 GHz to 39 GHz upconversion link for a 5G repeater is proposed and investigated. The upconversion link features an ultra efficient method for output power level adjustment as well as a size efficient broadside coupler for control signal extraction. A tuning range of 7 dB is realized at almost no additional layout effort and zero power consumption. The design yields a measured large signal power gain of 13.8 dB and an input-referred 1 dB compression point of −7.1 dBm; a linearity improvement of 4 dB is achieved by using analog predistortion. For the broadside coupler an insertion loss of −2.2 dB and a coupling of −14 dB is realized. The broadside coupler consumes an area of $340 mumathrm{m} times 220mumathrm{m}$.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126924860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159792
A. A. Shakoush, E. Lauga-Larroze, F. Podevin, S. Ibrahim, L. Fesquet, S. Bourdel
The purpose of this paper is to study the complexity of the Harmonic Rejection N-Path Mixer HRNPM based receivers. In this framework, a HR-NPM architecture has been discussed based on the π-delayed driving signals. The harmonic rejection and the system complexity have been improved with this new architecture such that the Harmonic rejection achieved by this structure is the same of the conventional HR-2NPM and the system complexity has been reduced by half, where as the number of the gain stages and the switches has been reduced. In this context, a 5-path mixer is thus proposed. It allows rejecting up to the 8th harmonic with only 2 differential gain stages by appropriately implementing the switches whereas only the 6th harmonic would be rejected with conventional HR-8PM topologies having 3 amplifier stages. Our structure shows high resilience to clocks overlapping effects.
{"title":"Improved $pi$-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver","authors":"A. A. Shakoush, E. Lauga-Larroze, F. Podevin, S. Ibrahim, L. Fesquet, S. Bourdel","doi":"10.1109/newcas49341.2020.9159792","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159792","url":null,"abstract":"The purpose of this paper is to study the complexity of the Harmonic Rejection N-Path Mixer HRNPM based receivers. In this framework, a HR-NPM architecture has been discussed based on the π-delayed driving signals. The harmonic rejection and the system complexity have been improved with this new architecture such that the Harmonic rejection achieved by this structure is the same of the conventional HR-2NPM and the system complexity has been reduced by half, where as the number of the gain stages and the switches has been reduced. In this context, a 5-path mixer is thus proposed. It allows rejecting up to the 8th harmonic with only 2 differential gain stages by appropriately implementing the switches whereas only the 6th harmonic would be rejected with conventional HR-8PM topologies having 3 amplifier stages. Our structure shows high resilience to clocks overlapping effects.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126312730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159802
Masoume Akbari, M. Honarparvar, Y. Savaria, M. Sawan
An OTA-free two-step incremental ADC (IADC) based on the noise-shaping successive approximation register (NS-SAR) topology is presented in this paper. During the first step, the ADC is configured as a multi-stage noise-shaping (MASH) 2–2 NS-SAR incremental ADC. During the second step, the first stage of the ADC is re-used to enhance the resolution of the incremental ADC. Employing 4-bit SAR ADCs as core quantizers, along with re-using parts of the hardware, can make this structure area and power-efficient. Simulation results, performed with MATLAB/SIMULINK, demonstrate the efficiency of the proposed ADC featuring a signal to quantization noise ratio (SQNR) of 150 dB, with an oversampling rate (OSR) of 48 over a 250 kHz bandwidth.
{"title":"OTA-Free MASH Two-Step Incremental ADC based on Noise Shaping SAR ADCs","authors":"Masoume Akbari, M. Honarparvar, Y. Savaria, M. Sawan","doi":"10.1109/newcas49341.2020.9159802","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159802","url":null,"abstract":"An OTA-free two-step incremental ADC (IADC) based on the noise-shaping successive approximation register (NS-SAR) topology is presented in this paper. During the first step, the ADC is configured as a multi-stage noise-shaping (MASH) 2–2 NS-SAR incremental ADC. During the second step, the first stage of the ADC is re-used to enhance the resolution of the incremental ADC. Employing 4-bit SAR ADCs as core quantizers, along with re-using parts of the hardware, can make this structure area and power-efficient. Simulation results, performed with MATLAB/SIMULINK, demonstrate the efficiency of the proposed ADC featuring a signal to quantization noise ratio (SQNR) of 150 dB, with an oversampling rate (OSR) of 48 over a 250 kHz bandwidth.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121047766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159847
Mohamed Akrarai, Nils Margotat, G. Sicard, L. Fesquet
We present a new image sensor architecture that manages spacial and temporal redundancies. This frameless image sensor only generates few events over time in order to target an efficient power consumption compared to the commercial CMOS image sensors. Indeed, this image sensor does not generate anymore frames but events only when a change appears in the scene. Moreover, the event throughput depends on the luminance variations of the recorded scene. This means that more activity in the scene will generate more events and vice versa. Collecting events over a period of time will define an image. It is noticeable that, at each instant, the generated events characterize the area of interest (the active area) of the scene. Consequently, processing such images should requires less computing energy.
{"title":"A Novel Event Based Image Sensor with spacial and temporal redundancy suppression","authors":"Mohamed Akrarai, Nils Margotat, G. Sicard, L. Fesquet","doi":"10.1109/NEWCAS49341.2020.9159847","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159847","url":null,"abstract":"We present a new image sensor architecture that manages spacial and temporal redundancies. This frameless image sensor only generates few events over time in order to target an efficient power consumption compared to the commercial CMOS image sensors. Indeed, this image sensor does not generate anymore frames but events only when a change appears in the scene. Moreover, the event throughput depends on the luminance variations of the recorded scene. This means that more activity in the scene will generate more events and vice versa. Collecting events over a period of time will define an image. It is noticeable that, at each instant, the generated events characterize the area of interest (the active area) of the scene. Consequently, processing such images should requires less computing energy.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116520723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159777
Hiro Tamura, K. Yanagisawa, A. Shirane, K. Okada
This paper presents a wireless device identification method that uses a convolutional neural network (CNN) operating on a quadrant IQ transition image. The proposed method can identify IoT wireless devices by exploiting their RF fingerprints, which is a technology to identify wireless devices using variation in analog signals. We proposed a quadrant IQ image technique to reduce the size of CNN while maintaining the accuracy. The CNN utilizes the IQ transition image, which is cut out into four-part. The over-the-air measurement was performed with six Zigbee wireless devices to confirm the validity of the proposed identification method. The measurement results demonstrate that the proposed method can achieve 99% accuracy with the light-weight CNN model with 36,500 trainable parameters. Furthermore, the proposed threshold algorithm can realize the detection of unknown devices that are not trained with 80% accuracy for further secured wireless communication.
{"title":"Wireless Devices Identification with Light-Weight Convolutional Neural Network Operating on Quadrant IQ Transition Image","authors":"Hiro Tamura, K. Yanagisawa, A. Shirane, K. Okada","doi":"10.1109/newcas49341.2020.9159777","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159777","url":null,"abstract":"This paper presents a wireless device identification method that uses a convolutional neural network (CNN) operating on a quadrant IQ transition image. The proposed method can identify IoT wireless devices by exploiting their RF fingerprints, which is a technology to identify wireless devices using variation in analog signals. We proposed a quadrant IQ image technique to reduce the size of CNN while maintaining the accuracy. The CNN utilizes the IQ transition image, which is cut out into four-part. The over-the-air measurement was performed with six Zigbee wireless devices to confirm the validity of the proposed identification method. The measurement results demonstrate that the proposed method can achieve 99% accuracy with the light-weight CNN model with 36,500 trainable parameters. Furthermore, the proposed threshold algorithm can realize the detection of unknown devices that are not trained with 80% accuracy for further secured wireless communication.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117050331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159834
G. Franco, Dang-Kièn Germain Pham, P. Desgreys
Recent wireless architectures have increased requirements in terms of power consumption and linearity. These requirements concern specially the power amplifier (PA) responsible for driving the antenna. One architecture proposed for this role is the outphasing amplifier, which realizes linear amplification using non-linear components. To generate the waveforms required by the switched-mode outphasing architecture, the Digital Interpolating Phase Modulator (DIPM) was proposed recently. It works by reconstructing a constant amplitude RF signal using several DSP engines. However, the authors only describe an implementation with four signal processing engines by hypothesis. In this paper, an implementation of the DIPM algorithm is developed, alongside an exploration on the number of signal processing engines used. Furthermore, the digital design is synthesized in two different process technologies to contrast power and area utilization. Our simulations confirm their choice of number of engines if power is a constraint. However, other requirements, such as technology used, may lead to different solutions.
{"title":"Digital Interpolating Phase Modulator Implementation for Outphasing PA","authors":"G. Franco, Dang-Kièn Germain Pham, P. Desgreys","doi":"10.1109/newcas49341.2020.9159834","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159834","url":null,"abstract":"Recent wireless architectures have increased requirements in terms of power consumption and linearity. These requirements concern specially the power amplifier (PA) responsible for driving the antenna. One architecture proposed for this role is the outphasing amplifier, which realizes linear amplification using non-linear components. To generate the waveforms required by the switched-mode outphasing architecture, the Digital Interpolating Phase Modulator (DIPM) was proposed recently. It works by reconstructing a constant amplitude RF signal using several DSP engines. However, the authors only describe an implementation with four signal processing engines by hypothesis. In this paper, an implementation of the DIPM algorithm is developed, alongside an exploration on the number of signal processing engines used. Furthermore, the digital design is synthesized in two different process technologies to contrast power and area utilization. Our simulations confirm their choice of number of engines if power is a constraint. However, other requirements, such as technology used, may lead to different solutions.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117074942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159769
G. B. Hacene, Vincent Gripon, M. Arzel, Nicolas Farrugia, Y. Bengio
Deep Neural Networks (DNNs) in general and Convolutional Neural Networks (CNNs) in particular are state-of-the-art in numerous computer vision tasks such as object classification and detection. However, the large amount of parameters they contain leads to a high computational complexity and strongly limits their usability in budget-constrained devices such as embedded devices. In this paper, we propose a combination of a pruning technique and a quantization scheme that effectively reduce the complexity and memory usage of convolutional layers of CNNs, by replacing the complex convolutional operation by a low-cost multiplexer. We perform experiments on CIFAR10, CIFAR100 and SVHN datasets and show that the proposed method achieves almost state-of-the-art accuracy, while drastically reducing the computational and memory footprints compared to the baselines. We also propose an efficient hardware architecture, implemented on Field Programmable Gate Arrays (FPGAs), to accelerate inference, which works as a pipeline and accommodates multiple layers working at the same time to speed up the inference process. In contrast with most proposed approaches which have used external memory or software defined memory controllers, our work is based on algorithmic optimization and full-hardware design, enabling a direct, on-chip memory implementation of a DNN while keeping close to state of the art accuracy.
{"title":"Quantized Guided Pruning for Efficient Hardware Implementations of Deep Neural Networks","authors":"G. B. Hacene, Vincent Gripon, M. Arzel, Nicolas Farrugia, Y. Bengio","doi":"10.1109/newcas49341.2020.9159769","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159769","url":null,"abstract":"Deep Neural Networks (DNNs) in general and Convolutional Neural Networks (CNNs) in particular are state-of-the-art in numerous computer vision tasks such as object classification and detection. However, the large amount of parameters they contain leads to a high computational complexity and strongly limits their usability in budget-constrained devices such as embedded devices. In this paper, we propose a combination of a pruning technique and a quantization scheme that effectively reduce the complexity and memory usage of convolutional layers of CNNs, by replacing the complex convolutional operation by a low-cost multiplexer. We perform experiments on CIFAR10, CIFAR100 and SVHN datasets and show that the proposed method achieves almost state-of-the-art accuracy, while drastically reducing the computational and memory footprints compared to the baselines. We also propose an efficient hardware architecture, implemented on Field Programmable Gate Arrays (FPGAs), to accelerate inference, which works as a pipeline and accommodates multiple layers working at the same time to speed up the inference process. In contrast with most proposed approaches which have used external memory or software defined memory controllers, our work is based on algorithmic optimization and full-hardware design, enabling a direct, on-chip memory implementation of a DNN while keeping close to state of the art accuracy.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123082602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159821
Saba Mohammadi, Michael M. Green
A comprehensive analysis on quadrature feedforward ring oscillators is presented. The propagation delay and oscillation frequency for one particular oscillator are simulated using 180nm CMOS technology. Conditions for oscillation are derived analytically based on circuit parameters and confirmed through simulations.
{"title":"A Rigorous Analysis on Quadrature Single-Ended Ring Oscillators","authors":"Saba Mohammadi, Michael M. Green","doi":"10.1109/newcas49341.2020.9159821","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159821","url":null,"abstract":"A comprehensive analysis on quadrature feedforward ring oscillators is presented. The propagation delay and oscillation frequency for one particular oscillator are simulated using 180nm CMOS technology. Conditions for oscillation are derived analytically based on circuit parameters and confirmed through simulations.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124507224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159820
Huili Chen, S. Potluri, F. Koushanfar
We propose FlowTrojan, the first systematic framework for insertion and detection of Hardware Trojans (HTs) on Flow-based Microfluidic Biochips (FMFBs). The FMFB is an emerging platform with critical usages in the medical field due to the handling of sensitive information. We discuss the attack model where the malicious foundry aims to compromise the on-chip control circuitry. FlowTrojan is designed to automatically extract the netlist for the control circuitry from the layout and explore the internal independence between regions on FMFBs for partitioning. We demonstrate that HT triggers can feature a low activation probability while placed on the non-critical timing path to stay clandestine during functional and parametric testing. To avoid such attacks, FlowTrojan provides a parallel regime of control-value (CV) based HT detection as the countermeasure. Experimental results corroborate the effectiveness and scalability of the proposed attack and detection schemes.
{"title":"FlowTrojan: Insertion and Detection of Hardware Trojans on Flow-Based Microfluidic Biochips","authors":"Huili Chen, S. Potluri, F. Koushanfar","doi":"10.1109/NEWCAS49341.2020.9159820","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159820","url":null,"abstract":"We propose FlowTrojan, the first systematic framework for insertion and detection of Hardware Trojans (HTs) on Flow-based Microfluidic Biochips (FMFBs). The FMFB is an emerging platform with critical usages in the medical field due to the handling of sensitive information. We discuss the attack model where the malicious foundry aims to compromise the on-chip control circuitry. FlowTrojan is designed to automatically extract the netlist for the control circuitry from the layout and explore the internal independence between regions on FMFBs for partitioning. We demonstrate that HT triggers can feature a low activation probability while placed on the non-critical timing path to stay clandestine during functional and parametric testing. To avoid such attacks, FlowTrojan provides a parallel regime of control-value (CV) based HT detection as the countermeasure. Experimental results corroborate the effectiveness and scalability of the proposed attack and detection schemes.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123485149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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