Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159803
Mengye Cai, K. Takahata, S. Mirabbasi
This paper presents a low-voltage low-power implantable telemonitoring system in the context of a smart stent that uses wireless endo-hyperthermia for the treatment of in-stent restenosis. More specifically, an application specific integrated circuit (ASIC) is designed and implemented that senses the ambient temperature and wirelessly transmits the sensory information to a nearby hub. A customized “smart” stent is used as an antenna for wireless data and power transfer over the unlicensed industrial, scientific, and medical (ISM) 915 MHz and 2.4 GHz bands, respectively. For the prototype design, the ASIC is embedded on the small platform at the end of the custom-made stent that also serves as an antenna and the circuit functions without requiring any off-chip components. The proposed fully integrated solution has the following functionalities: radio-frequency (RF) telemetry, power management unit (RF -to-DC converter and voltage regulation), and temperature sensing. The proof-of-concept prototype ASIC is designed and fabricated in a $0.13-mu mathrm{m}$ CMOS process and has a chip area of 1.56 mm2. The device can detect and response to the temperature variations in the range of 30 to 50 °C. The remote power link is established when the power received by the implantable device is about −8 dBm. The data can be transmitted from the ASIC to an external hub at the power level of −28.38 dBm, with the total power consumption of 109.6 $mumathrm{W}$.
{"title":"A Low-Voltage Low-Power Implantable Telemonitoring System with Application to Endo-Hyperthermia Treatment of In-Stent Restenosis","authors":"Mengye Cai, K. Takahata, S. Mirabbasi","doi":"10.1109/NEWCAS49341.2020.9159803","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159803","url":null,"abstract":"This paper presents a low-voltage low-power implantable telemonitoring system in the context of a smart stent that uses wireless endo-hyperthermia for the treatment of in-stent restenosis. More specifically, an application specific integrated circuit (ASIC) is designed and implemented that senses the ambient temperature and wirelessly transmits the sensory information to a nearby hub. A customized “smart” stent is used as an antenna for wireless data and power transfer over the unlicensed industrial, scientific, and medical (ISM) 915 MHz and 2.4 GHz bands, respectively. For the prototype design, the ASIC is embedded on the small platform at the end of the custom-made stent that also serves as an antenna and the circuit functions without requiring any off-chip components. The proposed fully integrated solution has the following functionalities: radio-frequency (RF) telemetry, power management unit (RF -to-DC converter and voltage regulation), and temperature sensing. The proof-of-concept prototype ASIC is designed and fabricated in a $0.13-mu mathrm{m}$ CMOS process and has a chip area of 1.56 mm2. The device can detect and response to the temperature variations in the range of 30 to 50 °C. The remote power link is established when the power received by the implantable device is about −8 dBm. The data can be transmitted from the ASIC to an external hub at the power level of −28.38 dBm, with the total power consumption of 109.6 $mumathrm{W}$.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121154244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159794
Mina Gad, A. Elshennawy, A. Ismail
Delta-Sigma $(DeltaSigma)$ technique represents an optimum way for realizing force-feedback electromechanical systems, especially for capacitive sensors. However, when operating the sensor in feedback, the stability of the system becomes a concern, particularly, in $DeltaSigma$ -based systems, and the higher the order of the system, the harder it becomes to achieve stability. Hence, following a systematic design flow for these systems is essential. While the design of stable electrical $DeltaSigma$ loops is well established, the design of electromechanical $DeltaSigma$ loops presents a challenge due to the nature of the capacitive sensor resonator. In this work, a way to stabilize high-order $DeltaSigma$-based interface systems for inertial capacitive sensors is introduced and a systematic design approach is proposed. The design approach is based on noise transfer function (NTF) matching which translates the system design problem to an NTF design problem as in electrical $DeltaSigma$ loops. The design approach is applied to the design of a fifth-order $DeltaSigma$ based interface for a capacitive accelerometer. The sensor has a $0.12 mu mathrm{g}$ proof-mass, a resonance frequency of 1.8 kHz, a displacement-to-capacitance factor of $3.22 text{pF}/ mu mathrm{m}$ and a feedback factor of $0.7 mu mathrm{N/V}^{2}$. The designed system achieves a signal-to-quantization noise ratio (SQNR) of 181 dB.
Delta-Sigma $(DeltaSigma)$技术代表了实现力反馈机电系统的最佳方式，特别是对于电容式传感器。然而，当在反馈中操作传感器时，系统的稳定性成为一个问题，特别是在基于$DeltaSigma$的系统中，系统的阶数越高，就越难实现稳定性。因此，遵循这些系统的系统设计流程是必不可少的。虽然稳定电气$DeltaSigma$回路的设计已经很好地建立，但由于电容式传感器谐振器的性质，机电$DeltaSigma$回路的设计提出了挑战。本文介绍了一种稳定惯性电容传感器高阶$DeltaSigma$接口系统的方法，并提出了一种系统的设计方法。设计方法基于噪声传递函数(NTF)匹配，将系统设计问题转化为电气$DeltaSigma$回路中的NTF设计问题。将该设计方法应用于电容式加速度计的五阶$DeltaSigma$接口设计。该传感器的验证质量为$0.12 mu mathrm{g}$，谐振频率为1.8 kHz，位移-电容因子为$3.22 text{pF}/ mu mathrm{m}$，反馈因子为$0.7 mu mathrm{N/V}^{2}$。该系统的信量化噪声比(SQNR)为181 dB。
{"title":"A Design Method for $Deltasum$ Force-Feedback Accelerometer Interface Systems","authors":"Mina Gad, A. Elshennawy, A. Ismail","doi":"10.1109/newcas49341.2020.9159794","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159794","url":null,"abstract":"Delta-Sigma $(DeltaSigma)$ technique represents an optimum way for realizing force-feedback electromechanical systems, especially for capacitive sensors. However, when operating the sensor in feedback, the stability of the system becomes a concern, particularly, in $DeltaSigma$ -based systems, and the higher the order of the system, the harder it becomes to achieve stability. Hence, following a systematic design flow for these systems is essential. While the design of stable electrical $DeltaSigma$ loops is well established, the design of electromechanical $DeltaSigma$ loops presents a challenge due to the nature of the capacitive sensor resonator. In this work, a way to stabilize high-order $DeltaSigma$-based interface systems for inertial capacitive sensors is introduced and a systematic design approach is proposed. The design approach is based on noise transfer function (NTF) matching which translates the system design problem to an NTF design problem as in electrical $DeltaSigma$ loops. The design approach is applied to the design of a fifth-order $DeltaSigma$ based interface for a capacitive accelerometer. The sensor has a $0.12 mu mathrm{g}$ proof-mass, a resonance frequency of 1.8 kHz, a displacement-to-capacitance factor of $3.22 text{pF}/ mu mathrm{m}$ and a feedback factor of $0.7 mu mathrm{N/V}^{2}$. The designed system achieves a signal-to-quantization noise ratio (SQNR) of 181 dB.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126177164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159793
Dominik Veit, J. Oehm
This paper presents a significantly improved concept for a proportional-to-absolute temperature (PTAT) current reference designed and manufactured for test purposes in a 0.18 μm 5V standard CMOS technology. The current reference concept has been proven to be very robust against both manufacturing tolerances and supply voltage interference over a very wide supply voltage and temperature range. An evaluation of 19 Die-to-Die (D2D) samples of the manufactured current source showed a worst-case variation in the output currents of only $pm 3%$. Finally, a supplementary Monte Carlo Lot-to-Lot (L2L) simulation with a sample size of 1000 showed that the to be expected worst-case tolerance should be smaller than $pm 12 %$. The circuit consists of 3 stacked unbalanced differential pairs operating in weak channel inversion, which are used as a PTAT voltage generator to define a current by means of a current loop consisting of a linear and nonlinear current mirror. By this it can be achieved that the overall statistics of the reference current is almost exclusively determined by the oxide thickness statistics. The manufactured version of the proposed current reference circuit provides a reference current of 2.2 μA, the area required is 0.1 mm2. A simulation of a cascoded version for DC blocking ratio $mathrm{PSRR} =20log_{10}(vert deltamathrm{I}_{mathrm{R}mathrm{e}mathrm{f}}/deltamathrm{V}_{mathrm{d}mathrm{d}}vert /(mathrm{I}_{mathrm{R}mathrm{e}mathrm{f}}/mathrm{V}_{mathrm{d}mathrm{d}}))$ of the power supply $mathrm{V}_{mathrm{d}mathrm{d}}$ onto the reference current IRef provides −50 dB within the $mathrm{V}_{mathrm{d}mathrm{d}}$ range from 1.3 V to 5 V.
{"title":"A Current Reference with high Robustness to Process and Supply Voltage Variations unaffected by Body Effect upon Threshold Voltage","authors":"Dominik Veit, J. Oehm","doi":"10.1109/newcas49341.2020.9159793","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159793","url":null,"abstract":"This paper presents a significantly improved concept for a proportional-to-absolute temperature (PTAT) current reference designed and manufactured for test purposes in a 0.18 μm 5V standard CMOS technology. The current reference concept has been proven to be very robust against both manufacturing tolerances and supply voltage interference over a very wide supply voltage and temperature range. An evaluation of 19 Die-to-Die (D2D) samples of the manufactured current source showed a worst-case variation in the output currents of only $pm 3%$. Finally, a supplementary Monte Carlo Lot-to-Lot (L2L) simulation with a sample size of 1000 showed that the to be expected worst-case tolerance should be smaller than $pm 12 %$. The circuit consists of 3 stacked unbalanced differential pairs operating in weak channel inversion, which are used as a PTAT voltage generator to define a current by means of a current loop consisting of a linear and nonlinear current mirror. By this it can be achieved that the overall statistics of the reference current is almost exclusively determined by the oxide thickness statistics. The manufactured version of the proposed current reference circuit provides a reference current of 2.2 μA, the area required is 0.1 mm2. A simulation of a cascoded version for DC blocking ratio $mathrm{PSRR} =20log_{10}(vert deltamathrm{I}_{mathrm{R}mathrm{e}mathrm{f}}/deltamathrm{V}_{mathrm{d}mathrm{d}}vert /(mathrm{I}_{mathrm{R}mathrm{e}mathrm{f}}/mathrm{V}_{mathrm{d}mathrm{d}}))$ of the power supply $mathrm{V}_{mathrm{d}mathrm{d}}$ onto the reference current IRef provides −50 dB within the $mathrm{V}_{mathrm{d}mathrm{d}}$ range from 1.3 V to 5 V.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114795157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159845
Man Wu, Yan Chen, Yirong Kan, Takeshi Nomura, Renyuan Zhang, Y. Nakashima
A bisection topology of neural networks (NN) is developed instead of conventional full connection (FC) fashion for NNs. Each neuron only communicates with two synapses from its previous neurons in adjacent, and outputs the data to two neurons in the post layer. A large amount of neurons and synapses are expected to symmetrically implement by the computational hardware in parallel. In this manner, the entire network can be partitioned into arbitrary diamond-shaped pieces (seen as DiaNet) for behaving the NN functions without any redundancy theoretically. Assuming such topology is implemented on-chip in parallel, the DiaNets perform multi-grained re-configuration to offer flexible function units. Various behaviors of conventional NNs are efficiently retrieved by the proposed DiaNet topology while maintaining high fidelity of results. Also, two optimization technologies such as overlapping and reshaping are proposed to further reduce the synapses. On the Wine dataset, our results show that the number of synapses is reduced to 36.3% without accuracy loss. Finally, the bit precision of the DiaNet is investigated to suggest the guideline toward efficient hardware implementations.
{"title":"An Elastic Neural Network Toward Multi-Grained Re-configurable Accelerator","authors":"Man Wu, Yan Chen, Yirong Kan, Takeshi Nomura, Renyuan Zhang, Y. Nakashima","doi":"10.1109/newcas49341.2020.9159845","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159845","url":null,"abstract":"A bisection topology of neural networks (NN) is developed instead of conventional full connection (FC) fashion for NNs. Each neuron only communicates with two synapses from its previous neurons in adjacent, and outputs the data to two neurons in the post layer. A large amount of neurons and synapses are expected to symmetrically implement by the computational hardware in parallel. In this manner, the entire network can be partitioned into arbitrary diamond-shaped pieces (seen as DiaNet) for behaving the NN functions without any redundancy theoretically. Assuming such topology is implemented on-chip in parallel, the DiaNets perform multi-grained re-configuration to offer flexible function units. Various behaviors of conventional NNs are efficiently retrieved by the proposed DiaNet topology while maintaining high fidelity of results. Also, two optimization technologies such as overlapping and reshaping are proposed to further reduce the synapses. On the Wine dataset, our results show that the number of synapses is reduced to 36.3% without accuracy loss. Finally, the bit precision of the DiaNet is investigated to suggest the guideline toward efficient hardware implementations.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129079061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159830
Mousa Karimi, Mohamed Ali, Ahmad Hassan, Guillaume Weber-boisvert, Ahmed Abuelnasr, M. Sawan, B. Gosselin
In this paper, we present a novel topology of level shifter circuit implemented in 0.35 μm CMOS technology. In this design, a closed-loop negative feedback is employed to decrease both propagation delay and power dissipation. A voltage controlled current source, three n-type MOSFETs, and three inverters have been utilized to implement the proposed fast and wide frequency range level shifter. The proposed approach has been validated with post-layout simulation results. It achieves an energy consumption of 0.551 pJ at 1MHz and a propagation delay of 1.99 ns while occupying only 25 μm×25 μm of silicon area. In addition, Shmoo plot is provided to show the circuit functionality over a frequency range of 1 Hz to 225 MHz.
{"title":"A 1.99-ns 0.5-pJ Wide Frequency Range Level Shifter With Closed-Loop Negative Feedback","authors":"Mousa Karimi, Mohamed Ali, Ahmad Hassan, Guillaume Weber-boisvert, Ahmed Abuelnasr, M. Sawan, B. Gosselin","doi":"10.1109/newcas49341.2020.9159830","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159830","url":null,"abstract":"In this paper, we present a novel topology of level shifter circuit implemented in 0.35 μm CMOS technology. In this design, a closed-loop negative feedback is employed to decrease both propagation delay and power dissipation. A voltage controlled current source, three n-type MOSFETs, and three inverters have been utilized to implement the proposed fast and wide frequency range level shifter. The proposed approach has been validated with post-layout simulation results. It achieves an energy consumption of 0.551 pJ at 1MHz and a propagation delay of 1.99 ns while occupying only 25 μm×25 μm of silicon area. In addition, Shmoo plot is provided to show the circuit functionality over a frequency range of 1 Hz to 225 MHz.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127609754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159757
G. A. Subbarao, P. Häfliger
Asynchronous Arbiters are an important component of asynchronous circuits. Several versions of asynchronous arbiters designed with Mutual exclusion elements and/or Muller C-elements have been proposed so far. They vary in the number of transistors used, responsiveness to client requests and the ability to be synthesized through Hardware Description Language (HDL). In applications such as Network-on-Chip, which use a large number of arbiters, the number of transistors used and HDL synthesizability are critical. This paper presents an improved 2-way asynchronous arbiter circuit for such applications. It also presents a comprehensive review and comparison of previously proposed solutions. All the compared arbiters were simulated in TSMC 65nm CMOS technology.
{"title":"Design and Comparison of Synthesizable Fair Asynchronous Arbiter","authors":"G. A. Subbarao, P. Häfliger","doi":"10.1109/NEWCAS49341.2020.9159757","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159757","url":null,"abstract":"Asynchronous Arbiters are an important component of asynchronous circuits. Several versions of asynchronous arbiters designed with Mutual exclusion elements and/or Muller C-elements have been proposed so far. They vary in the number of transistors used, responsiveness to client requests and the ability to be synthesized through Hardware Description Language (HDL). In applications such as Network-on-Chip, which use a large number of arbiters, the number of transistors used and HDL synthesizability are critical. This paper presents an improved 2-way asynchronous arbiter circuit for such applications. It also presents a comprehensive review and comparison of previously proposed solutions. All the compared arbiters were simulated in TSMC 65nm CMOS technology.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128049872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159843
F. Sabahi, M. Ahmad, M. Swamy
In recent times, image retrieval has garnered an increasing amount of interest due to the introduction of image datasets of significant size. Many methods have been suggested to retrieve images swiftly and accurately. However, the majority of these techniques are centered on the representation of the image. It is felt that alongside the representation of the image, smart storage is required that can rise to the demands of the task. A possible solution is to model human visual memory, retrieving images by imitating the brain's detection processes. This paper proposes a memory model that can be employed as smart memory for efficiently retrieving images based on image hashes. The memory model accepts hash code inputs derived from DWT and DCT transformations. The model is evaluated in terms of the memory capacity and the accuracy of the image retrieval. The results demonstrate that this model has a greater capacity and is significantly quicker than other types of memory models.
{"title":"ExSDM: Novel Content-based Image Retrieval based on Sparse Distributed Memory Model","authors":"F. Sabahi, M. Ahmad, M. Swamy","doi":"10.1109/newcas49341.2020.9159843","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159843","url":null,"abstract":"In recent times, image retrieval has garnered an increasing amount of interest due to the introduction of image datasets of significant size. Many methods have been suggested to retrieve images swiftly and accurately. However, the majority of these techniques are centered on the representation of the image. It is felt that alongside the representation of the image, smart storage is required that can rise to the demands of the task. A possible solution is to model human visual memory, retrieving images by imitating the brain's detection processes. This paper proposes a memory model that can be employed as smart memory for efficiently retrieving images based on image hashes. The memory model accepts hash code inputs derived from DWT and DCT transformations. The model is evaluated in terms of the memory capacity and the accuracy of the image retrieval. The results demonstrate that this model has a greater capacity and is significantly quicker than other types of memory models.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134504824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159828
Abdel-Latif Alshalalfah, Ghaith Bany Hamad, O. Mohamed
Artificial pancreas enhances the life experience for diabetic patients by allowing them to live normally with their glucose levels controlled automatically with minimal or no intervention. For closed-loop glucose controllers to be approved for clinical practice, they have to prove safety under all potential scenarios. One of the biggest challenges of closed-loop glucose control is to handle the distortion caused by meal intake. In this paper, we construct an improvement on the Proportional- Integral- Derivative (PID) controller by proposing an adaptive weighted PID strategy for robust glucose control under varying meal conditions. The proposed approach mimics the recommended clinical practice by varying the weights based on the current and previous status. Statistical model checking was conducted to analyze the performance figures and safety properties as compared with the standard PID strategy. The results have shown that the proposed approach outperforms the standard PID control in avoiding postprandial hypoglycemia without sacrificing the glycemic control.
{"title":"Towards Safe and Robust Closed-Loop Artificial Pancreas Using Adaptive Weighted PID Control Strategy","authors":"Abdel-Latif Alshalalfah, Ghaith Bany Hamad, O. Mohamed","doi":"10.1109/NEWCAS49341.2020.9159828","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159828","url":null,"abstract":"Artificial pancreas enhances the life experience for diabetic patients by allowing them to live normally with their glucose levels controlled automatically with minimal or no intervention. For closed-loop glucose controllers to be approved for clinical practice, they have to prove safety under all potential scenarios. One of the biggest challenges of closed-loop glucose control is to handle the distortion caused by meal intake. In this paper, we construct an improvement on the Proportional- Integral- Derivative (PID) controller by proposing an adaptive weighted PID strategy for robust glucose control under varying meal conditions. The proposed approach mimics the recommended clinical practice by varying the weights based on the current and previous status. Statistical model checking was conducted to analyze the performance figures and safety properties as compared with the standard PID strategy. The results have shown that the proposed approach outperforms the standard PID control in avoiding postprandial hypoglycemia without sacrificing the glycemic control.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133753218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159808
Jérémy Nadal, Mickaël Fiorentino, Elsa Dupraz, François Leduc-Primeau
A deeply pipelined and parallel LDPC decoder architecture is proposed in this paper. The main feature of this architecture is the Δ-update scheme, which relaxes the data dependency requirement and allows for deeper pipelines than typical decoders. The proposed architecture also has the flexibility to handle a large number of codes. Frame error rate performance is shown for three codes with different quantization parameters. Finally, the impact of pipeline depth on processing time and on the energy-delay product (EDP) is evaluated from post-synthesis results. The results show that the ability to have deeper pipelines can lead to large reductions in EDP.
{"title":"A Deeply Pipelined, Highly Parallel and Flexible LDPC Decoder","authors":"Jérémy Nadal, Mickaël Fiorentino, Elsa Dupraz, François Leduc-Primeau","doi":"10.1109/newcas49341.2020.9159808","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159808","url":null,"abstract":"A deeply pipelined and parallel LDPC decoder architecture is proposed in this paper. The main feature of this architecture is the Δ-update scheme, which relaxes the data dependency requirement and allows for deeper pipelines than typical decoders. The proposed architecture also has the flexibility to handle a large number of codes. Frame error rate performance is shown for three codes with different quantization parameters. Finally, the impact of pipeline depth on processing time and on the energy-delay product (EDP) is evaluated from post-synthesis results. The results show that the ability to have deeper pipelines can lead to large reductions in EDP.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130138879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159798
Laura Gagliano, F. Lesage, E. B. Assi, D. Nguyen, M. Sawan
The quality of life of patients with refractory epilepsy can be significantly improved by designing algorithms capable of forecasting seizures and implementing them into closed-loop advisory/intervention devices. Over the last decade, several algorithms based on neural networks and deep learning have been proposed and showed promising performances. Nevertheless, the computational requirements of such algorithms were major obstacles towards their use in clinical devices. In this work, we overview recently proposed neural network-based seizure forecasting algorithms and summarize the state of the art regarding advancement in hardware design and implementation of deep neural network inferences. The paper ends with a list of recommendation for future seizure forecasting endeavors.
{"title":"Neural Networks for Epileptic Seizure Prediction: Algorithms and Hardware Implementation","authors":"Laura Gagliano, F. Lesage, E. B. Assi, D. Nguyen, M. Sawan","doi":"10.1109/NEWCAS49341.2020.9159798","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159798","url":null,"abstract":"The quality of life of patients with refractory epilepsy can be significantly improved by designing algorithms capable of forecasting seizures and implementing them into closed-loop advisory/intervention devices. Over the last decade, several algorithms based on neural networks and deep learning have been proposed and showed promising performances. Nevertheless, the computational requirements of such algorithms were major obstacles towards their use in clinical devices. In this work, we overview recently proposed neural network-based seizure forecasting algorithms and summarize the state of the art regarding advancement in hardware design and implementation of deep neural network inferences. The paper ends with a list of recommendation for future seizure forecasting endeavors.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114009038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：