Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159796
Ahmad Hassan, Mostafa Amer, Y. Savaria, M. Sawan
This paper contributes toward the implementation of Gallium Nitride (GaN)-based integrated circuits (ICs) intended for high-temperature (HT) applications. We present the implementation and HT characterization of epitaxial AlGaN/GaN Heterojunction Field Effect Transistors (HFETs). The AlGaN/GaN HFETs are remarkably stable enabling operation above 600°C. The characterization results are used to extract an extended version of the Angelov model of GaN HFETs after considering the temperature as a variable parameter. A MATLAB program is used to fit the developed model with experimental I- V characteristics and a R-squared regression of 0.998 was attained over a wide temperature range extending from 25°C to 500°C. The extracted model is intended to be included in a design kit capturing the temperature effects and enabling accurate design simulations.
{"title":"Towards GaN500-based High Temperature ICs: Characterization and Modeling up to 600°C","authors":"Ahmad Hassan, Mostafa Amer, Y. Savaria, M. Sawan","doi":"10.1109/NEWCAS49341.2020.9159796","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159796","url":null,"abstract":"This paper contributes toward the implementation of Gallium Nitride (GaN)-based integrated circuits (ICs) intended for high-temperature (HT) applications. We present the implementation and HT characterization of epitaxial AlGaN/GaN Heterojunction Field Effect Transistors (HFETs). The AlGaN/GaN HFETs are remarkably stable enabling operation above 600°C. The characterization results are used to extract an extended version of the Angelov model of GaN HFETs after considering the temperature as a variable parameter. A MATLAB program is used to fit the developed model with experimental I- V characteristics and a R-squared regression of 0.998 was attained over a wide temperature range extending from 25°C to 500°C. The extracted model is intended to be included in a design kit capturing the temperature effects and enabling accurate design simulations.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114473179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159763
Amir Mirbeik-Sabzevari, L. Najafizadeh, Negar Tavassolian
This work presents three integrated pulse generators that can collectively provide a synthetic ultra-wide imaging bandwidth of 100 GHz in the millimeter-wave regime. Such a development is the first step towards the realization of a fully-integrated ultra-high-resolution imaging chip for biomedical applications. The pulse generators are designed in a Global Foundry 130-nm SiGe BiCMOS process technology and produce pulses with frequency ranges of 10-40-GHz, 40-75-GHz, and 75–110-GHz respectively. The three sub-band pulse generators possess a similar differential pulsed VCO configuration with the highest average power consumption of 40 mW.
{"title":"Synthetic Ultra-Wideband Integrated Pulse Generator for Millimeter-Wave Imaging Applications","authors":"Amir Mirbeik-Sabzevari, L. Najafizadeh, Negar Tavassolian","doi":"10.1109/newcas49341.2020.9159763","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159763","url":null,"abstract":"This work presents three integrated pulse generators that can collectively provide a synthetic ultra-wide imaging bandwidth of 100 GHz in the millimeter-wave regime. Such a development is the first step towards the realization of a fully-integrated ultra-high-resolution imaging chip for biomedical applications. The pulse generators are designed in a Global Foundry 130-nm SiGe BiCMOS process technology and produce pulses with frequency ranges of 10-40-GHz, 40-75-GHz, and 75–110-GHz respectively. The three sub-band pulse generators possess a similar differential pulsed VCO configuration with the highest average power consumption of 40 mW.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123937691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159825
Yang Ge, Ximing Fu, Yadong Yin, K. El-Sankary
This paper presents a new high speed, high conversion gain envelope detector (ED) using dynamic load (DL) and 2nd order nonlinearity maximization techniques. To enhance the conversion gain and speed of conventional ED architectures, the proposed ED uses a dynamic load (DL) technique with class-AB architecture to increase the speed and tune the output impedance dynamically. To improve nonlinearity of the ED, derivative superposition (DS) is used. By biasing the NMOS and PMOS transistors of the ED initially in different regions of operation, 2nd order derivative of transconductance (g2) is maximized which increases the 2nd order conversion gain. This configuration enables low power consumption without compromising the conversion gain. Simulation results of the proposed ED in 0.18μm CMOS technology show a high data rate of 14.5Mbps with power consumption of 1.21μW.
{"title":"Design of a high-speed RF envelope detector with dynamic load and derivative superposition techniques","authors":"Yang Ge, Ximing Fu, Yadong Yin, K. El-Sankary","doi":"10.1109/newcas49341.2020.9159825","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159825","url":null,"abstract":"This paper presents a new high speed, high conversion gain envelope detector (ED) using dynamic load (DL) and 2nd order nonlinearity maximization techniques. To enhance the conversion gain and speed of conventional ED architectures, the proposed ED uses a dynamic load (DL) technique with class-AB architecture to increase the speed and tune the output impedance dynamically. To improve nonlinearity of the ED, derivative superposition (DS) is used. By biasing the NMOS and PMOS transistors of the ED initially in different regions of operation, 2nd order derivative of transconductance (g2) is maximized which increases the 2nd order conversion gain. This configuration enables low power consumption without compromising the conversion gain. Simulation results of the proposed ED in 0.18μm CMOS technology show a high data rate of 14.5Mbps with power consumption of 1.21μW.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129136063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159787
Masashi Tawada, N. Togawa
In this study, we propose a novel stochastic number generator architecture and prove that the resulting circuit can deliver independent stochastic numbers and improve the accuracy of the calculation results obtained using some recent conventional stochastic computing-based arithmetic circuits. This study is motivated by the increasingly important role of stochastic computing in various fields, such as the digital circuit design, where the stochastic number generators are responsible for a significant share of the hardware cost.
{"title":"Designing Stochastic Number Generators Sharing a Random Number Source based on the Randomization Function","authors":"Masashi Tawada, N. Togawa","doi":"10.1109/newcas49341.2020.9159787","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159787","url":null,"abstract":"In this study, we propose a novel stochastic number generator architecture and prove that the resulting circuit can deliver independent stochastic numbers and improve the accuracy of the calculation results obtained using some recent conventional stochastic computing-based arithmetic circuits. This study is motivated by the increasingly important role of stochastic computing in various fields, such as the digital circuit design, where the stochastic number generators are responsible for a significant share of the hardware cost.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124676841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159822
Malgorzata Rechmal-Lesse, Gerald Alexander Koroa, Y. G. Adhisantoso, M. Olbrich
With the advancements in analog/mixed-signal (AMS) systems and continuously shrinking design sizes, there is an increased demand for reliable verification to ensure correct behavior. To overcome this obstacle, using formal verification is a promising option. We present a modeling system that automatically provides dependable set-valued models from circuit netlists in a form suitable for reachability analysis. Our method is based on local linearizations of the nonlinear circuit. Linearized locations are computed on-the-fly depending on which states are reachable to avoid the state-space explosion problem. The set-valued models include device parameter variations, modeling errors and uncertain input stimuli.
{"title":"Automated Model Generation Including Variations for Formal Verification of Nonlinear Analog Circuits","authors":"Malgorzata Rechmal-Lesse, Gerald Alexander Koroa, Y. G. Adhisantoso, M. Olbrich","doi":"10.1109/newcas49341.2020.9159822","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159822","url":null,"abstract":"With the advancements in analog/mixed-signal (AMS) systems and continuously shrinking design sizes, there is an increased demand for reliable verification to ensure correct behavior. To overcome this obstacle, using formal verification is a promising option. We present a modeling system that automatically provides dependable set-valued models from circuit netlists in a form suitable for reachability analysis. Our method is based on local linearizations of the nonlinear circuit. Linearized locations are computed on-the-fly depending on which states are reachable to avoid the state-space explosion problem. The set-valued models include device parameter variations, modeling errors and uncertain input stimuli.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128096622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159842
Govind Radhakrishnan, Y. Yoon, M. Sachdev
Systematic characterization is crucial for magnetic tunnel junction from initial stack development to the final mass production. It has a direct impact on the wafer turn-around time and time to market. Under these circumstances, device characterization of the magnetic tunnel junction (MTJ) stack configuration is a critical step in the product development cycle. This paper reviews the challenges and advancements in spin torque transfer (STT)-magnetoresistive random access memory (MRAM) characterization and testing over the past decade that has accelerated the fabrication process ramp-up. We also provide an overview of a design-for-testability (DFT) scheme that can be used for parametric sensitivity analysis and a built-in-self-test (BIST) scheme that utilizes the DFT for bit-cell health monitoring in STT-MRAMs. The proposed schemes open new avenues for testing and characterization.
{"title":"Accelerating STT-MRAM Ramp-up Characterization","authors":"Govind Radhakrishnan, Y. Yoon, M. Sachdev","doi":"10.1109/newcas49341.2020.9159842","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159842","url":null,"abstract":"Systematic characterization is crucial for magnetic tunnel junction from initial stack development to the final mass production. It has a direct impact on the wafer turn-around time and time to market. Under these circumstances, device characterization of the magnetic tunnel junction (MTJ) stack configuration is a critical step in the product development cycle. This paper reviews the challenges and advancements in spin torque transfer (STT)-magnetoresistive random access memory (MRAM) characterization and testing over the past decade that has accelerated the fabrication process ramp-up. We also provide an overview of a design-for-testability (DFT) scheme that can be used for parametric sensitivity analysis and a built-in-self-test (BIST) scheme that utilizes the DFT for bit-cell health monitoring in STT-MRAMs. The proposed schemes open new avenues for testing and characterization.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134032133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159776
L. G. Rocha, Morgana Macedo, Guilherme Paim, E. Costa, S. Bampi
Arithmetic operations are intrinsic to any embedded devices, and they usually have a significant impact on the circuit speed, area, and power consumption. Applications like video processing, digital signal processing, machine learning, among others, rely heavily on multipliers to execute their algorithms. Radix-2mmultipliers have been reported as one of the most power-efficient circuits. However, their architecture has not been explored nor optimized to improve the circuit quality. This work proposed two sign extension optimization techniques for these multipliers, aiming for better power efficiency and a smaller area. The baseline radix-4 $(m=2)$ multiplier and its optimized versions were synthesized in a commercial 65nm technology to evaluate their performance. Results show that the optimized versions achieve power efficiency gains from 16.4% up to 78.6%, with circuit area reduction up to 49.2%.
{"title":"Improving the Partial Product Tree Compression on Signed Radix-2m Parallel Multipliers","authors":"L. G. Rocha, Morgana Macedo, Guilherme Paim, E. Costa, S. Bampi","doi":"10.1109/newcas49341.2020.9159776","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159776","url":null,"abstract":"Arithmetic operations are intrinsic to any embedded devices, and they usually have a significant impact on the circuit speed, area, and power consumption. Applications like video processing, digital signal processing, machine learning, among others, rely heavily on multipliers to execute their algorithms. Radix-2mmultipliers have been reported as one of the most power-efficient circuits. However, their architecture has not been explored nor optimized to improve the circuit quality. This work proposed two sign extension optimization techniques for these multipliers, aiming for better power efficiency and a smaller area. The baseline radix-4 $(m=2)$ multiplier and its optimized versions were synthesized in a commercial 65nm technology to evaluate their performance. Results show that the optimized versions achieve power efficiency gains from 16.4% up to 78.6%, with circuit area reduction up to 49.2%.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131999561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159767
Meiqi Wang, Ruixin Xue, Jun Lin, Zhongfeng Wang
Training the neural networks on chip, which enables the local privacy data to be stored and processed at edge platforms, is earning vital importance with the explosive growth of Internet of Things (IoT). Although the on-chip training has been widely investigated in previous arts, there are few works related to the on-chip learning of Few-Shot Learning (FSL), an emerging topic which explores effective learning with only a small number of samples. In this paper, we explore the effectiveness of quantization, a mainstream compression method that helps reduce the memory footprint and computational resource requirements of a full-precision neural network to enable the on-chip deployment of FSL. We first perform extensive experiments on quantization of three mainstream meta-learning-based FSL networks, MAML, Meta-SGD, and Reptile, for both training and testing stages. Experimental results show that the 16-bit quantized training and testing models can be achieved with negligible losses on MAML and Meta-SGD. Then a comprehensive analysis is presented which demonstrates that a most favorable trade-off between accuracy, computational complexity, and model size can be achieved using the Meta-SGD model. This paves the way for the deployment of FSL system on the resource-constrained platforms.
{"title":"Exploring Quantization in Few-Shot Learning","authors":"Meiqi Wang, Ruixin Xue, Jun Lin, Zhongfeng Wang","doi":"10.1109/NEWCAS49341.2020.9159767","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159767","url":null,"abstract":"Training the neural networks on chip, which enables the local privacy data to be stored and processed at edge platforms, is earning vital importance with the explosive growth of Internet of Things (IoT). Although the on-chip training has been widely investigated in previous arts, there are few works related to the on-chip learning of Few-Shot Learning (FSL), an emerging topic which explores effective learning with only a small number of samples. In this paper, we explore the effectiveness of quantization, a mainstream compression method that helps reduce the memory footprint and computational resource requirements of a full-precision neural network to enable the on-chip deployment of FSL. We first perform extensive experiments on quantization of three mainstream meta-learning-based FSL networks, MAML, Meta-SGD, and Reptile, for both training and testing stages. Experimental results show that the 16-bit quantized training and testing models can be achieved with negligible losses on MAML and Meta-SGD. Then a comprehensive analysis is presented which demonstrates that a most favorable trade-off between accuracy, computational complexity, and model size can be achieved using the Meta-SGD model. This paves the way for the deployment of FSL system on the resource-constrained platforms.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124391697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159805
A. Tamakoshi, N. Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, T. Hanyu
In this paper, we introduce an energy-efficient true random number generator (TRNG) using triple read-write data-stream multiplexing combined CMOS-circuits with three-terminal magnetic tunnel junction (3T-MTJ) devices. When multiple 3T-MTJ devices are used and sequentially activated for high-speed random-number generation, the sufficient timing margin must be guaranteed for correct random-number bit stream from the 3T-MTJ devices. In the proposed TRNG, random-number bit streams are triplicated and three individual random-number bit streams are superposed among them on a single output line, which achieves high-speed and energy-efficient random number generation. We use 65 nm-CMOS/3T-MTJ design technologies, and confirm its correct operation verification by HSPICE simulation with a 3T-MTJ model. The quality of random numbers generated is verified by NIST test. As a result, the energy consumption per bit is 0.5 pJ / bit, which is about 1/10 of a conventional CMOS-based TRNG.
{"title":"Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices","authors":"A. Tamakoshi, N. Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, T. Hanyu","doi":"10.1109/newcas49341.2020.9159805","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159805","url":null,"abstract":"In this paper, we introduce an energy-efficient true random number generator (TRNG) using triple read-write data-stream multiplexing combined CMOS-circuits with three-terminal magnetic tunnel junction (3T-MTJ) devices. When multiple 3T-MTJ devices are used and sequentially activated for high-speed random-number generation, the sufficient timing margin must be guaranteed for correct random-number bit stream from the 3T-MTJ devices. In the proposed TRNG, random-number bit streams are triplicated and three individual random-number bit streams are superposed among them on a single output line, which achieves high-speed and energy-efficient random number generation. We use 65 nm-CMOS/3T-MTJ design technologies, and confirm its correct operation verification by HSPICE simulation with a 3T-MTJ model. The quality of random numbers generated is verified by NIST test. As a result, the energy consumption per bit is 0.5 pJ / bit, which is about 1/10 of a conventional CMOS-based TRNG.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121334024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159795
Nakisa Shams, A. Abbasi, F. Nabki
An RF receiver front-end using two feedforward N-path switching filters and harmonic-recombination configuration is presented. As the time-variant nature of the N-path filter introduces multiple frequency translations, third harmonic selection of the switching frequency rather than the fundamental helps to reduce the input frequency of the multiphase clock generator by a factor of three. The proposed 5.9-7.1 GHz RF receiver operates at the third harmonic of the local oscillator, thanks to the combination of an N-Path switching filter and a harmonic recombination architecture. The receiver is implemented in a 130 nm CMOS technology and operates from a 1.2 V supply. Post-layout simulation results show that, for a 6 GHz RF input, the receiver provides a harmonic rejection of 45 and 55 dB for the first and second harmonics, respectively. A noise figure of 5.5 dB at a 16 MHz baseband frequency is achieved, and an input matching of less than -15 dB is attained over the desired frequency band.
{"title":"A 6 GHz 130 nm CMOS Harmonic Recombination RF Receiver Front-End Using N-Path Filtering","authors":"Nakisa Shams, A. Abbasi, F. Nabki","doi":"10.1109/NEWCAS49341.2020.9159795","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159795","url":null,"abstract":"An RF receiver front-end using two feedforward N-path switching filters and harmonic-recombination configuration is presented. As the time-variant nature of the N-path filter introduces multiple frequency translations, third harmonic selection of the switching frequency rather than the fundamental helps to reduce the input frequency of the multiphase clock generator by a factor of three. The proposed 5.9-7.1 GHz RF receiver operates at the third harmonic of the local oscillator, thanks to the combination of an N-Path switching filter and a harmonic recombination architecture. The receiver is implemented in a 130 nm CMOS technology and operates from a 1.2 V supply. Post-layout simulation results show that, for a 6 GHz RF input, the receiver provides a harmonic rejection of 45 and 55 dB for the first and second harmonics, respectively. A noise figure of 5.5 dB at a 16 MHz baseband frequency is achieved, and an input matching of less than -15 dB is attained over the desired frequency band.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123452791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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