The ultrafast laser for material processing concentrates the pulse energy into the scale of picosecond or femtosecond temporal duration. The high peak power would induce nonlinear multiphoton fluorescence, material modification and photoablation with higher pulse energy [1]–[3]. With the increase of processing resolution and complexity, we would propose the noninvasive inspection method by integrating with multiphoton excited fluorescence microscopy (MPEFM) to directly monitor the processed structure in specimen for verification and analysis [1]. In this paper, we would show the setup of FPGA-based MPEFM and adopt the single photon counting (SPC) technique for high signal-to-noise (SNR) images. The image spatial resolution is submicron level. To the need of the high bandwidth electrical components and applications in industry, companies are developing different kinds of composite materials and insulators together with the technology of different kinds of laser processing methods and protocols including direct writing, drilling, and modification with etching-assistance. Glass and polyimide (PI) are important materials for the insulation layer in PCB (printed circuit board) design and the narrow electrical routing structures are especially required to be confirmed after processing [4], [5]. We have shown the MPEFM can detect the axial-resolved images of the laser modified surface on the silicon glass and the laser-cut structure on the PI film without damaging the specimen. The mechanism shows the potential for the rapid 3D inspection of the laser processed specimen.
{"title":"Real time analysis for Laser drilling vias of 5G Material with Multiphoton microscopy","authors":"Jyun-Zong Yu, Hsin-Yu Chang, Chien-Jung Huang, Yu-Chung Lin, Chia-Yuan Chang","doi":"10.1109/IMPACT56280.2022.9966642","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966642","url":null,"abstract":"The ultrafast laser for material processing concentrates the pulse energy into the scale of picosecond or femtosecond temporal duration. The high peak power would induce nonlinear multiphoton fluorescence, material modification and photoablation with higher pulse energy [1]–[3]. With the increase of processing resolution and complexity, we would propose the noninvasive inspection method by integrating with multiphoton excited fluorescence microscopy (MPEFM) to directly monitor the processed structure in specimen for verification and analysis [1]. In this paper, we would show the setup of FPGA-based MPEFM and adopt the single photon counting (SPC) technique for high signal-to-noise (SNR) images. The image spatial resolution is submicron level. To the need of the high bandwidth electrical components and applications in industry, companies are developing different kinds of composite materials and insulators together with the technology of different kinds of laser processing methods and protocols including direct writing, drilling, and modification with etching-assistance. Glass and polyimide (PI) are important materials for the insulation layer in PCB (printed circuit board) design and the narrow electrical routing structures are especially required to be confirmed after processing [4], [5]. We have shown the MPEFM can detect the axial-resolved images of the laser modified surface on the silicon glass and the laser-cut structure on the PI film without damaging the specimen. The mechanism shows the potential for the rapid 3D inspection of the laser processed specimen.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90308568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966633
Chengyong Chen, Liang-Yih Hung, Yueh Yang Lee, Yu-Po Wang
High performance computing (HPC) products market is growing to meet current and future demands in business, government, engineering, and science. HPC system can process big data and perform complex calculation at high speeds, where the system also generates a lot of heat continuously. The accumulated heat needs to be managed to avoid affecting the performance and lifetime of HPC system. Therefore, a key design and development of HPC products is to achieve high thermal dissipation in electronic devices. The application of thermal interface materials (TIMs) has been a promising thermal dissipation solution for electronic devices. However, the thermal conductivities of current silicone-based TIMs have been insufficient for future products. Indium is a potential candidate for high heat dissipation needs, because the thermal conductivity of pure indium is around 86 W/mK, which is higher than most silicone-based TIMs. When indium has been applied as a metallic TIM and jointed with the metal of surface finish, there is an intermetallic compound (IMC) reaction at the interface of indium joint. The phase and microstructure of IMC depend on the conditions of thermal treatments and the type of surface finish. The interfacial condition of indium joint is the key to heat dissipation performance. Therefore, the interfacial mechanism of indium joints have been investigated by applying different surface finishes and various heat treatments in this study.In this paper, the interfacial reactions of indium jointed with different surface finishes (Au/Ni(V) and Au/Ni) have been investigated, respectively. For studying the interfacial microstructure evolution of the indium joints, they have been treated with different thermal treatments, including reflow process (with 245°C peak temperature) and high temperature storage tests (aging at 100°C, 125°C, and 150°C for 250~1000 hours). The interfacial morphologies of indium joint and the growth behaviors of IMC have been observed, and the interfacial IMC has been identified as Ni28 In72 phase. For Au/Ni(V) surface finish, there is rock shaped IMC grains on the surface of Ni(V) layer, and the grain size of IMC increases with the increase of the reflow cycle. In Ni(V) layer, there is a significant In/Ni inter-diffusion reaction after different thermal treatments. For Au/Ni surface finish, the thickness of IMC increases with the increase of aging time and temperature, and the growth rate of IMC increases with the elevating storage temperature.
{"title":"Interfacial Microstructure Evolution of Indium Jointed with Different Surface Finishes after Thermal Treatments","authors":"Chengyong Chen, Liang-Yih Hung, Yueh Yang Lee, Yu-Po Wang","doi":"10.1109/IMPACT56280.2022.9966633","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966633","url":null,"abstract":"High performance computing (HPC) products market is growing to meet current and future demands in business, government, engineering, and science. HPC system can process big data and perform complex calculation at high speeds, where the system also generates a lot of heat continuously. The accumulated heat needs to be managed to avoid affecting the performance and lifetime of HPC system. Therefore, a key design and development of HPC products is to achieve high thermal dissipation in electronic devices. The application of thermal interface materials (TIMs) has been a promising thermal dissipation solution for electronic devices. However, the thermal conductivities of current silicone-based TIMs have been insufficient for future products. Indium is a potential candidate for high heat dissipation needs, because the thermal conductivity of pure indium is around 86 W/mK, which is higher than most silicone-based TIMs. When indium has been applied as a metallic TIM and jointed with the metal of surface finish, there is an intermetallic compound (IMC) reaction at the interface of indium joint. The phase and microstructure of IMC depend on the conditions of thermal treatments and the type of surface finish. The interfacial condition of indium joint is the key to heat dissipation performance. Therefore, the interfacial mechanism of indium joints have been investigated by applying different surface finishes and various heat treatments in this study.In this paper, the interfacial reactions of indium jointed with different surface finishes (Au/Ni(V) and Au/Ni) have been investigated, respectively. For studying the interfacial microstructure evolution of the indium joints, they have been treated with different thermal treatments, including reflow process (with 245°C peak temperature) and high temperature storage tests (aging at 100°C, 125°C, and 150°C for 250~1000 hours). The interfacial morphologies of indium joint and the growth behaviors of IMC have been observed, and the interfacial IMC has been identified as Ni28 In72 phase. For Au/Ni(V) surface finish, there is rock shaped IMC grains on the surface of Ni(V) layer, and the grain size of IMC increases with the increase of the reflow cycle. In Ni(V) layer, there is a significant In/Ni inter-diffusion reaction after different thermal treatments. For Au/Ni surface finish, the thickness of IMC increases with the increase of aging time and temperature, and the growth rate of IMC increases with the elevating storage temperature.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"18 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81486882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966675
B. Schafsteller, Bernhard Schachtner, Anja Streek, Kenneth Lee, H. Mertens, G. Ramos
Immersion tin is a final finish which is widely used in the printed circuit board (PCB) industry. It provides a cost competitive surface protection with excellent corrosion resistance and has the capability for multiple reflow soldering. The tin is deposited on copper by immersion reaction with a typical layer thickness of 0.8 – 1.2 μm. On top of the tin layer an oxide layer is formed, which can influence the properties of the final finish. During the assembly process, an intermetallic compound (IMC) grows connecting the copper substrate and the tin of the solder alloy. The growth of the IMC is a complex function of temp and time. The IMC formation and well distributed pure tin remnants are key factors to obtain a reliable solder joint. With increased aging or reflow of the immersion tin deposit, the role of the tin oxide layer becomes of particular interest influencing properties of solder and immersion tin in liquidus process at reflow step. Due to the IMC formation, the tin layer is facing increasing internal stress which is potentially released via the oxide covered surface. The quality and thickness of the tin oxide layer impacts the solder wetting performance of the final finish, the risk of whisker formation and in particular the stability and appearance of the layer after reflow aging. In this paper, an introduction on typical failure mechanisms and root causes for solder wetting defects of immersion tin will be given. Such defects can become e.g. visible by solder dewetting in certain areas of the soldered pads or by partially shiny appearance of the tin surface after reflow cycles. The mechanisms introduced in this paper are supported by correlating tests to identify possible root causes for the solder wetting defects. Various methods are presented which allow the determination of the tin oxide layer thickness. Different factors are investigated for their impact on the tin oxide layer formation, and various approaches are studied to modify the thickness of the oxide layer. Based on the test results, the properties of the tin oxide layer could be identified as critical parameters for the immersion tin layer performance. The application of a dedicated post-treatment solution can modify the tin oxide layer and improve the performance of the immersion tin deposit regarding appearance and solderability. This is confirmed by optical inspection, different types of solderability tests and whisker evaluation.
{"title":"The impact of Sn-Oxide on the solder wetting of immersion tin and how to overcome possible solderability defects to ensure constant solder wetting performance","authors":"B. Schafsteller, Bernhard Schachtner, Anja Streek, Kenneth Lee, H. Mertens, G. Ramos","doi":"10.1109/IMPACT56280.2022.9966675","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966675","url":null,"abstract":"Immersion tin is a final finish which is widely used in the printed circuit board (PCB) industry. It provides a cost competitive surface protection with excellent corrosion resistance and has the capability for multiple reflow soldering. The tin is deposited on copper by immersion reaction with a typical layer thickness of 0.8 – 1.2 μm. On top of the tin layer an oxide layer is formed, which can influence the properties of the final finish. During the assembly process, an intermetallic compound (IMC) grows connecting the copper substrate and the tin of the solder alloy. The growth of the IMC is a complex function of temp and time. The IMC formation and well distributed pure tin remnants are key factors to obtain a reliable solder joint. With increased aging or reflow of the immersion tin deposit, the role of the tin oxide layer becomes of particular interest influencing properties of solder and immersion tin in liquidus process at reflow step. Due to the IMC formation, the tin layer is facing increasing internal stress which is potentially released via the oxide covered surface. The quality and thickness of the tin oxide layer impacts the solder wetting performance of the final finish, the risk of whisker formation and in particular the stability and appearance of the layer after reflow aging. In this paper, an introduction on typical failure mechanisms and root causes for solder wetting defects of immersion tin will be given. Such defects can become e.g. visible by solder dewetting in certain areas of the soldered pads or by partially shiny appearance of the tin surface after reflow cycles. The mechanisms introduced in this paper are supported by correlating tests to identify possible root causes for the solder wetting defects. Various methods are presented which allow the determination of the tin oxide layer thickness. Different factors are investigated for their impact on the tin oxide layer formation, and various approaches are studied to modify the thickness of the oxide layer. Based on the test results, the properties of the tin oxide layer could be identified as critical parameters for the immersion tin layer performance. The application of a dedicated post-treatment solution can modify the tin oxide layer and improve the performance of the immersion tin deposit regarding appearance and solderability. This is confirmed by optical inspection, different types of solderability tests and whisker evaluation.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"62 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85783651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966667
Dem Lee, Jeffiey Lee, Ricky S. W. Lee, Calvin Lee
The proliferation of Artificial Intelligence (AI), big data, 5G, electric vehicles, Internet of Things (IoT), edge computing, High Performance Computing (HPC) and Electric Vehicle (EV) in recent years has necessitated the increased use of electronics. Therefore, the hardware reliability of electronics has received more attention in the industry. With prevalent environmental pollution, air quality will also directly or indirectly influence the life of electronics in indoor and outdoor applications. In general, the hardware reliability of electronics can be easily affected by corrosive gases, moisture, salts, contaminants and particulate matter, especially in outdoor environments with high sulfur-bearing gaseous contamination. Therefore, next generation electronics required not only high performance but also robustness against harsher environments. A guideline from the International Society for Automation (ISA) standard 71.04-2013 was used to classify the measured corrosion thickness of airbome contaminants into the various severity level rankings by using pure copper and silver coupon exposure. However, some end-customers have asked their Original Design Manufacturers (ODMs) provide the product for passing G2/G3 severity level compliant to 3 years, 5 years, even 10 years through accelerated corrosion methodologies in recent years. Therefore, more and more ODMs have adopted the conformal coating solution. Conformal coating is a popular solution which can protect the board and component to prevent the sulfur corrosion occurrence, especially in edge computing and outdoor infrastructure. In this research, Flower of Sulfur (FoS) testing method was adopted to validate the anti-corrosion capability of bare copper Printed Circuit Board (PCB) with different conformal coating materials, including typical silicon-based and electronic grade fluorine-based conformal coating, and also benchmarked them against the bare copper PCB without conformal coating. Besides, this corrosion test can be satisfied ANSI/ISA G3 severity level compliant to 5 years exposure. Several analytical methods were used in this research, including, Optical Microscope (OM) Inspection, Coulometric Reduction (CR), Scanning Electron Microscopy (SEM) and Energy-Dispersive X-ray spectroscopy (EDX). Finally, we found that fluorine-based conformal coating from 3MTMNovecTM has robust corrosion resistance that can enhance the specific protectively of outdoor electronics application.
{"title":"A Fluorinated Electronic Grade Coating which can help to Pass ANSI/ISA G3 Corrosion Test for Protecting Outdoor Electronics","authors":"Dem Lee, Jeffiey Lee, Ricky S. W. Lee, Calvin Lee","doi":"10.1109/IMPACT56280.2022.9966667","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966667","url":null,"abstract":"The proliferation of Artificial Intelligence (AI), big data, 5G, electric vehicles, Internet of Things (IoT), edge computing, High Performance Computing (HPC) and Electric Vehicle (EV) in recent years has necessitated the increased use of electronics. Therefore, the hardware reliability of electronics has received more attention in the industry. With prevalent environmental pollution, air quality will also directly or indirectly influence the life of electronics in indoor and outdoor applications. In general, the hardware reliability of electronics can be easily affected by corrosive gases, moisture, salts, contaminants and particulate matter, especially in outdoor environments with high sulfur-bearing gaseous contamination. Therefore, next generation electronics required not only high performance but also robustness against harsher environments. A guideline from the International Society for Automation (ISA) standard 71.04-2013 was used to classify the measured corrosion thickness of airbome contaminants into the various severity level rankings by using pure copper and silver coupon exposure. However, some end-customers have asked their Original Design Manufacturers (ODMs) provide the product for passing G2/G3 severity level compliant to 3 years, 5 years, even 10 years through accelerated corrosion methodologies in recent years. Therefore, more and more ODMs have adopted the conformal coating solution. Conformal coating is a popular solution which can protect the board and component to prevent the sulfur corrosion occurrence, especially in edge computing and outdoor infrastructure. In this research, Flower of Sulfur (FoS) testing method was adopted to validate the anti-corrosion capability of bare copper Printed Circuit Board (PCB) with different conformal coating materials, including typical silicon-based and electronic grade fluorine-based conformal coating, and also benchmarked them against the bare copper PCB without conformal coating. Besides, this corrosion test can be satisfied ANSI/ISA G3 severity level compliant to 5 years exposure. Several analytical methods were used in this research, including, Optical Microscope (OM) Inspection, Coulometric Reduction (CR), Scanning Electron Microscopy (SEM) and Energy-Dispersive X-ray spectroscopy (EDX). Finally, we found that fluorine-based conformal coating from 3MTMNovecTM has robust corrosion resistance that can enhance the specific protectively of outdoor electronics application.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"25 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81528076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966671
Ander Hsieh, Mike Huang, Johnny Ch Chen, Michael Yeh
A practical case related to package failure from field was presented in this paper, traditional equipment (cross-section, oven, SEM) was used to reveal 2 of mixed factors that may trigger failure of package. In the final conclusion, we considered the failure was strongly related to crack between gold wire ball & pad and concave molding of package when using 1~1.5 years from field. Another purpose of this paper is that author would like to draw industry’s attention regarding to quality standard of wire bonding. In current standard only stated the pull strength of wire bonding, but it did not control the structure quality of wire bonding, bad connection of electrical property may result in temporal failure of electronic product and not easy to find out the root cause of failure, this situation may influence different level of product, e.g. military, satellite, medical instrument, air industry, server, personal computer.
{"title":"Failure Analysis for Package of Gold Wire Bonding from Practical Case","authors":"Ander Hsieh, Mike Huang, Johnny Ch Chen, Michael Yeh","doi":"10.1109/IMPACT56280.2022.9966671","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966671","url":null,"abstract":"A practical case related to package failure from field was presented in this paper, traditional equipment (cross-section, oven, SEM) was used to reveal 2 of mixed factors that may trigger failure of package. In the final conclusion, we considered the failure was strongly related to crack between gold wire ball & pad and concave molding of package when using 1~1.5 years from field. Another purpose of this paper is that author would like to draw industry’s attention regarding to quality standard of wire bonding. In current standard only stated the pull strength of wire bonding, but it did not control the structure quality of wire bonding, bad connection of electrical property may result in temporal failure of electronic product and not easy to find out the root cause of failure, this situation may influence different level of product, e.g. military, satellite, medical instrument, air industry, server, personal computer.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"138 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80527037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966690
Jack Huang
Laser drilling is widely employed for PCB/FPCB production, especially for ABF/RDL substrates used for 5G telecommunication. Compared with the mechanical drilling which is usually used for the via diameter over 200um, laser drilling can fulfill the smaller via diameter amid 15um and 200um. Plasma descum and wet cleaning are the common post-processes after the laser drilling to obtain the better via quality by removing drilling residue and debris. But traditional nano-second/pico-second lasers used in laser drilling may not drill well on the protective layer or redistribution layer(RDL) of the wafer-level chip-scale-package(WLCSP). Challenges including: (1) Bottom metal layer damaged or insulation layer peeling from the metal layer attributed to the severe heat-affected-zone(HAZ). (2) Via diameter smaller than 30um is unachievable. (3) Positional error below 5um can’t be secured while drilling at the faster speed. This paper will demonstrate using the femto-second laser with the inherent feature of cold ablation to drill vias on the ABF layer and then carrying out the post-treatment of plasma descum to fulfill the requirements of higher taper angle and faster throughput. Advantages include: (1) Flesible drilling capability, via diameter is programmable in the range of 15um to 200um. (2) Undamaged and residue-free on the bottom metal layer. (3) Smooth via sidewall. (4) Continuous drilling can reach the speed of 3000 via/sec.
{"title":"Laser Drilling & Plasma Descum Employed In The Process of Wafer-Level Chip Scale Package(WLCSP)","authors":"Jack Huang","doi":"10.1109/IMPACT56280.2022.9966690","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966690","url":null,"abstract":"Laser drilling is widely employed for PCB/FPCB production, especially for ABF/RDL substrates used for 5G telecommunication. Compared with the mechanical drilling which is usually used for the via diameter over 200um, laser drilling can fulfill the smaller via diameter amid 15um and 200um. Plasma descum and wet cleaning are the common post-processes after the laser drilling to obtain the better via quality by removing drilling residue and debris. But traditional nano-second/pico-second lasers used in laser drilling may not drill well on the protective layer or redistribution layer(RDL) of the wafer-level chip-scale-package(WLCSP). Challenges including: (1) Bottom metal layer damaged or insulation layer peeling from the metal layer attributed to the severe heat-affected-zone(HAZ). (2) Via diameter smaller than 30um is unachievable. (3) Positional error below 5um can’t be secured while drilling at the faster speed. This paper will demonstrate using the femto-second laser with the inherent feature of cold ablation to drill vias on the ABF layer and then carrying out the post-treatment of plasma descum to fulfill the requirements of higher taper angle and faster throughput. Advantages include: (1) Flesible drilling capability, via diameter is programmable in the range of 15um to 200um. (2) Undamaged and residue-free on the bottom metal layer. (3) Smooth via sidewall. (4) Continuous drilling can reach the speed of 3000 via/sec.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"88 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78966435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966707
K. Yong, Chin Theng Lim, Wei Khoon Teng
Understanding of how a chip power performance is impacted by the IR drop of a power delivery network (PDN) enables system operating conditions to be optimized. It allows IR drop impacts to a silicon chip to be identified and fixed early during design phases. Conventionally, the static and dynamic IR drop analysis for a silicon chip only considers the impact of silicon level power switching gates and metal routing. Such an analysis approach assumes the power supply from voltage regulator module (VRM) to silicon bumps is noise-free and steady, without taking the impacts of system level components into considerations [1]–[4]. In our opinions, such an analysis approach is unduly optimistic and causes IR drop signoff to be less reliable. This paper uses a RISC-V CPU as a case study to illustrate the importance of the external components in an IR drop analysis. The characterization results show that an IR drop of 100mV caused by PDN impedance can result in the targeted clock speed to be reduced by up to 500MHz, which is equivalent to a 50% performance degradation for a 1GHz CPU and is significant. Then, the impact of system level IR drop caused by package, board and VRM to a silicon chip power performance is further shown. A comparison between the conventional Redhawk chip IR drop simulation and our approach is presented. Our modelling methodology, which uses a system-level distributed PDN to increase IR drop analysis accuracy has also been described in detail. It is shown that external factors including package, board and VRM can induce up to 5.8% additional IR drop, or, 0. 058V for a 1V power supply. This may cause the targeted clock speed to be reduced by up to 250MHz in the actual silicon. It is demonstrated that the intrinsic resistance and impedance of PDN if not being managed properly could negate the power delivery efficiency and impacting silicon performance.
{"title":"System Level IR Drop Impact on Chip Power Performance Signoff for RISC-V System on Chip","authors":"K. Yong, Chin Theng Lim, Wei Khoon Teng","doi":"10.1109/IMPACT56280.2022.9966707","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966707","url":null,"abstract":"Understanding of how a chip power performance is impacted by the IR drop of a power delivery network (PDN) enables system operating conditions to be optimized. It allows IR drop impacts to a silicon chip to be identified and fixed early during design phases. Conventionally, the static and dynamic IR drop analysis for a silicon chip only considers the impact of silicon level power switching gates and metal routing. Such an analysis approach assumes the power supply from voltage regulator module (VRM) to silicon bumps is noise-free and steady, without taking the impacts of system level components into considerations [1]–[4]. In our opinions, such an analysis approach is unduly optimistic and causes IR drop signoff to be less reliable. This paper uses a RISC-V CPU as a case study to illustrate the importance of the external components in an IR drop analysis. The characterization results show that an IR drop of 100mV caused by PDN impedance can result in the targeted clock speed to be reduced by up to 500MHz, which is equivalent to a 50% performance degradation for a 1GHz CPU and is significant. Then, the impact of system level IR drop caused by package, board and VRM to a silicon chip power performance is further shown. A comparison between the conventional Redhawk chip IR drop simulation and our approach is presented. Our modelling methodology, which uses a system-level distributed PDN to increase IR drop analysis accuracy has also been described in detail. It is shown that external factors including package, board and VRM can induce up to 5.8% additional IR drop, or, 0. 058V for a 1V power supply. This may cause the targeted clock speed to be reduced by up to 250MHz in the actual silicon. It is demonstrated that the intrinsic resistance and impedance of PDN if not being managed properly could negate the power delivery efficiency and impacting silicon performance.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"212 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75968164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966681
Chung-Yu Ke, Liang-Pin Chen
With the development of smart phones, the developing direction of Application Chip (AP) is to be thinner and lighter. FOPOP (Fan-Out Package On Package) is the mainstream packaging mode to cope with the ever-increasing layout density [1] [2]. In the mobile phone market where a hundred schools of thought contend, to cope with mobile phone APs of different brands and performances, the structure of without memory stacking has gradually become the mainstream of the FOPOP structure. The FOPOP without memory stacking, in order to complete the memory stacking of different brands and the application of mobile phones at high frequencies, there are strict requirements on the material of the connection surface. Among them, Build-up Film, due to its low dielectric constant (Dk), low dielectric loss and low coefficient of thermal expansion (CTE) at high frequencies, can solve problems such as transmission loss and package warpage [3] [4]. In order to achieve memory stacking, we used the laser drilling technology on the Build-up Film to reveal the pattern that connected to the Memory, and fill the solder into the drill hole in advance, which is convenient for the end product to stack the Memory. The shift of the laser drilling will directly affect the difficulty of stacking the Memory, which will eventually lead to the opening of the circuit. Hence, the shift of the laser drilling is one of the necessary inspection items. However, Build-up Film is a non-traditional transparent film, by laser microscope, we cannot know the position of the pattern under the Build-up Film, and cannot measure the shift. The Infrared (IR) Microscope is generally used to detect backside and side wall cracks in silicon die. The purpose of detection is achieved through the characteristics of IR long wavelengths that easily penetrate silicon. Relatively, the red light laser microscope that most commonly used in the production line cannot penetrate the Build-up Film due to the short wavelength of red light. Hence, we use long-wavelength IR to penetrate the Build-up Film, and use a correction sheet to correct the length to ensure the accuracy of the length measurement. The measurement of laser drilling shift is achieved, to ensure the quality of laser drilling. Finally, we confirmed that the error between IR Microscope measurement result and cross-section & SEM is within 2.14μm, so IR Microscope is a feasible measurement tool for laser drilling shift of Build-up Film.
随着智能手机的发展，应用芯片(AP)的发展方向是更薄、更轻。FOPOP (Fan-Out Package On Package)是应对日益增长的布局密度[1]b[2]的主流封装模式。在百家争抢的手机市场，为了应对不同品牌、不同性能的手机ap，无内存堆叠的结构逐渐成为FOPOP结构的主流。没有内存堆叠的FOPOP，为了完成不同品牌的内存堆叠和手机在高频下的应用，对连接面的材质有严格的要求。其中，积聚膜由于其在高频下具有低介电常数(Dk)、低介电损耗和低热膨胀系数(CTE)，可以解决传输损耗和封装翘曲[3][4]等问题。为了实现存储器的堆叠，我们在堆积膜上使用激光钻孔技术，将连接到存储器的图案显示出来，并提前将焊料填充到钻孔中，方便最终产品堆叠存储器。激光打孔的移位会直接影响Memory的堆叠难度，最终导致电路的打开。因此，激光打孔的位移是必要的检测项目之一。然而，堆积膜是一种非传统的透明薄膜，通过激光显微镜，我们无法知道图案在堆积膜下的位置，也无法测量位移。红外显微镜通常用于检测硅模具的背面和侧壁裂纹。探测的目的是通过红外长波容易穿透硅的特性来实现的。相对而言，生产线上最常用的红光激光显微镜由于红光波长短，无法穿透堆积膜。因此，我们使用长波长的IR来穿透堆积膜，并使用校正片来校正长度，以确保长度测量的准确性。实现了激光打孔位移的测量，保证了激光打孔质量。最后，我们证实了红外显微镜测量结果与横截面和扫描电镜的误差在2.14μm以内，因此红外显微镜是激光钻削堆积膜位移的一种可行的测量工具。
{"title":"Measurement of Laser Drilling Shift for Opaque Build-up Film by Infrared Microscope","authors":"Chung-Yu Ke, Liang-Pin Chen","doi":"10.1109/IMPACT56280.2022.9966681","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966681","url":null,"abstract":"With the development of smart phones, the developing direction of Application Chip (AP) is to be thinner and lighter. FOPOP (Fan-Out Package On Package) is the mainstream packaging mode to cope with the ever-increasing layout density [1] [2]. In the mobile phone market where a hundred schools of thought contend, to cope with mobile phone APs of different brands and performances, the structure of without memory stacking has gradually become the mainstream of the FOPOP structure. The FOPOP without memory stacking, in order to complete the memory stacking of different brands and the application of mobile phones at high frequencies, there are strict requirements on the material of the connection surface. Among them, Build-up Film, due to its low dielectric constant (Dk), low dielectric loss and low coefficient of thermal expansion (CTE) at high frequencies, can solve problems such as transmission loss and package warpage [3] [4]. In order to achieve memory stacking, we used the laser drilling technology on the Build-up Film to reveal the pattern that connected to the Memory, and fill the solder into the drill hole in advance, which is convenient for the end product to stack the Memory. The shift of the laser drilling will directly affect the difficulty of stacking the Memory, which will eventually lead to the opening of the circuit. Hence, the shift of the laser drilling is one of the necessary inspection items. However, Build-up Film is a non-traditional transparent film, by laser microscope, we cannot know the position of the pattern under the Build-up Film, and cannot measure the shift. The Infrared (IR) Microscope is generally used to detect backside and side wall cracks in silicon die. The purpose of detection is achieved through the characteristics of IR long wavelengths that easily penetrate silicon. Relatively, the red light laser microscope that most commonly used in the production line cannot penetrate the Build-up Film due to the short wavelength of red light. Hence, we use long-wavelength IR to penetrate the Build-up Film, and use a correction sheet to correct the length to ensure the accuracy of the length measurement. The measurement of laser drilling shift is achieved, to ensure the quality of laser drilling. Finally, we confirmed that the error between IR Microscope measurement result and cross-section & SEM is within 2.14μm, so IR Microscope is a feasible measurement tool for laser drilling shift of Build-up Film.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"51 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77386631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For the high reliability and harsh environment applications such as automotive grade MCM (multi-chip modules) or SiP (System in Package), normally requires under-fill to achieve the needed thermal cycles, mechanical shock and vibration reliability. And, these high reliability applications often incorporate high process cost, spending on module ilux cleaning, baking, plasma treatment even under-fill capillary time consuming. Despite of that, the extra environmental regulation compliance issues of energy saving and wastes disposal also challenge the manufacturer to consider more cost effective and environment friendly manufacturing processes with moderate reliability to meet modern automotive industrial requirements. This study focus on non-cleaning side-fill and corner / edge bond (hereafter be cited within the text as CEB) reinforcement techniques including material selection, verification, and dispensing process design to improve the solder-joint reliability of BGAs or BTC in MCM or SiP to meet the minimum automotive industrial standards (AECQ104 Failure Mechanism Based Stress Test Qualification for Multichip Modules in Automotive Applications). The reliability testing protocol used here, included pre-conditioning(3X multi-reflow) and thermal cycling ($-40^{circ}C-85^{circ}C$). Four adhesive materials (commercially available) were studied with test vehicles including wafer glass attachment and BGA packages with plans to expand the study on WLCSP BGAs. For side-fill and CEB processing, establishing side-fill adhesion and edge bond that maximizes adhesion/bond area with proper fillet height without encapsulating the solder balls is key success to prevent the process quality issues as well as to reliability improvements.
{"title":"Effects of Corner/Edge Bond and Side-fill for Automotive MCM Applications","authors":"Kuo-Hua Heish, Chao-Chieh Chan, Ming-Jhe Wu, Chih-Yang Weng, Yu-Da Dong, Chun-Jen Cheng","doi":"10.1109/IMPACT56280.2022.9966634","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966634","url":null,"abstract":"For the high reliability and harsh environment applications such as automotive grade MCM (multi-chip modules) or SiP (System in Package), normally requires under-fill to achieve the needed thermal cycles, mechanical shock and vibration reliability. And, these high reliability applications often incorporate high process cost, spending on module ilux cleaning, baking, plasma treatment even under-fill capillary time consuming. Despite of that, the extra environmental regulation compliance issues of energy saving and wastes disposal also challenge the manufacturer to consider more cost effective and environment friendly manufacturing processes with moderate reliability to meet modern automotive industrial requirements. This study focus on non-cleaning side-fill and corner / edge bond (hereafter be cited within the text as CEB) reinforcement techniques including material selection, verification, and dispensing process design to improve the solder-joint reliability of BGAs or BTC in MCM or SiP to meet the minimum automotive industrial standards (AECQ104 Failure Mechanism Based Stress Test Qualification for Multichip Modules in Automotive Applications). The reliability testing protocol used here, included pre-conditioning(3X multi-reflow) and thermal cycling ($-40^{circ}C-85^{circ}C$). Four adhesive materials (commercially available) were studied with test vehicles including wafer glass attachment and BGA packages with plans to expand the study on WLCSP BGAs. For side-fill and CEB processing, establishing side-fill adhesion and edge bond that maximizes adhesion/bond area with proper fillet height without encapsulating the solder balls is key success to prevent the process quality issues as well as to reliability improvements.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"45 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75702978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966727
Chao-Ting Chu, Z. Lin, Shih-Ting Dai
This paper proposes solar cell boost converter with adaptive PD controller. Solar power generation systems use sunlight to generate electricity mainly. The same technology as integrated circuits that collect electric energy through solar panel to achieve boost converter. In this paper, we proposed an adaptive PD controller adjusts adaptive law real time that according to load changes and light changes. The adaptive laws used Lyaponuv function to derivation that ensure the convergence stable. Experimental results are shown output voltage stable when input voltage and load change. Therefore, the adaptive laws adjusted real time to achieve the robustness in the system.
{"title":"Solar Cell Boost Converter with Adaptive PD Controller","authors":"Chao-Ting Chu, Z. Lin, Shih-Ting Dai","doi":"10.1109/IMPACT56280.2022.9966727","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966727","url":null,"abstract":"This paper proposes solar cell boost converter with adaptive PD controller. Solar power generation systems use sunlight to generate electricity mainly. The same technology as integrated circuits that collect electric energy through solar panel to achieve boost converter. In this paper, we proposed an adaptive PD controller adjusts adaptive law real time that according to load changes and light changes. The adaptive laws used Lyaponuv function to derivation that ensure the convergence stable. Experimental results are shown output voltage stable when input voltage and load change. Therefore, the adaptive laws adjusted real time to achieve the robustness in the system.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"41 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88831615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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