Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966719
Mak Hoi Chau, Chung-Long Pan, Yu-Jung Huang
The main development trend of modern microelectronics is to continuously reduce product mass and dimension, and also increase their performance and reliability. The wide application of multichiplet architecture in high-performance computing clusters has aroused great interest. The multi-chiplet placement can influence the signal transmission behavior in a 3D integration architecture. Interchip communication has remained a major design factor due to the diverse traffic requirements in heterogeneous multi-chiplet systems. In general, to exploit the capabilities of a multi-chiplet architecture without I/O bottlenecks, dense vertical connections in stacked chips become of increasing importance in modern semiconductor technology. Consider a heterogeneous or homogeneous multi-chiplet architecture with a dense vertical connection system that gains a performance per energy benefit from fast state migration between these chiplets. In this paper, we study the effects of signal transmission on different chiplet placement designs, in which wirelessly connected multi-chiplets modules are proposed. The inter-chip wireless heterogeneous or homogeneous multi-chiplet architecture is modeled using a high-frequency structure simulator, in particular, the placement effect of the side differential vertical signal transmission is analyzed.
{"title":"Multi-Chiplet Placement Design for 3D Integration","authors":"Mak Hoi Chau, Chung-Long Pan, Yu-Jung Huang","doi":"10.1109/IMPACT56280.2022.9966719","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966719","url":null,"abstract":"The main development trend of modern microelectronics is to continuously reduce product mass and dimension, and also increase their performance and reliability. The wide application of multichiplet architecture in high-performance computing clusters has aroused great interest. The multi-chiplet placement can influence the signal transmission behavior in a 3D integration architecture. Interchip communication has remained a major design factor due to the diverse traffic requirements in heterogeneous multi-chiplet systems. In general, to exploit the capabilities of a multi-chiplet architecture without I/O bottlenecks, dense vertical connections in stacked chips become of increasing importance in modern semiconductor technology. Consider a heterogeneous or homogeneous multi-chiplet architecture with a dense vertical connection system that gains a performance per energy benefit from fast state migration between these chiplets. In this paper, we study the effects of signal transmission on different chiplet placement designs, in which wirelessly connected multi-chiplets modules are proposed. The inter-chip wireless heterogeneous or homogeneous multi-chiplet architecture is modeled using a high-frequency structure simulator, in particular, the placement effect of the side differential vertical signal transmission is analyzed.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78764404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966720
J.Y. Wang, Cadmus C.A. Yuan, K. Chiang
This research establishes a set of transient finite element models to represent the mechanical impacts during the w/b process [1]. Moreover, a finite element model of the BEOL structure, which consisted of 7 layers of copper metal stacks and an aluminum pad to represent the current frequent-used technology, is established to investigate the stress pattern. The results show that both the Cu/low-k design and the w/b process parameters, including the free-air ball (FAB) size and w/b capillary, influence the maximum stress of the Cu/low-k structure. It is suggested that the w/b process of Cu/low-k structure should be precisely controlled, compared to the conventional w/b process of the Al/SiO4 structure, to maintain the low stress level of the Cu/low-k structure.
{"title":"Wire Boning Process Failure Risk Estimation of the Cu/low-k Structure using the Transient Finite Element","authors":"J.Y. Wang, Cadmus C.A. Yuan, K. Chiang","doi":"10.1109/IMPACT56280.2022.9966720","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966720","url":null,"abstract":"This research establishes a set of transient finite element models to represent the mechanical impacts during the w/b process [1]. Moreover, a finite element model of the BEOL structure, which consisted of 7 layers of copper metal stacks and an aluminum pad to represent the current frequent-used technology, is established to investigate the stress pattern. The results show that both the Cu/low-k design and the w/b process parameters, including the free-air ball (FAB) size and w/b capillary, influence the maximum stress of the Cu/low-k structure. It is suggested that the w/b process of Cu/low-k structure should be precisely controlled, compared to the conventional w/b process of the Al/SiO4 structure, to maintain the low stress level of the Cu/low-k structure.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"26 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87641675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966686
P. Y. Sun, Yuan Cadmus C.A., K. Chiang
This research establishes a set of transient finite element models to represent the mechanical impacts during the w/b process. Moreover, a finite element model of the BEOL structure, which consisted of 7 layers of copper metal stacks and an aluminum pad to represent the current frequent-used technology, is established to investigate the stress pattern. The results show that the Cu/low-k system produces larger stress levels in the column structure and induces a larger amount of deformation than the Al/TEOS system, and different annealing temperatures can affect the deformation behavior of the Cu stack.
{"title":"The numerical study of mechanical improvement of the metal annealing process during the manufacturing of the IC backend Damascene structure.","authors":"P. Y. Sun, Yuan Cadmus C.A., K. Chiang","doi":"10.1109/IMPACT56280.2022.9966686","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966686","url":null,"abstract":"This research establishes a set of transient finite element models to represent the mechanical impacts during the w/b process. Moreover, a finite element model of the BEOL structure, which consisted of 7 layers of copper metal stacks and an aluminum pad to represent the current frequent-used technology, is established to investigate the stress pattern. The results show that the Cu/low-k system produces larger stress levels in the column structure and induces a larger amount of deformation than the Al/TEOS system, and different annealing temperatures can affect the deformation behavior of the Cu stack.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"27 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83521624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966677
Fu-Hsiang Chang, Kuo-Chi Chang, Hsiao-Chuan Wang
The semiconductor factory itself has a large amount of flammable and explosive gases, chemicals, etc., which have great harm to the safety of production equipment and personal safety. When the abnormal system fails, it may lead to inevitable gas leakage risks. In the past, many fire and explosion accidents and toxic gases happened in Taiwan. The leakage has seriously affected the operation of Taiwan's semiconductor supply chain. Especially now that Taiwan has become the world's leading semiconductor manufacturing center, it is particularly important. Therefore, the importance of monitoring and early warning of flammable and explosive dangerous gases is extremely important. Now that the era of Industry 4.0 has arrived, the intelligent production of semiconductor companies is undoubtedly an inevitable trend. Only by realizing the intelligence of explosion-proof gas monitoring and early warning can meet and adapt to the production needs of the era of Industry 4.0. ESP32 is a family of low-cost, low-power single-chip microcontrollers that integrate Wi-Fi and dual-mode Bluetooth. It uses the Tensilica Xtensa LX6 microprocessor and includes dual-core and single-core variants with built-in antenna switches, RF converters, power amplifiers, low noise receiver amplifiers, f2ilters and power management modules. This research takes ESP3 as the core, and the system is designed according to the scene of the semiconductor factory. This intelligent explosion-proof gas monitoring and early warning system includes: sensing and detection system; data communication system; data processing system; comprehensive systems such as early warning, semiconductor factory engineers can real-time monitoring of dangerous gases, according to the intuitive results such as data and status generated by the system, and the trend of gas status changes can be obtained by analyzing the data and status information stored in the database, and the potential threats of safety hazards can be stifled in the cradle as soon as possible. So as to ensure the safety, continuity, and efficiency of the real-time wafer production process.
{"title":"INTELLIGENT EXPLOSION-PROOF GAS MONITORING AND EARLY WARNING SYSTEM WITH SEMICONDUCTOR PLANT As DISASTER PRVENTION TARGET","authors":"Fu-Hsiang Chang, Kuo-Chi Chang, Hsiao-Chuan Wang","doi":"10.1109/IMPACT56280.2022.9966677","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966677","url":null,"abstract":"The semiconductor factory itself has a large amount of flammable and explosive gases, chemicals, etc., which have great harm to the safety of production equipment and personal safety. When the abnormal system fails, it may lead to inevitable gas leakage risks. In the past, many fire and explosion accidents and toxic gases happened in Taiwan. The leakage has seriously affected the operation of Taiwan's semiconductor supply chain. Especially now that Taiwan has become the world's leading semiconductor manufacturing center, it is particularly important. Therefore, the importance of monitoring and early warning of flammable and explosive dangerous gases is extremely important. Now that the era of Industry 4.0 has arrived, the intelligent production of semiconductor companies is undoubtedly an inevitable trend. Only by realizing the intelligence of explosion-proof gas monitoring and early warning can meet and adapt to the production needs of the era of Industry 4.0. ESP32 is a family of low-cost, low-power single-chip microcontrollers that integrate Wi-Fi and dual-mode Bluetooth. It uses the Tensilica Xtensa LX6 microprocessor and includes dual-core and single-core variants with built-in antenna switches, RF converters, power amplifiers, low noise receiver amplifiers, f2ilters and power management modules. This research takes ESP3 as the core, and the system is designed according to the scene of the semiconductor factory. This intelligent explosion-proof gas monitoring and early warning system includes: sensing and detection system; data communication system; data processing system; comprehensive systems such as early warning, semiconductor factory engineers can real-time monitoring of dangerous gases, according to the intuitive results such as data and status generated by the system, and the trend of gas status changes can be obtained by analyzing the data and status information stored in the database, and the potential threats of safety hazards can be stifled in the cradle as soon as possible. So as to ensure the safety, continuity, and efficiency of the real-time wafer production process.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"29 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86671636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966696
Yung-Sheng Kuo, Bud Tseng, Nhlakanipho Sikhondze
This research discusses the thermal influence of the pin-fin angle and spacing of a liquid cooling module, and uses CFD simulation software for validation. When the pin-fin angle was increased, the junction temperature became higher. Although the junction temperature rose slowly, it was still above the maximum operating junction temperature of an IGBT module. Furthermore, when the pin-fin spacing was increased from 1mm to 8mm, the junction temperature rose at a faster rate. Therefore, the results from this study suggest that the pin-fin angle should be, or close to, 0° (perpendicular to fluid flow direction) and the spacing between pin-fins should be as small as possible when designing liquid cooling thermal dissipation module.
{"title":"The Study of the Influence on Heat Dissipation Effectiveness of the Pin-Fin Angle and Spacing in a Liquid Cooling Module","authors":"Yung-Sheng Kuo, Bud Tseng, Nhlakanipho Sikhondze","doi":"10.1109/IMPACT56280.2022.9966696","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966696","url":null,"abstract":"This research discusses the thermal influence of the pin-fin angle and spacing of a liquid cooling module, and uses CFD simulation software for validation. When the pin-fin angle was increased, the junction temperature became higher. Although the junction temperature rose slowly, it was still above the maximum operating junction temperature of an IGBT module. Furthermore, when the pin-fin spacing was increased from 1mm to 8mm, the junction temperature rose at a faster rate. Therefore, the results from this study suggest that the pin-fin angle should be, or close to, 0° (perpendicular to fluid flow direction) and the spacing between pin-fins should be as small as possible when designing liquid cooling thermal dissipation module.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"77 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88963458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the rapid development of technology, the number and demand for handheld devices are increasing, and the new technology product development and launch are getting faster and faster. Also, handheld devices need to withstand various movements, fall-down situations, and even regular use in different temperature environments. Therefore, solder joint reliability is decidedly crucial for handheld devices. Moreover, how to seize the critical factors during the design development phase and fulfill market demands are also significant. According to the definition of JESD22-B111 [1], the drop test requires that the board should be horizontal with the package facing in the downward direction (-Z) during the experiment. Therefore, under the influence of the acceleration of gravity, the weight of the ball grid array(BGA) package, the number of balls, solder ball material, and the solder ball pad size in the drop test are recognized as important factors affecting the board-level reliability of the drop test. This study will explore these key factors and how they affect the board-level reliability of the drop test.
{"title":"A Study of JEDEC Board-Level Drop Test Performance Prediction Trend of BGA Package with SAC1205 Under Different Key Factors","authors":"Chih-Min Cheng, Hsi-Wei Chao, Chu-Chiao Yen, Kun-Ting Chiang, Wei-Yao Chang, Chia-Wen Chang, Ya-Ping Chen, Hsien-Wei Ho, Chun-Yu Ko, Chun-Liang Kuo","doi":"10.1109/IMPACT56280.2022.9966688","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966688","url":null,"abstract":"With the rapid development of technology, the number and demand for handheld devices are increasing, and the new technology product development and launch are getting faster and faster. Also, handheld devices need to withstand various movements, fall-down situations, and even regular use in different temperature environments. Therefore, solder joint reliability is decidedly crucial for handheld devices. Moreover, how to seize the critical factors during the design development phase and fulfill market demands are also significant. According to the definition of JESD22-B111 [1], the drop test requires that the board should be horizontal with the package facing in the downward direction (-Z) during the experiment. Therefore, under the influence of the acceleration of gravity, the weight of the ball grid array(BGA) package, the number of balls, solder ball material, and the solder ball pad size in the drop test are recognized as important factors affecting the board-level reliability of the drop test. This study will explore these key factors and how they affect the board-level reliability of the drop test.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"67 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89049322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966645
Maddux Sy, Sean Fleuriel, Confesol Rodriguez, Kesheng Feng, Robert Moon, Dolores Cruz, J. Hander
Advanced packaging suppliers are having two primary challenges during IC substrate fabrication, meeting the requirements on copper plating performance and reducing the cost from manufacturing process. The requirements on plating performance include high resolution and strict height uniformity within a die (WID) and within a panel (WIP), consistent deposit grain structure, and robust physical properties to meet reliability requirements. The plated features include fine lines, trenches, and vias, whose top shape and coplanarity are critical to the product quality. A non-planar surface could result in signal transmission loss and introduce weak points in the connections. Therefore, copper plating solutions providing uniform, planar structures, without any special post treatment are highly desirable features from RDL plating processes. The copper plating solution can also reduce cost by plating two or three types of features in a single electrolyte, this flexibility allows fabricators to save on space and equipmentIn this paper, an electroplating package, Systek UVF 200, is introduced to plate RDL under different current densities in vertical continuous platers (VCP) and a high-speed panel plater. The plating uniformity was evaluated on a panel level in a high-speed plater, AMSPT NEXX P500.The Systek UVF 200 package offered excellent coplanarity within a pattern unit or die for RDL plating. The variation in the plated height (or thickness) between fine lines (as low as 9 μm in width) and pads, was below 2.0 μm when using a current density below 5.0 ASD to obtain the plated copper thickness around 12 μm. For 14 μm wide lines, the plated copper thickness variation can be below 1.2 μm. The variation of plated thickness across 510 mm x 515 mm panels was below 5%. The tops of the fine lines have defined, slightly domed shapes, these types of profiles have excellent conductivity.Physical properties of the plated copper deposit are essential for the reliability of the finished product. A few key physical properties are tensile strength, elongation %, and internal stress. These properties show the tolerance of the deposit to withstand thermal stress and warpage. The additives (wetter, brightener, and leveler) strongly influence the physical properties of the deposit. Copper deposited with the Systek UVF 200 package has tensile strength above 40,000 psi, elongation % above 18%, and internal stress below 1.0 Kg/mm2. The physical properties of the deposited copper did not change under different current density, showing that the package has stable performance.
{"title":"RDL Copper Plating Process for Panel Level Packaging Application","authors":"Maddux Sy, Sean Fleuriel, Confesol Rodriguez, Kesheng Feng, Robert Moon, Dolores Cruz, J. Hander","doi":"10.1109/IMPACT56280.2022.9966645","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966645","url":null,"abstract":"Advanced packaging suppliers are having two primary challenges during IC substrate fabrication, meeting the requirements on copper plating performance and reducing the cost from manufacturing process. The requirements on plating performance include high resolution and strict height uniformity within a die (WID) and within a panel (WIP), consistent deposit grain structure, and robust physical properties to meet reliability requirements. The plated features include fine lines, trenches, and vias, whose top shape and coplanarity are critical to the product quality. A non-planar surface could result in signal transmission loss and introduce weak points in the connections. Therefore, copper plating solutions providing uniform, planar structures, without any special post treatment are highly desirable features from RDL plating processes. The copper plating solution can also reduce cost by plating two or three types of features in a single electrolyte, this flexibility allows fabricators to save on space and equipmentIn this paper, an electroplating package, Systek UVF 200, is introduced to plate RDL under different current densities in vertical continuous platers (VCP) and a high-speed panel plater. The plating uniformity was evaluated on a panel level in a high-speed plater, AMSPT NEXX P500.The Systek UVF 200 package offered excellent coplanarity within a pattern unit or die for RDL plating. The variation in the plated height (or thickness) between fine lines (as low as 9 μm in width) and pads, was below 2.0 μm when using a current density below 5.0 ASD to obtain the plated copper thickness around 12 μm. For 14 μm wide lines, the plated copper thickness variation can be below 1.2 μm. The variation of plated thickness across 510 mm x 515 mm panels was below 5%. The tops of the fine lines have defined, slightly domed shapes, these types of profiles have excellent conductivity.Physical properties of the plated copper deposit are essential for the reliability of the finished product. A few key physical properties are tensile strength, elongation %, and internal stress. These properties show the tolerance of the deposit to withstand thermal stress and warpage. The additives (wetter, brightener, and leveler) strongly influence the physical properties of the deposit. Copper deposited with the Systek UVF 200 package has tensile strength above 40,000 psi, elongation % above 18%, and internal stress below 1.0 Kg/mm2. The physical properties of the deposited copper did not change under different current density, showing that the package has stable performance.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"27 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80967494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966636
J. Hsu, Ryan Chang, Xiaoning Ye, T. Su, Zoe Liu
In this paper, a novel and effective approach by the innovative customized PCB surface printing was proposed to reduce far-end crosstalk (FEXT) in multiple microstrip lines. A new type of solder mask with higher dielectric constant up to 8, instead of the conventional one with around 4, was developed for PCB surface printing. The test coupons with the proposed customized solder mask are built and validated, and the measured FEXT was significantly reduced. The design strategy with the optimized structures was clearly addressed, and this innovation can effectively enhance the microstrip electrical performance for high-speed application.
{"title":"An Innovative Customized PCB Surface Printing for Performance Enhancement","authors":"J. Hsu, Ryan Chang, Xiaoning Ye, T. Su, Zoe Liu","doi":"10.1109/IMPACT56280.2022.9966636","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966636","url":null,"abstract":"In this paper, a novel and effective approach by the innovative customized PCB surface printing was proposed to reduce far-end crosstalk (FEXT) in multiple microstrip lines. A new type of solder mask with higher dielectric constant up to 8, instead of the conventional one with around 4, was developed for PCB surface printing. The test coupons with the proposed customized solder mask are built and validated, and the measured FEXT was significantly reduced. The design strategy with the optimized structures was clearly addressed, and this innovation can effectively enhance the microstrip electrical performance for high-speed application.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"52 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76342923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/impact56280.2022.9966722
Chun-Kai Liu, Chiu Po-Kai, Yuan-Cheng Huang, J. Syu, Yao-Shun Chen, Yu-An Chou, Kuang-Hung Wu, Wen-Yang Pan
Silicon-Carbide semiconductor device has the benefits of higher breakdown voltage, higher current, higher operating temperature, higher switching speed, and lower switching loss over Si devices. It offers system-level benefits of high efficiency and power density to EV/HEV powertrain. However, thermal management solutions face new challenges in mitigating the increased heat flux in powertrain due to increased power density. High heat flux can raise the temperature of power devices and ICs, which reduces reliability and efficiency, and can lead to failure. In this paper, we studied the thermal design of the 1200 V, 400A SiC power module for EV/HEV applications by numerical simulation and experimental measurement. The effects of powering conditions, inlet temperature, and liquid flow rate are studied comprehensively.
{"title":"Thermal Design of SiC Power Module for EV/HEV Applications","authors":"Chun-Kai Liu, Chiu Po-Kai, Yuan-Cheng Huang, J. Syu, Yao-Shun Chen, Yu-An Chou, Kuang-Hung Wu, Wen-Yang Pan","doi":"10.1109/impact56280.2022.9966722","DOIUrl":"https://doi.org/10.1109/impact56280.2022.9966722","url":null,"abstract":"Silicon-Carbide semiconductor device has the benefits of higher breakdown voltage, higher current, higher operating temperature, higher switching speed, and lower switching loss over Si devices. It offers system-level benefits of high efficiency and power density to EV/HEV powertrain. However, thermal management solutions face new challenges in mitigating the increased heat flux in powertrain due to increased power density. High heat flux can raise the temperature of power devices and ICs, which reduces reliability and efficiency, and can lead to failure. In this paper, we studied the thermal design of the 1200 V, 400A SiC power module for EV/HEV applications by numerical simulation and experimental measurement. The effects of powering conditions, inlet temperature, and liquid flow rate are studied comprehensively.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"80 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76562439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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