Pub Date : 2004-08-15DOI: 10.1109/CIPE.2004.1428156
P. Ljušev, M. Andersen
This paper describes implementation of a simple digital PID control algorithm for a boost converter using a cheap fixed-point 8-bit microcontroller. Serial communication to a PC server application is established for easier downloading of compensator parameters and current and voltage waveform acquisition. At the end, client application is presented which uses TCP/IP connection for operating the digitally controlled boost converter over Internet. The aim of this cheap and flexible PC-interfaced boost converter bench is predominantly educational, to allow students to synthesize different digital controllers and compare their performance.
{"title":"Digitally-controlled PC-interfaced boost converter for educational purposes","authors":"P. Ljušev, M. Andersen","doi":"10.1109/CIPE.2004.1428156","DOIUrl":"https://doi.org/10.1109/CIPE.2004.1428156","url":null,"abstract":"This paper describes implementation of a simple digital PID control algorithm for a boost converter using a cheap fixed-point 8-bit microcontroller. Serial communication to a PC server application is established for easier downloading of compensator parameters and current and voltage waveform acquisition. At the end, client application is presented which uses TCP/IP connection for operating the digitally controlled boost converter over Internet. The aim of this cheap and flexible PC-interfaced boost converter bench is predominantly educational, to allow students to synthesize different digital controllers and compare their performance.","PeriodicalId":137483,"journal":{"name":"2004 IEEE Workshop on Computers in Power Electronics, 2004. Proceedings.","volume":" 67","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120830857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-08-15DOI: 10.1109/CIPE.2004.1428122
W. Weaver, P. Krein
The field population of power electronics loads continues to grow. Most such loads, including motor drives, computer power supplies, and even compact fluorescent lighting "isolate" the load dynamics from the utility grid. When isolated these loads enforce local constant power behavior, which can de-stabilize a weak power system. One method to mitigate the effects of constant power loads is the use of active dynamic power buffers. This paper reviews the power buffer concept, and presents DC-DC converter control methods and considerations to implement an active power buffer.
{"title":"Control method considerations for DC-DC converters in power buffer applications","authors":"W. Weaver, P. Krein","doi":"10.1109/CIPE.2004.1428122","DOIUrl":"https://doi.org/10.1109/CIPE.2004.1428122","url":null,"abstract":"The field population of power electronics loads continues to grow. Most such loads, including motor drives, computer power supplies, and even compact fluorescent lighting \"isolate\" the load dynamics from the utility grid. When isolated these loads enforce local constant power behavior, which can de-stabilize a weak power system. One method to mitigate the effects of constant power loads is the use of active dynamic power buffers. This paper reviews the power buffer concept, and presents DC-DC converter control methods and considerations to implement an active power buffer.","PeriodicalId":137483,"journal":{"name":"2004 IEEE Workshop on Computers in Power Electronics, 2004. Proceedings.","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117339352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-08-15DOI: 10.1109/CIPE.2004.1428146
Hui Li, Da Zhang, M. Steuer, K. Shi, S. Woodruf
As the cost of power electronics and control is decreasing, the squirrel-cage induction generator with back-to-back power converters is becoming popular among the variable-speed wind turbines. This paper describes a complete simulation study of a VSWT (variable-speed wind turbine) system based on squirrel-cage induction generator. It includes the modeling of a wind turbine, generator, and a double-sided PWM converter with real power and reactive power control. The validity of the simulation and the modeling of the system are verified by a real-time wind turbine generation system test bed.
{"title":"Modeling, simulation and experimental test of a variable-speed cage machine wind generation system","authors":"Hui Li, Da Zhang, M. Steuer, K. Shi, S. Woodruf","doi":"10.1109/CIPE.2004.1428146","DOIUrl":"https://doi.org/10.1109/CIPE.2004.1428146","url":null,"abstract":"As the cost of power electronics and control is decreasing, the squirrel-cage induction generator with back-to-back power converters is becoming popular among the variable-speed wind turbines. This paper describes a complete simulation study of a VSWT (variable-speed wind turbine) system based on squirrel-cage induction generator. It includes the modeling of a wind turbine, generator, and a double-sided PWM converter with real power and reactive power control. The validity of the simulation and the modeling of the system are verified by a real-time wind turbine generation system test bed.","PeriodicalId":137483,"journal":{"name":"2004 IEEE Workshop on Computers in Power Electronics, 2004. Proceedings.","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123851821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-08-15DOI: 10.1109/CIPE.2004.1428157
A. Hande
A high frequency inverter has been designed for internally heating hybrid electric vehicle (HEV) batteries at cold temperatures using alternating current (AC). The inverter was designed for a maximum pack voltage of 200 V and minimum operating frequency of 6.67 kHz while operating in the continuous conduction mode. It uses a pair of insulated gate bipolar transistors (IGBTs) connected in a half bridge configuration. The inverter circuit was first simulated in PSpice for obtaining adequate values for the circuit components and then constructed. A digital circuit was used to control the input signals to the IGBT driver cards. The inverter was tested on a pack of nickel metal hydride (NiMH) batteries at different cold temperatures to verify the feasibility of high frequency AC heating. A sophisticated data acquisition system was used for measuring battery temperature and voltage data for display on a computer. This data was also used to control the inverter operation during the tests. Experimental results have shown that at both -20 and -30 /spl deg/C, 10-20 kHz AC currents at amplitudes of 60-80 A rms warmed the pack to about 25 /spl deg/C within a few minutes, and thereby improved the pack discharge capability.
{"title":"A high frequency inverter for cold temperature battery heating","authors":"A. Hande","doi":"10.1109/CIPE.2004.1428157","DOIUrl":"https://doi.org/10.1109/CIPE.2004.1428157","url":null,"abstract":"A high frequency inverter has been designed for internally heating hybrid electric vehicle (HEV) batteries at cold temperatures using alternating current (AC). The inverter was designed for a maximum pack voltage of 200 V and minimum operating frequency of 6.67 kHz while operating in the continuous conduction mode. It uses a pair of insulated gate bipolar transistors (IGBTs) connected in a half bridge configuration. The inverter circuit was first simulated in PSpice for obtaining adequate values for the circuit components and then constructed. A digital circuit was used to control the input signals to the IGBT driver cards. The inverter was tested on a pack of nickel metal hydride (NiMH) batteries at different cold temperatures to verify the feasibility of high frequency AC heating. A sophisticated data acquisition system was used for measuring battery temperature and voltage data for display on a computer. This data was also used to control the inverter operation during the tests. Experimental results have shown that at both -20 and -30 /spl deg/C, 10-20 kHz AC currents at amplitudes of 60-80 A rms warmed the pack to about 25 /spl deg/C within a few minutes, and thereby improved the pack discharge capability.","PeriodicalId":137483,"journal":{"name":"2004 IEEE Workshop on Computers in Power Electronics, 2004. Proceedings.","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115311429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-08-15DOI: 10.1109/CIPE.2004.1428113
L. Qu, P. Chapman
In power electronics and electric machinery, finite-element based time-domain modeling has been used frequently. Generally, the time-domain modeling of magnetic devices is completed by solving a high order system at each time step. Fortunately, the full order state-space models can be reduced methodically without additional assumption. The method for reducing the order of magnetically linear system is presented in previous work. However, in the analysis of magnetic devices the problems are usually nonlinear due to the presence of ferromagnetic materials. In this paper, a nonlinear model of the magnetic devices is presented and reduced by using a trajectory piecewise-linear approach.
{"title":"A trajectory piecewise-linear approach to model order reduction for nonlinear stationary magnetic devices","authors":"L. Qu, P. Chapman","doi":"10.1109/CIPE.2004.1428113","DOIUrl":"https://doi.org/10.1109/CIPE.2004.1428113","url":null,"abstract":"In power electronics and electric machinery, finite-element based time-domain modeling has been used frequently. Generally, the time-domain modeling of magnetic devices is completed by solving a high order system at each time step. Fortunately, the full order state-space models can be reduced methodically without additional assumption. The method for reducing the order of magnetically linear system is presented in previous work. However, in the analysis of magnetic devices the problems are usually nonlinear due to the presence of ferromagnetic materials. In this paper, a nonlinear model of the magnetic devices is presented and reduced by using a trajectory piecewise-linear approach.","PeriodicalId":137483,"journal":{"name":"2004 IEEE Workshop on Computers in Power Electronics, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121637448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-08-15DOI: 10.1109/CIPE.2004.1428137
Z. Du, L. Tolbert, J. Chiasson
This paper presents an optimal total harmonic distortion (THD) control algorithm referred to as active harmonic elimination method for cascaded H-bridges multilevel converter control with unequal DC sources. First, the multilevel converter is decoupled into unipolar converters, the low order harmonics, such as the 5th, 7th, 11th and 13th are eliminated by using elimination theory, and the minimum THD combination of unipolar converters for multilevel converter control is found. Next, the magnitudes and phases of the residual higher harmonics are computed and subtracted from the original output voltage waveform to eliminate these higher harmonics. To validate the proposed algorithm, the method is simulated by Matlab first. After the simulation, an experimental 11-level H-bridge multilevel converter with a real-time controller based on Altera FLEX 10 K field programmable gate array (FPGA) is used to implement the algorithm with 8 /spl mu/s control resolution. The experimental results show that the method can effectively eliminate the specific harmonics as expected, and the output voltage waveforms have low THD.
{"title":"Active harmonic elimination in multilevel converters using FPGA control","authors":"Z. Du, L. Tolbert, J. Chiasson","doi":"10.1109/CIPE.2004.1428137","DOIUrl":"https://doi.org/10.1109/CIPE.2004.1428137","url":null,"abstract":"This paper presents an optimal total harmonic distortion (THD) control algorithm referred to as active harmonic elimination method for cascaded H-bridges multilevel converter control with unequal DC sources. First, the multilevel converter is decoupled into unipolar converters, the low order harmonics, such as the 5th, 7th, 11th and 13th are eliminated by using elimination theory, and the minimum THD combination of unipolar converters for multilevel converter control is found. Next, the magnitudes and phases of the residual higher harmonics are computed and subtracted from the original output voltage waveform to eliminate these higher harmonics. To validate the proposed algorithm, the method is simulated by Matlab first. After the simulation, an experimental 11-level H-bridge multilevel converter with a real-time controller based on Altera FLEX 10 K field programmable gate array (FPGA) is used to implement the algorithm with 8 /spl mu/s control resolution. The experimental results show that the method can effectively eliminate the specific harmonics as expected, and the output voltage waveforms have low THD.","PeriodicalId":137483,"journal":{"name":"2004 IEEE Workshop on Computers in Power Electronics, 2004. Proceedings.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120962585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-08-15DOI: 10.1109/CIPE.2004.1428119
A. Kashyap, C. Vemulapally, H. Mantooth
VHDL-AMS is gaining ground as the standard modeling language for devices and systems. A new modeling tool, Paragon, is presented in this work that helps the user to create models with only the topology and the characteristic equations. Paragon then generates the model in various HDLs such as VHDL-AMS, MAST and Verilog-A. As an example, a silicon carbide vertical JFET/SIT is modeled using Paragon. SiC JFETs are power switches that have a variety of applications in the industry. A compact model is developed in VHDL-AMS based on the device geometry and SiC material properties. The on-state model has been tested in mentor graphics' system vision VHDL-AMS simulator and it clearly replicates the behavior seen in experimental characterization as the validation results show.
{"title":"VHDL - AMS modeling of silicon carbide power semiconductor devices","authors":"A. Kashyap, C. Vemulapally, H. Mantooth","doi":"10.1109/CIPE.2004.1428119","DOIUrl":"https://doi.org/10.1109/CIPE.2004.1428119","url":null,"abstract":"VHDL-AMS is gaining ground as the standard modeling language for devices and systems. A new modeling tool, Paragon, is presented in this work that helps the user to create models with only the topology and the characteristic equations. Paragon then generates the model in various HDLs such as VHDL-AMS, MAST and Verilog-A. As an example, a silicon carbide vertical JFET/SIT is modeled using Paragon. SiC JFETs are power switches that have a variety of applications in the industry. A compact model is developed in VHDL-AMS based on the device geometry and SiC material properties. The on-state model has been tested in mentor graphics' system vision VHDL-AMS simulator and it clearly replicates the behavior seen in experimental characterization as the validation results show.","PeriodicalId":137483,"journal":{"name":"2004 IEEE Workshop on Computers in Power Electronics, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129488320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-08-15DOI: 10.1109/CIPE.2004.1428138
Tim C. O’Connell, P. Krein, J. Mossoba, Grainger
Mathematica 5.0 software is used to develop a first-principles analysis of an induction machine represented by a planar layered structure subject to a sinusoidal current sheet excitation. A brief review is also given of mathematical application to problems in both power electronic and electric machine systems. The program presented is capable of calculating the time-harmonic steady-state magnetic field, current density, ohmic loss, and torque-speed curve for an n-layered structure. When it is used to optimize both two- and three-layer rotor structures, the program shows that the smaller the air gap, the better the performance of the design.
{"title":"Symbolic analysis with Mathematica in power electronics and electromechanical systems","authors":"Tim C. O’Connell, P. Krein, J. Mossoba, Grainger","doi":"10.1109/CIPE.2004.1428138","DOIUrl":"https://doi.org/10.1109/CIPE.2004.1428138","url":null,"abstract":"Mathematica 5.0 software is used to develop a first-principles analysis of an induction machine represented by a planar layered structure subject to a sinusoidal current sheet excitation. A brief review is also given of mathematical application to problems in both power electronic and electric machine systems. The program presented is capable of calculating the time-harmonic steady-state magnetic field, current density, ohmic loss, and torque-speed curve for an n-layered structure. When it is used to optimize both two- and three-layer rotor structures, the program shows that the smaller the air gap, the better the performance of the design.","PeriodicalId":137483,"journal":{"name":"2004 IEEE Workshop on Computers in Power Electronics, 2004. Proceedings.","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130300318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-08-15DOI: 10.1109/CIPE.2004.1428124
J. Byoun, P. Chapman
The central power management unit (CPMU) is proposed and verified with a simple example system. The CPMU is a single controller for the multiple heterogeneous converters in a single portable system. CPMU is the true digital controller, located in the feedback loop, and is not based on a processor. The CPMU regulates multiple converters as well as systematically integrates other power management architecture such as the protection circuitry, converter sequencing, and voltage scaling. The control parameters can be flexibly and dynamically modified in CPMU. The proposed architecture is evaluated with the detailed simulation in Matlab/Simulink environment.
{"title":"Central power management unit as portable power management architecture based on true digital control","authors":"J. Byoun, P. Chapman","doi":"10.1109/CIPE.2004.1428124","DOIUrl":"https://doi.org/10.1109/CIPE.2004.1428124","url":null,"abstract":"The central power management unit (CPMU) is proposed and verified with a simple example system. The CPMU is a single controller for the multiple heterogeneous converters in a single portable system. CPMU is the true digital controller, located in the feedback loop, and is not based on a processor. The CPMU regulates multiple converters as well as systematically integrates other power management architecture such as the protection circuitry, converter sequencing, and voltage scaling. The control parameters can be flexibly and dynamically modified in CPMU. The proposed architecture is evaluated with the detailed simulation in Matlab/Simulink environment.","PeriodicalId":137483,"journal":{"name":"2004 IEEE Workshop on Computers in Power Electronics, 2004. Proceedings.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129870265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-08-15DOI: 10.1109/CIPE.2004.1428126
G. Capponi, P. Livreri, G. Di Blasi, F. Marino
This paper presents a digital controller architecture oriented to IC implementation. The classical digital pulse width modulator (D-PWM), using digital analog converter (DAC), is replaced with a Sigma-Delta (/spl Sigma//spl Delta/) modulator based on pulse frequency modulator (PFM) technique. Results of an investigation from a prototype for DC-DC converter, in terms of simulated and experimental performances, are reported, together with harmonic frequency investigation. The control function design is implemented on a field programmable gate array (FPGA). As a consequence of good agreement between simulated and experimental results, the proposed architecture realizes a digital control loop with dynamic performances comparable to analog control systems.
{"title":"Architecture of a digital PFM controller for IC implementation","authors":"G. Capponi, P. Livreri, G. Di Blasi, F. Marino","doi":"10.1109/CIPE.2004.1428126","DOIUrl":"https://doi.org/10.1109/CIPE.2004.1428126","url":null,"abstract":"This paper presents a digital controller architecture oriented to IC implementation. The classical digital pulse width modulator (D-PWM), using digital analog converter (DAC), is replaced with a Sigma-Delta (/spl Sigma//spl Delta/) modulator based on pulse frequency modulator (PFM) technique. Results of an investigation from a prototype for DC-DC converter, in terms of simulated and experimental performances, are reported, together with harmonic frequency investigation. The control function design is implemented on a field programmable gate array (FPGA). As a consequence of good agreement between simulated and experimental results, the proposed architecture realizes a digital control loop with dynamic performances comparable to analog control systems.","PeriodicalId":137483,"journal":{"name":"2004 IEEE Workshop on Computers in Power Electronics, 2004. Proceedings.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127872860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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