This paper describes a fast Boolean matching algorithm which checks the containment relationship between an incompletely specified function and a completely specified function under permutation and negation on the input variables. The algorithm is designed for the pattern matching problem in technology mapping. It exploits functional symmetries of patterns and utilizes a compact data structure: binary permutation matrix. Using this matrix, nonmatching permutations and phase assignments can be pruned efficiently. All legal permutations and phase assignments, leading to a matching, can be obtained, as well. The experimental results on the MCNC benchmarks show that, compared with other Boolean matching approaches, our algorithm is at least 1,500 times faster for a common pattern abed + efgh and 58,000 times faster for another common pattern ab + cd + ef + gh. The matching speed for completely specified functions is also comparable to state-of-the-art matching algorithms
本文描述了一种快速布尔匹配算法，用于在输入变量的置换和否定条件下检验不完全指定函数与完全指定函数之间的包含关系。该算法是针对技术映射中的模式匹配问题设计的。它利用模式的功能对称性，并利用紧凑的数据结构:二进制置换矩阵。利用该矩阵可以有效地修剪不匹配的排列和相位分配。所有合法的排列和阶段分配，导致匹配，也可以得到。MCNC基准测试的实验结果表明，与其他布尔匹配方法相比，我们的算法对于常见模式abed + efgh的速度至少快1500倍，对于另一种常见模式ab + cd + ef + gh的速度快58,000倍。完全指定函数的匹配速度也可与最先进的匹配算法相媲美
{"title":"Fast Boolean matching with don't cares","authors":"Zile Wei, Donald Chai, A. Newton, A. Kuehlmann","doi":"10.1109/ISQED.2006.65","DOIUrl":"https://doi.org/10.1109/ISQED.2006.65","url":null,"abstract":"This paper describes a fast Boolean matching algorithm which checks the containment relationship between an incompletely specified function and a completely specified function under permutation and negation on the input variables. The algorithm is designed for the pattern matching problem in technology mapping. It exploits functional symmetries of patterns and utilizes a compact data structure: binary permutation matrix. Using this matrix, nonmatching permutations and phase assignments can be pruned efficiently. All legal permutations and phase assignments, leading to a matching, can be obtained, as well. The experimental results on the MCNC benchmarks show that, compared with other Boolean matching approaches, our algorithm is at least 1,500 times faster for a common pattern abed + efgh and 58,000 times faster for another common pattern ab + cd + ef + gh. The matching speed for completely specified functions is also comparable to state-of-the-art matching algorithms","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133731456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher permittivity (dual-K) or use of silicon dioxide of higher thicknesses (dual-T) is being considered as methods for its reduction. This paper presents a comparative view of dual dielectric and dual thickness low leakage design techniques from a behavioral synthesis perspective. An algorithm is presented for the gate leakage current reduction that does simultaneous scheduling, allocation and binding during behavioral synthesis while accounting for process variations. The algorithm minimizes the gate leakage for given time constraints. We performed experiments for a number of benchmark circuits using a 45nm CMOS technology datapath library. We obtained gate leakage reduction as high as 95% for the dual-K (SiO2 and Si3 N4) and 91% for the dual-T (1.4 nm and 1.7 nm) approaches. It is observed that the dual-K approach outperformed the dual-T approach for all benchmark circuits
{"title":"Dual-K versus dual-T technique for gate leakage reduction: a comparative perspective","authors":"S. Mohanty, R. Velagapudi, E. Kougianos","doi":"10.1109/ISQED.2006.52","DOIUrl":"https://doi.org/10.1109/ISQED.2006.52","url":null,"abstract":"As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher permittivity (dual-K) or use of silicon dioxide of higher thicknesses (dual-T) is being considered as methods for its reduction. This paper presents a comparative view of dual dielectric and dual thickness low leakage design techniques from a behavioral synthesis perspective. An algorithm is presented for the gate leakage current reduction that does simultaneous scheduling, allocation and binding during behavioral synthesis while accounting for process variations. The algorithm minimizes the gate leakage for given time constraints. We performed experiments for a number of benchmark circuits using a 45nm CMOS technology datapath library. We obtained gate leakage reduction as high as 95% for the dual-K (SiO2 and Si3 N4) and 91% for the dual-T (1.4 nm and 1.7 nm) approaches. It is observed that the dual-K approach outperformed the dual-T approach for all benchmark circuits","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133592026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One or 2-step Gauss-Jacobi method is efficiently incorporated to the large scale interconnect analysis. In order to make the Gauss-Jacobi method within 1 or 2 iterations during each time step, the interconnect network is formulated by the RLCG-MNA formulation. In the numerical example, it is illustrated that the one-step Gauss-Jacobi method is 1,035 times faster than Berkeley SPICE and several tens times faster than INDUCTWISE which is known as the recent fast simulation method. Further, we show that the 2-step Gauss-Jacobi method is rational from efficiency and accuracy points of views
{"title":"Quasi-one-step Gauss-Jacobi method for large-scale interconnect analysis via RLCG-MNA formulation","authors":"Y. Tanji, Takayuki Watanabe, H. Kubota, H. Asai","doi":"10.1109/ISQED.2006.109","DOIUrl":"https://doi.org/10.1109/ISQED.2006.109","url":null,"abstract":"One or 2-step Gauss-Jacobi method is efficiently incorporated to the large scale interconnect analysis. In order to make the Gauss-Jacobi method within 1 or 2 iterations during each time step, the interconnect network is formulated by the RLCG-MNA formulation. In the numerical example, it is illustrated that the one-step Gauss-Jacobi method is 1,035 times faster than Berkeley SPICE and several tens times faster than INDUCTWISE which is known as the recent fast simulation method. Further, we show that the 2-step Gauss-Jacobi method is rational from efficiency and accuracy points of views","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129074141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Accurate measurement and analysis of interconnect capacitance is a critical component of nanometer technology verification. The charged-based capacitance measurement (CBCM) technique has been widely adopted as a robust technique to measure on-chip capacitance test structures. In this paper we present two design improvements for CBCM. The first is an area reduction by using bused circuit architecture to reduce probe pad area required for the test structure input and output signals. The second improvement involves techniques to reduce the impact of gate leakage and charge injection currents in 90 and 65nm process technology nodes. At the 90nm node we demonstrate accuracy improvement of an order of magnitude for small test structures
{"title":"Improvements to CBCM (charge-based capacitance measurement) for deep submicron CMOS technology","authors":"Randy Bach, Bob Davis, Rich Laubhan","doi":"10.1109/ISQED.2006.74","DOIUrl":"https://doi.org/10.1109/ISQED.2006.74","url":null,"abstract":"Accurate measurement and analysis of interconnect capacitance is a critical component of nanometer technology verification. The charged-based capacitance measurement (CBCM) technique has been widely adopted as a robust technique to measure on-chip capacitance test structures. In this paper we present two design improvements for CBCM. The first is an area reduction by using bused circuit architecture to reduce probe pad area required for the test structure input and output signals. The second improvement involves techniques to reduce the impact of gate leakage and charge injection currents in 90 and 65nm process technology nodes. At the 90nm node we demonstrate accuracy improvement of an order of magnitude for small test structures","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120966585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Kurdahi, A. Eltawil, Young-Hwan Park, R. Kanj, S. Nassif
It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or SOC. Thus yield management of these SRAMs plays a crucial role in insuring design success. This paper demonstrates analysis techniques to model and improve the yield of SRAMs at the system level by proper accounting for the coupling between the algorithms targeted for an SOC and the performance, power, and yield of SRAMs used in implementing the algorithms. It is shown that coupling the algorithm and SRAM design phases provides significant advantages over independent optimization
{"title":"System-level SRAM yield enhancement","authors":"F. Kurdahi, A. Eltawil, Young-Hwan Park, R. Kanj, S. Nassif","doi":"10.1109/ISQED.2006.130","DOIUrl":"https://doi.org/10.1109/ISQED.2006.130","url":null,"abstract":"It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or SOC. Thus yield management of these SRAMs plays a crucial role in insuring design success. This paper demonstrates analysis techniques to model and improve the yield of SRAMs at the system level by proper accounting for the coupling between the algorithms targeted for an SOC and the performance, power, and yield of SRAMs used in implementing the algorithms. It is shown that coupling the algorithm and SRAM design phases provides significant advantages over independent optimization","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124050075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Q. Do, Mindaugas Drazdziulis, P. Larsson-Edefors, L. Bengtsson
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circuit-simulation backend used to obtain static leakage power values of all basic memory components. The method is flexible in that memory size is an arbitrary parameter. In a comparison to circuit-level simulations (Hspice) of complete 2 KBytes and 8 KBytes 6T-SRAM memories implemented both in 0.13-mum and 65-nm (BPTM) bulk CMOS processes, the proposed method shows a high accuracy in estimating leakage power
{"title":"Parameterizable architecture-level SRAM power model using circuit-simulation backend for leakage calibration","authors":"M. Q. Do, Mindaugas Drazdziulis, P. Larsson-Edefors, L. Bengtsson","doi":"10.1109/ISQED.2006.97","DOIUrl":"https://doi.org/10.1109/ISQED.2006.97","url":null,"abstract":"We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circuit-simulation backend used to obtain static leakage power values of all basic memory components. The method is flexible in that memory size is an arbitrary parameter. In a comparison to circuit-level simulations (Hspice) of complete 2 KBytes and 8 KBytes 6T-SRAM memories implemented both in 0.13-mum and 65-nm (BPTM) bulk CMOS processes, the proposed method shows a high accuracy in estimating leakage power","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115273891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The onward march of Moore's Law obviously brings with it a host of challenges, not the least of which is how to design to the space that is now available on an average leading edge semiconductor device. With millions of available transistors and a variety of technology options to choose from, it's small wonder that IP providers have managed to continue to build a viable industry. But that industry is changing, with numerous business models and sources of IP emerging. How will the interaction between IP providers and semiconductor manufacturers change? How will the industry benefit, in terms of quality and availability of IP? Dr. Di Ma will present a foundry perspective, including interesting statistics on IP usage and how the future interplay of foundry and IP provider might develop.
{"title":"Successful IP Business Models","authors":"Di Ma","doi":"10.1109/ISQED.2006.127","DOIUrl":"https://doi.org/10.1109/ISQED.2006.127","url":null,"abstract":"The onward march of Moore's Law obviously brings with it a host of challenges, not the least of which is how to design to the space that is now available on an average leading edge semiconductor device. With millions of available transistors and a variety of technology options to choose from, it's small wonder that IP providers have managed to continue to build a viable industry. But that industry is changing, with numerous business models and sources of IP emerging. How will the interaction between IP providers and semiconductor manufacturers change? How will the industry benefit, in terms of quality and availability of IP? Dr. Di Ma will present a foundry perspective, including interesting statistics on IP usage and how the future interplay of foundry and IP provider might develop.","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"152 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115288655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
On-chip decoupling capacitors are generally used to reduce power supply noise. Traditional decoupling capacitor designs using NMOS devices may no longer be suitable for 90nm CMOS technology due to increased concerns on thin-oxide gate leakage and electrostatic discharge (ESD) reliability. A cross coupled design for standard cells have recently been proposed to address the ESD issue. In this paper, three modifications of the cross coupled design are introduced and the tradeoffs among ESD performance, transient response and gate leakage are analyzed. As shown here, the modifications offer designers greater flexibility in decoupling capacitor design for 90nm and below
{"title":"Novel decoupling capacitor designs for sub-90nm CMOS technology","authors":"Xiongfei Meng, R. Saleh, Karim Arabi","doi":"10.1109/ISQED.2006.93","DOIUrl":"https://doi.org/10.1109/ISQED.2006.93","url":null,"abstract":"On-chip decoupling capacitors are generally used to reduce power supply noise. Traditional decoupling capacitor designs using NMOS devices may no longer be suitable for 90nm CMOS technology due to increased concerns on thin-oxide gate leakage and electrostatic discharge (ESD) reliability. A cross coupled design for standard cells have recently been proposed to address the ESD issue. In this paper, three modifications of the cross coupled design are introduced and the tradeoffs among ESD performance, transient response and gate leakage are analyzed. As shown here, the modifications offer designers greater flexibility in decoupling capacitor design for 90nm and below","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115306450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Increasing process-parameter variations due to technology scaling to nanometer nodes have a significant impact on the circuit design flow. As shown repeatedly in previous work, a worst-case design approach is no longer feasible to guarantee a yielding design. Furthermore, the study of these process-parameter variations on the distributions of performance parameters has been done extensively in the past. However, this will not improve the circuit design unless the statistical information is considered during the optimization of the design. In this paper, we propose a method to minimize the leakage power of a SRAM cell while satisfying conflicting functionality and delay constraints, under these technology variations. Additionally, this method generates power-stability tradeoffs to optimize the circuit for a given yield at design time. Even at cell level, statistically aware design allows both minimal standby leakage power and minimal area
{"title":"Statistically aware SRAM memory array design","authors":"E. Grossar, M. Stucchi, K. Maex, W. Dehaene","doi":"10.1109/ISQED.2006.122","DOIUrl":"https://doi.org/10.1109/ISQED.2006.122","url":null,"abstract":"Increasing process-parameter variations due to technology scaling to nanometer nodes have a significant impact on the circuit design flow. As shown repeatedly in previous work, a worst-case design approach is no longer feasible to guarantee a yielding design. Furthermore, the study of these process-parameter variations on the distributions of performance parameters has been done extensively in the past. However, this will not improve the circuit design unless the statistical information is considered during the optimization of the design. In this paper, we propose a method to minimize the leakage power of a SRAM cell while satisfying conflicting functionality and delay constraints, under these technology variations. Additionally, this method generates power-stability tradeoffs to optimize the circuit for a given yield at design time. Even at cell level, statistically aware design allows both minimal standby leakage power and minimal area","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130701641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Melvin, Daniel N. Zhang, K. Strozewski, Skye Wolfer
As semiconductor device manufacturing processes are reducing feature sizes ever smaller, the manufacturing processes are becoming ever more complex. This complexity is having significant impacts on data communications between device design teams and manufacturing process teams. With current manufacturing process constraints, the constraints placed on a design team are difficult to conceptualize, communicate and enforce. This study describes a new type of process model, referred to as a focus sensitivity model that is capable of speeding up the model based analysis of design patterns for manufacturing robustness. The FSM is a difference model based on the photolithography process model. The FSM produces information about multiple process states in one pass. It also produces interpreted data, which removes the need to understand the performance of individual process states. Finally, FSM is capable of analyzing drawn patterns without optical proximity correction applied to determine pattern manufacturability
{"title":"The use of the manufacturing sensitivity model forms to comprehend layout manufacturing robustness for use during device design","authors":"L. Melvin, Daniel N. Zhang, K. Strozewski, Skye Wolfer","doi":"10.1109/ISQED.2006.135","DOIUrl":"https://doi.org/10.1109/ISQED.2006.135","url":null,"abstract":"As semiconductor device manufacturing processes are reducing feature sizes ever smaller, the manufacturing processes are becoming ever more complex. This complexity is having significant impacts on data communications between device design teams and manufacturing process teams. With current manufacturing process constraints, the constraints placed on a design team are difficult to conceptualize, communicate and enforce. This study describes a new type of process model, referred to as a focus sensitivity model that is capable of speeding up the model based analysis of design patterns for manufacturing robustness. The FSM is a difference model based on the photolithography process model. The FSM produces information about multiple process states in one pass. It also produces interpreted data, which removes the need to understand the performance of individual process states. Finally, FSM is capable of analyzing drawn patterns without optical proximity correction applied to determine pattern manufacturability","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127006186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：