Negative bias temperature instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in static noise margin (SNM) which is a measure of the read stability of the 6-T SRAM cell has been estimated using reaction-diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique
{"title":"Impact of NBTI on SRAM read stability and design for reliability","authors":"Sanjay V. Kumar, C. Kim, S. Sapatnekar","doi":"10.1109/ISQED.2006.73","DOIUrl":"https://doi.org/10.1109/ISQED.2006.73","url":null,"abstract":"Negative bias temperature instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in static noise margin (SNM) which is a measure of the read stability of the 6-T SRAM cell has been estimated using reaction-diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127392545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Multi-Threshold CMOS (MTCMOS) technique can significantly reduce sub-threshold leakage currents during the circuit sleep (standby) mode by adding high-Vth power switches (sleep transistors) to low-Vth logic cells. During the active mode of the circuit, the high-Vth transistors and the virtual ground network can be modeled as resistors, which in turn cause voltage of the virtual ground node to rise thereby degrading the switching speed of the logic cells. This paper introduces a new design methodology that minimizes the impact of virtual ground parasitic resistances on the performance of an MTCMOS circuit by using gate resizing and logic restructuring (i.e., gate replication.) Experimental results show that the proposed techniques are highly effective in making the MTCMOS circuits robust with respect to such parasitic resistance effects
{"title":"Gate sizing and replication to minimize the effects of virtual ground parasitic resistances in MTCMOS designs","authors":"Chanseok Hwang, C. Kang, Massoud Pedram","doi":"10.1109/ISQED.2006.70","DOIUrl":"https://doi.org/10.1109/ISQED.2006.70","url":null,"abstract":"The Multi-Threshold CMOS (MTCMOS) technique can significantly reduce sub-threshold leakage currents during the circuit sleep (standby) mode by adding high-Vth power switches (sleep transistors) to low-Vth logic cells. During the active mode of the circuit, the high-Vth transistors and the virtual ground network can be modeled as resistors, which in turn cause voltage of the virtual ground node to rise thereby degrading the switching speed of the logic cells. This paper introduces a new design methodology that minimizes the impact of virtual ground parasitic resistances on the performance of an MTCMOS circuit by using gate resizing and logic restructuring (i.e., gate replication.) Experimental results show that the proposed techniques are highly effective in making the MTCMOS circuits robust with respect to such parasitic resistance effects","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125468361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Convex optimization problems are very popular in the VLSI design society due to their guaranteed convergence to a global optimal point. Table data is often fitted into analytical forms like posynomials to make them convex. However, fitting the look-up tables into posynomial forms with minimum error itself may not be a convex optimization problem and hence excessive fitting errors may be introduced. In recent literature numerically convex tables have been proposed. These tables are created optimally by minimizing the perturbation of data to make them numerically convex. But since these tables are numerical, it is extremely important to make the table data smooth, and yet preserve its convexity. Smoothness will ensure that the convex optimizer behaves in a predictable way and converges quickly to the global optimal point. In this paper, we propose to simultaneously create optimal numerically convex look-up tables and guarantee smoothness in the data. We show that numerically "convexifying" and "smoothing" the table data with minimum perturbation can be formulated as a convex semidefinite optimization problem and hence optimality can be reached in polynomial time. We present our convexifying and smoothing results on industrial cell libraries. ConvexSmooth shows 14times reduction in fitting error over a well-developed posynomial fitting algorithm
{"title":"ConvexSmooth: a simultaneous convex fitting and smoothing algorithm for convex optimization problems","authors":"Sanghamitra Roy, C. C. Chen","doi":"10.1109/ISQED.2006.40","DOIUrl":"https://doi.org/10.1109/ISQED.2006.40","url":null,"abstract":"Convex optimization problems are very popular in the VLSI design society due to their guaranteed convergence to a global optimal point. Table data is often fitted into analytical forms like posynomials to make them convex. However, fitting the look-up tables into posynomial forms with minimum error itself may not be a convex optimization problem and hence excessive fitting errors may be introduced. In recent literature numerically convex tables have been proposed. These tables are created optimally by minimizing the perturbation of data to make them numerically convex. But since these tables are numerical, it is extremely important to make the table data smooth, and yet preserve its convexity. Smoothness will ensure that the convex optimizer behaves in a predictable way and converges quickly to the global optimal point. In this paper, we propose to simultaneously create optimal numerically convex look-up tables and guarantee smoothness in the data. We show that numerically \"convexifying\" and \"smoothing\" the table data with minimum perturbation can be formulated as a convex semidefinite optimization problem and hence optimality can be reached in polynomial time. We present our convexifying and smoothing results on industrial cell libraries. ConvexSmooth shows 14times reduction in fitting error over a well-developed posynomial fitting algorithm","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126802661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Traditionally, IC designers have been able to define "Quality of Results" (QoR) primarily in terms of functionality, area, speed, and power. Hardly a backward glance was given to what manufacturers would do once the designs were handed off to them. Today, manufacturability has clearly joining the ranks of QoR. This is particularly true for technology nodes at 65 nanometers (nm) and below. Yield loss mechanisms, both functional and parametric, have become dependant on the design and increasingly, as geometries continue to shrink to 45nm and below, must be addressed from design to lithography to process. In this talk, we will examine some solutions being used to ensure quality in this area of concern. Topics include incorporating yield-rated cells and probabilistic methods such as statistical timing analysis to address yield losses early in the design. Test is being used for diagnosis. Routing optimization techniques such as minimizing critical areas for shorts and open circuits, wire-spreading, redundant vias and dummy metal fills improve manufacturability for metal layers. Further down the tool chain, resolution enhancement techniques (RET) used in mask synthesis addresses lithography, improving printability and hence yield. Manufacturing process knowledge is becoming increasingly important in design to enable effective yield modeling. TCAD models are making their way into manufacturing, helping, for example, to simulate statistical variations of electrical parameters as a function of process parameters.
{"title":"Adding Manufacturability to the Quality of Results","authors":"R. Camposano","doi":"10.1109/ISQED.2006.21","DOIUrl":"https://doi.org/10.1109/ISQED.2006.21","url":null,"abstract":"Traditionally, IC designers have been able to define \"Quality of Results\" (QoR) primarily in terms of functionality, area, speed, and power. Hardly a backward glance was given to what manufacturers would do once the designs were handed off to them. Today, manufacturability has clearly joining the ranks of QoR. This is particularly true for technology nodes at 65 nanometers (nm) and below. Yield loss mechanisms, both functional and parametric, have become dependant on the design and increasingly, as geometries continue to shrink to 45nm and below, must be addressed from design to lithography to process. In this talk, we will examine some solutions being used to ensure quality in this area of concern. Topics include incorporating yield-rated cells and probabilistic methods such as statistical timing analysis to address yield losses early in the design. Test is being used for diagnosis. Routing optimization techniques such as minimizing critical areas for shorts and open circuits, wire-spreading, redundant vias and dummy metal fills improve manufacturability for metal layers. Further down the tool chain, resolution enhancement techniques (RET) used in mask synthesis addresses lithography, improving printability and hence yield. Manufacturing process knowledge is becoming increasingly important in design to enable effective yield modeling. TCAD models are making their way into manufacturing, helping, for example, to simulate statistical variations of electrical parameters as a function of process parameters.","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134100725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The chip area and delay in digital VLSI design depends on the number of transistors that are used for the logic gates involved. While the determination of a series-parallel implementation can be straightforward once a simplified expression of the function is available, this may not be an optimum solution. In the current paper an improved approach for determining a satisfactory solution for complex gates is presented. Experimental results demonstrate the efficiency of the approach
{"title":"Transistor-level optimization of supergates","authors":"D. Kagaris, T. Haniotakis","doi":"10.1109/ISQED.2006.139","DOIUrl":"https://doi.org/10.1109/ISQED.2006.139","url":null,"abstract":"The chip area and delay in digital VLSI design depends on the number of transistors that are used for the logic gates involved. While the determination of a series-parallel implementation can be straightforward once a simplified expression of the function is available, this may not be an optimum solution. In the current paper an improved approach for determining a satisfactory solution for complex gates is presented. Experimental results demonstrate the efficiency of the approach","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134478247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This tutorial discusses emerging technologie. We will focus on three major components.
本教程讨论新兴技术。我们将重点从三个方面着手。
{"title":"Tutorial 1: Emerging Technologies for VLSI Design","authors":"R. Joshi, K. Banerjee, A. DeHon","doi":"10.1109/ISQED.2006.140","DOIUrl":"https://doi.org/10.1109/ISQED.2006.140","url":null,"abstract":"This tutorial discusses emerging technologie. We will focus on three major components.","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131115762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two circuit-level techniques to efficiently yet economically improve SEU tolerance of static CMOS digital circuits. We also developed a "Robustness COmpiler (ROCO)" to integrate these techniques into the existing design flow to achieve high level of reliability at low design cost. Experiment results show that the proposed methodology is able to greatly improve the circuits' SEU tolerance with zero timing overhead and very limited area penalty
{"title":"Improving transient error tolerance of digital VLSI circuits using robustness compiler (ROCO)","authors":"Chong Zhao, S. Dey","doi":"10.1109/ISQED.2006.75","DOIUrl":"https://doi.org/10.1109/ISQED.2006.75","url":null,"abstract":"Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two circuit-level techniques to efficiently yet economically improve SEU tolerance of static CMOS digital circuits. We also developed a \"Robustness COmpiler (ROCO)\" to integrate these techniques into the existing design flow to achieve high level of reliability at low design cost. Experiment results show that the proposed methodology is able to greatly improve the circuits' SEU tolerance with zero timing overhead and very limited area penalty","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114961263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the introduction of 90 nm node technology, silicon CMOS is already at the nanoscale. There is no doubt that the semiconductor industry desires to stay on the historical rate of cost/performance/density improvement as exemplified by the International Technology Roadmap for Semiconductors (ITRS). The challenges for continued device scaling are daunting. At the highest level, the challenges are: (1) delivering cost/performance improvement while at the same time containing power consumption/dissipation, (2) control of device variations, and (3) device/circuit/system co-design and integration. New devices and new materials offer new opportunities for solving the challenges of continued improvement. In this talk, we give an overview of the device options being considered for CMOS logic technologies from 45 nm to 22 nm and beyond. Technology options include the use of device structures (multi-gate FET) and transport-enhanced channel materials (strained Si, Ge). Beyond the 22 nm node, research are underway to explore even more adventurous options such as III-V compound semiconductors as channel materials, metal Schottky source/drain. Beyond that time horizon, there is the question of whether new materials and fabrication methods such as carbon nanotubes, semiconductor nanowires and self-assembly techniques will make an impact in nanoscale CMOS technologies. We survey the state-of-the-art of these emerging devices and technologies and discuss the research opportunities going forward. We conclude with a discussion of the interaction between device design and the circuit/system architecture and how this interaction will change the landscape of technology development in the future.
{"title":"Device and Technology Challenges for Nanoscale CMOS","authors":"H. Wong","doi":"10.1109/ISQED.2006.49","DOIUrl":"https://doi.org/10.1109/ISQED.2006.49","url":null,"abstract":"With the introduction of 90 nm node technology, silicon CMOS is already at the nanoscale. There is no doubt that the semiconductor industry desires to stay on the historical rate of cost/performance/density improvement as exemplified by the International Technology Roadmap for Semiconductors (ITRS). The challenges for continued device scaling are daunting. At the highest level, the challenges are: (1) delivering cost/performance improvement while at the same time containing power consumption/dissipation, (2) control of device variations, and (3) device/circuit/system co-design and integration. New devices and new materials offer new opportunities for solving the challenges of continued improvement. In this talk, we give an overview of the device options being considered for CMOS logic technologies from 45 nm to 22 nm and beyond. Technology options include the use of device structures (multi-gate FET) and transport-enhanced channel materials (strained Si, Ge). Beyond the 22 nm node, research are underway to explore even more adventurous options such as III-V compound semiconductors as channel materials, metal Schottky source/drain. Beyond that time horizon, there is the question of whether new materials and fabrication methods such as carbon nanotubes, semiconductor nanowires and self-assembly techniques will make an impact in nanoscale CMOS technologies. We survey the state-of-the-art of these emerging devices and technologies and discuss the research opportunities going forward. We conclude with a discussion of the interaction between device design and the circuit/system architecture and how this interaction will change the landscape of technology development in the future.","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116743679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Moroz, Lee Smith, Xi-Wei Lin, D. Pramanik, G. Rollins
Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This stress is generated by a variety of intentional and unintentional stress sources. Shallow trench isolation is an example of an unintentional stress source, whereas embedded SiGe in the source and drain is an example of an intentional stress source. The amount of stress in each transistor in the circuit depends on the shape of its diffusion area as well as the density of the adjacent layout. The resulting non-uniform stress distribution alters individual transistor performance and, ultimately, the behavior of the circuit. In this paper, several examples are used to illustrate this effect based on design rules for the 45 nm technology node. A number of alternative approaches are suggested for partially suppressing or completely eliminating the stress-induced performance variations
{"title":"Stress-aware design methodology","authors":"V. Moroz, Lee Smith, Xi-Wei Lin, D. Pramanik, G. Rollins","doi":"10.1109/ISQED.2006.124","DOIUrl":"https://doi.org/10.1109/ISQED.2006.124","url":null,"abstract":"Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This stress is generated by a variety of intentional and unintentional stress sources. Shallow trench isolation is an example of an unintentional stress source, whereas embedded SiGe in the source and drain is an example of an intentional stress source. The amount of stress in each transistor in the circuit depends on the shape of its diffusion area as well as the density of the adjacent layout. The resulting non-uniform stress distribution alters individual transistor performance and, ultimately, the behavior of the circuit. In this paper, several examples are used to illustrate this effect based on design rules for the 45 nm technology node. A number of alternative approaches are suggested for partially suppressing or completely eliminating the stress-induced performance variations","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128570335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Probabilistic system simulations for analog circuits have traditionally been handled with Monte Carlo analysis. For a manufacturable design, fast and accurate simulations are necessary for time-to-market, design for manufacturability and yield concerns. In this paper, a fast and accurate probabilistic simulation alternative is proposed targeting the simulation of analog systems. The proposed method shows high accuracy for performance estimation combined with a 100-fold reduction in run-time with respect to a 1000-sample Monte Carlo analysis
{"title":"Monte Carlo-alternative probabilistic simulations for analog systems","authors":"R. Topaloglu","doi":"10.1109/ISQED.2006.90","DOIUrl":"https://doi.org/10.1109/ISQED.2006.90","url":null,"abstract":"Probabilistic system simulations for analog circuits have traditionally been handled with Monte Carlo analysis. For a manufacturable design, fast and accurate simulations are necessary for time-to-market, design for manufacturability and yield concerns. In this paper, a fast and accurate probabilistic simulation alternative is proposed targeting the simulation of analog systems. The proposed method shows high accuracy for performance estimation combined with a 100-fold reduction in run-time with respect to a 1000-sample Monte Carlo analysis","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134355303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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