While device dimensions continue to shrink into the sub-90nm range, device self-heating emerges as a pressing problem, affecting both mobility and leakage current. Coupled electro-thermal simulation can be used to assess the impact. Simulation, however, is time consuming. Furthermore, it does not give insight into the device's performance robustness against self-heating. We propose in this paper a novel metric, metric for electro-thermal sensitivity (METS), for characterizing a device's electrical robustness to self-heating. We demonstrate the effectiveness of METS in characterizing FinFETs, novel double-gate devices promising to replace traditional MOSFETs because of their reduced leakage currents. FinFETs are an ideal case study for METS as they have ultra thin bodies and are thus prone to self-heating. We show that our proposed metric, METS, is capable of characterizing the self-heating behavior of FinFETs in the on and off states
{"title":"METS: a metric for electro-thermal sensitivity, and its application to FinFETs","authors":"Brian Swahn, S. Hassoun","doi":"10.1109/ISQED.2006.86","DOIUrl":"https://doi.org/10.1109/ISQED.2006.86","url":null,"abstract":"While device dimensions continue to shrink into the sub-90nm range, device self-heating emerges as a pressing problem, affecting both mobility and leakage current. Coupled electro-thermal simulation can be used to assess the impact. Simulation, however, is time consuming. Furthermore, it does not give insight into the device's performance robustness against self-heating. We propose in this paper a novel metric, metric for electro-thermal sensitivity (METS), for characterizing a device's electrical robustness to self-heating. We demonstrate the effectiveness of METS in characterizing FinFETs, novel double-gate devices promising to replace traditional MOSFETs because of their reduced leakage currents. FinFETs are an ideal case study for METS as they have ultra thin bodies and are thus prone to self-heating. We show that our proposed metric, METS, is capable of characterizing the self-heating behavior of FinFETs in the on and off states","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129178793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As digital designs scale down into the sub-100nm regime, the effects of variations are seen to dramatically affect the behavior of the circuit. These may arise from.
随着数字设计缩小到100纳米以下的范围，变化的影响被认为会极大地影响电路的行为。这些可能来自。
{"title":"Tutorial II: Variability and Its Impact on Design","authors":"K. Bowman, M. Orshansky, S. Sapatnekar","doi":"10.1109/ISQED.2006.141","DOIUrl":"https://doi.org/10.1109/ISQED.2006.141","url":null,"abstract":"As digital designs scale down into the sub-100nm regime, the effects of variations are seen to dramatically affect the behavior of the circuit. These may arise from.","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"69 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131749134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the migration to deep sub-micron (DSM) process technologies, the static power (leakage) has become the major contributor to the design's overall power consumption. In this work, we show experiments that illustrate the significant increase in the ratio of the leakage to the total power as the DSM process nodes shrink. We also present a high-level design/synthesis method, called power islands that minimize the leakage in the circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all the logic contained within it is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. A main benefit of power islands is the elimination of leakage in inactive components during the power down cycles of the islands, and hence a decrease in circuit's power consumption. The effectiveness of the proposed technique is demonstrated through several examples implemented with 4 different feature sizes: 180 nm, 130 nm, 100 nm and 70 nm. These experiments showed improvements in leakage ranging from 41% to 80% at 70 nm due to power islands
{"title":"Power islands: a high-level technique for counteracting leakage in deep sub-micron","authors":"D. Dal, A. Nunez, N. Mansouri","doi":"10.1109/ISQED.2006.103","DOIUrl":"https://doi.org/10.1109/ISQED.2006.103","url":null,"abstract":"With the migration to deep sub-micron (DSM) process technologies, the static power (leakage) has become the major contributor to the design's overall power consumption. In this work, we show experiments that illustrate the significant increase in the ratio of the leakage to the total power as the DSM process nodes shrink. We also present a high-level design/synthesis method, called power islands that minimize the leakage in the circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all the logic contained within it is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. A main benefit of power islands is the elimination of leakage in inactive components during the power down cycles of the islands, and hence a decrease in circuit's power consumption. The effectiveness of the proposed technique is demonstrated through several examples implemented with 4 different feature sizes: 180 nm, 130 nm, 100 nm and 70 nm. These experiments showed improvements in leakage ranging from 41% to 80% at 70 nm due to power islands","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134019094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we propose a dual-Vt FPGA architecture for reduction of subthreshold leakage power. A CAD flow has been proposed based on the dual-Vt assignment algorithm and placement for realizing the dual-Vt FPGA architecture. Logic elements within the logic blocks are the candidates for dual-Vt assignment. We propose an architecture in which there are two kinds of logic blocks, one with all high-Vt logic elements and another with a fixed percentage of high-Vt logic elements. These two kinds of logic blocks are then placed in such a way that the FPGA architecture remains regular. Results indicate that in the ideal case of dual-Vt assignment, over 95% of the logic elements can be assigned high-Vt. Results show that leakage savings of 55% can be achieved. Design tradeoffs for various ratios of the two kinds of logic blocks are investigated. The dual-Vt FPGA CAD flow is intended for development and evaluation of dual-Vt FPGA architectures
{"title":"Dual-Vt design of FPGAs for subthreshold leakage tolerance","authors":"Akhilesh Kumar, M. Anis","doi":"10.1109/ISQED.2006.53","DOIUrl":"https://doi.org/10.1109/ISQED.2006.53","url":null,"abstract":"In this paper we propose a dual-Vt FPGA architecture for reduction of subthreshold leakage power. A CAD flow has been proposed based on the dual-Vt assignment algorithm and placement for realizing the dual-Vt FPGA architecture. Logic elements within the logic blocks are the candidates for dual-Vt assignment. We propose an architecture in which there are two kinds of logic blocks, one with all high-Vt logic elements and another with a fixed percentage of high-Vt logic elements. These two kinds of logic blocks are then placed in such a way that the FPGA architecture remains regular. Results indicate that in the ideal case of dual-Vt assignment, over 95% of the logic elements can be assigned high-Vt. Results show that leakage savings of 55% can be achieved. Design tradeoffs for various ratios of the two kinds of logic blocks are investigated. The dual-Vt FPGA CAD flow is intended for development and evaluation of dual-Vt FPGA architectures","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134301694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper deals with diagnosis and design for diagnosability at the system level. In particular, diagnosis and design for diagnosability of high-end Internet routers in manufacturing test and design validation are considered. A packet flow model is used for diagnosis down to the replaceable unit level. The diagnosis method operates correctly when there are multiple or intermittent faults. A diagnosability criterion is proposed and a method for assessing diagnosability of various designs given. The paper concludes with a description of empirical results from an industrial application of the diagnosis method
{"title":"Diagnosis and design for diagnosability for Internet routers","authors":"L. Barford","doi":"10.1109/ISQED.2006.51","DOIUrl":"https://doi.org/10.1109/ISQED.2006.51","url":null,"abstract":"This paper deals with diagnosis and design for diagnosability at the system level. In particular, diagnosis and design for diagnosability of high-end Internet routers in manufacturing test and design validation are considered. A packet flow model is used for diagnosis down to the replaceable unit level. The diagnosis method operates correctly when there are multiple or intermittent faults. A diagnosability criterion is proposed and a method for assessing diagnosability of various designs given. The paper concludes with a description of empirical results from an industrial application of the diagnosis method","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134399644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliability of commercial electronics. For the first time, a fast and accurate methodology FASER based on static, vector-less analysis of error rates due to single event upsets in general combinational circuits is proposed. Accurate models are based on STA-like pre-characterization methods, and logical masking is computed via binary decision diagrams with circuit partitioning. Experimental results indicate that FASER achieves good accuracy compared to the SPICE-based simulation method. The average error across the benchmark circuits is 12% at over 90,000X speed-up. The accuracy can be further improved by more accurate cell library characterization. The run-time for ISCAS '85 benchmark circuits ranges from 10 to 120 minutes. The estimated bit error rate (BER) for the ISCAS'85 benchmark circuits implemented in the 100nm CMOS technology is about 10-5 FIT
本文关注的是静态分析任意组合电路对单事件扰动的敏感性，这已成为商业电子产品可靠性的一个重要问题。首次提出了一种基于静态、无矢量分析一般组合电路中单事件扰动错误率的快速、准确方法FASER。精确的模型基于类似sta的预表征方法，逻辑掩蔽是通过带有电路划分的二进制决策图计算的。实验结果表明，与基于spice的仿真方法相比，FASER获得了较好的精度。在超过90,000倍的加速下，基准电路的平均误差为12%。通过更精确的细胞库表征，可以进一步提高准确性。ISCAS '85基准电路的运行时间范围从10到120分钟。在100nm CMOS技术中实现的ISCAS'85基准电路的估计误码率(BER)约为10-5 FIT
{"title":"FASER: fast analysis of soft error susceptibility for cell-based designs","authors":"Bin Zhang, Wei-Shen Wang, M. Orshansky","doi":"10.1109/ISQED.2006.64","DOIUrl":"https://doi.org/10.1109/ISQED.2006.64","url":null,"abstract":"This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliability of commercial electronics. For the first time, a fast and accurate methodology FASER based on static, vector-less analysis of error rates due to single event upsets in general combinational circuits is proposed. Accurate models are based on STA-like pre-characterization methods, and logical masking is computed via binary decision diagrams with circuit partitioning. Experimental results indicate that FASER achieves good accuracy compared to the SPICE-based simulation method. The average error across the benchmark circuits is 12% at over 90,000X speed-up. The accuracy can be further improved by more accurate cell library characterization. The run-time for ISCAS '85 benchmark circuits ranges from 10 to 120 minutes. The estimated bit error rate (BER) for the ISCAS'85 benchmark circuits implemented in the 100nm CMOS technology is about 10-5 FIT","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134267249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new test set embedding method with re-seeding for scan-based testing is proposed. The bit sequences of multiple cells of an LFSR, which is used as test pattern generator, are exploited for effectively encoding the test set of the core under test (multiphase architecture). A new algorithm which comprises four heuristic criteria is introduced for efficiently selecting the required seeds and LFSR cells. Also, a cost metric for assessing the quality of the algorithm's results is proposed. By using this metric, the process of determining proper values for the algorithm's input parameters is significantly simplified. The proposed method compares favorably with the most recent and effective test set embedding techniques in the literature
{"title":"Efficient multiphase test set embedding for scan-based testing","authors":"E. Kalligeros, X. Kavousianos, D. Nikolos","doi":"10.1109/ISQED.2006.56","DOIUrl":"https://doi.org/10.1109/ISQED.2006.56","url":null,"abstract":"In this paper, a new test set embedding method with re-seeding for scan-based testing is proposed. The bit sequences of multiple cells of an LFSR, which is used as test pattern generator, are exploited for effectively encoding the test set of the core under test (multiphase architecture). A new algorithm which comprises four heuristic criteria is introduced for efficiently selecting the required seeds and LFSR cells. Also, a cost metric for assessing the quality of the algorithm's results is proposed. By using this metric, the process of determining proper values for the algorithm's input parameters is significantly simplified. The proposed method compares favorably with the most recent and effective test set embedding techniques in the literature","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134533442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Scratch-pad memories (SPMs) are important storage components in many embedded applications and used as an alternative or a complimentary storage to on-chip cache memories. One of the most critical issues in the context of SPMs is to select the data elements to place in them since the gap between SPM access latencies and off-chip memory access latencies keep increasing dramatically. Previous research considered this problem and attacked it using both static and dynamic schemes. Most of the prior efforts on data SPMs have mainly focused on single application scenarios, i.e., the SPM space available is assumed to be managed by a single application at any given time. While this assumption makes sense in certain domains, there also exist many cases where multiple applications need to share the same SPM space. This paper focuses on such a multi-application scenario and proposes a nonuniform SPM space partitioning and management across concurrently-executing applications. In our approach, the amount of data to be allocated to each application is decided based on the data reuse each application exhibits
{"title":"Shared scratch-pad memory space management","authors":"O. Ozturk, M. Kandemir, I. Kolcu","doi":"10.1109/ISQED.2006.115","DOIUrl":"https://doi.org/10.1109/ISQED.2006.115","url":null,"abstract":"Scratch-pad memories (SPMs) are important storage components in many embedded applications and used as an alternative or a complimentary storage to on-chip cache memories. One of the most critical issues in the context of SPMs is to select the data elements to place in them since the gap between SPM access latencies and off-chip memory access latencies keep increasing dramatically. Previous research considered this problem and attacked it using both static and dynamic schemes. Most of the prior efforts on data SPMs have mainly focused on single application scenarios, i.e., the SPM space available is assumed to be managed by a single application at any given time. While this assumption makes sense in certain domains, there also exist many cases where multiple applications need to share the same SPM space. This paper focuses on such a multi-application scenario and proposes a nonuniform SPM space partitioning and management across concurrently-executing applications. In our approach, the amount of data to be allocated to each application is decided based on the data reuse each application exhibits","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124935884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their "expected delay" over input data space. This paradigm shift calls for customized statistical design techniques to replace the conventional pessimistic worst case analysis methodologies. Statistical design methods can provide a realistic assessment of design space, and improve the design quality by exploiting its stochastic behavior. We present a novel probabilistic time budgeting algorithm that translates the application expected delay constraint into its components delay constraints. Our algorithm which is based on mathematical properties of the problem, determines the optimal maximum weighted timing relaxation of an application under expected delay constraint. Experimental results on core-based synthesis of several multi-media applications on FPGAs show about 20% and 19% average energy and area improvement, respectively
{"title":"Probabilistic delay budgeting for soft realtime applications","authors":"S. Ghiasi, Po-Kuan Huang","doi":"10.1109/ISQED.2006.106","DOIUrl":"https://doi.org/10.1109/ISQED.2006.106","url":null,"abstract":"Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their \"expected delay\" over input data space. This paradigm shift calls for customized statistical design techniques to replace the conventional pessimistic worst case analysis methodologies. Statistical design methods can provide a realistic assessment of design space, and improve the design quality by exploiting its stochastic behavior. We present a novel probabilistic time budgeting algorithm that translates the application expected delay constraint into its components delay constraints. Our algorithm which is based on mathematical properties of the problem, determines the optimal maximum weighted timing relaxation of an application under expected delay constraint. Experimental results on core-based synthesis of several multi-media applications on FPGAs show about 20% and 19% average energy and area improvement, respectively","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124288860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design for manufacturability (DFM) is becoming increasingly important as process geometries shrink. Conventional design rule pass/fail is not adequate to quantify DFM compliance. Instead, metrics are needed to compare designs. Yield might be an ideal metric, but is difficult to calculate objectively without significant manufacturing data. This paper investigates the qualities that good metrics require and shows an example of an approach that seems promising
{"title":"DFM metrics for standard cells","authors":"R. Aitken","doi":"10.1109/ISQED.2006.50","DOIUrl":"https://doi.org/10.1109/ISQED.2006.50","url":null,"abstract":"Design for manufacturability (DFM) is becoming increasingly important as process geometries shrink. Conventional design rule pass/fail is not adequate to quantify DFM compliance. Instead, metrics are needed to compare designs. Yield might be an ideal metric, but is difficult to calculate objectively without significant manufacturing data. This paper investigates the qualities that good metrics require and shows an example of an approach that seems promising","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116013673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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