With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful design in scan cell placement and chain ordering, circuits consume much more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present an approach to simultaneously minimizing power and routing cost in scan chain reordering after cell placement. We formulate the problem as a traveling salesman problem (TSP), different cost evaluation from (Bonhomme et al., 2004), (Bonhomme et al., 2003), and apply an efficient heuristic to solve it. The experimental results are encouraging. Compared with a recent result in (Bonhomme et al., 2004), which uses the approach with clustering overhead, we obtain up to 10% average power saving under the same low routing cost Furthermore, we obtain 57% routing cost improvement under the same test power consumption in s9234, one of ISCAS'89 benchmarks. We collaborate multiple scan chains architecture with our methodology and obtain good results as well
凭借先进的深亚微米(DSM) VLSI制造技术，我们可以将整个电子系统集成在单芯片(SoC)上。由于SoC设计的复杂性，电路的可测试性成为最具挑战性的工作之一。如果没有仔细设计扫描单元的位置和链的排序，电路在测试模式下比在正常功能模式下消耗更多的功率。这种提高的测试功率可能会导致包括总产量损失和瞬间电路损坏在内的问题。在本文中，我们提出了一种在单元放置后扫描链重新排序中同时最小化功耗和路由成本的方法。我们将问题表述为旅行推销员问题(TSP)，不同于(Bonhomme et al.， 2004)， (Bonhomme et al.， 2003)的成本评估，并应用有效的启发式方法来解决它。实验结果令人鼓舞。与最近在(Bonhomme et al.， 2004)中使用集群开销方法的结果相比，我们在相同的低路由成本下获得了高达10%的平均功耗节省。此外，在isas '89基准之一的s9234中，我们在相同的测试功耗下获得了57%的路由成本改进。我们将多个扫描链架构与我们的方法协作，并获得了良好的结果
{"title":"On optimizing scan testing power and routing cost in scan chain design","authors":"L. Hsu, Hung-Ming Chen","doi":"10.1109/ISQED.2006.95","DOIUrl":"https://doi.org/10.1109/ISQED.2006.95","url":null,"abstract":"With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful design in scan cell placement and chain ordering, circuits consume much more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present an approach to simultaneously minimizing power and routing cost in scan chain reordering after cell placement. We formulate the problem as a traveling salesman problem (TSP), different cost evaluation from (Bonhomme et al., 2004), (Bonhomme et al., 2003), and apply an efficient heuristic to solve it. The experimental results are encouraging. Compared with a recent result in (Bonhomme et al., 2004), which uses the approach with clustering overhead, we obtain up to 10% average power saving under the same low routing cost Furthermore, we obtain 57% routing cost improvement under the same test power consumption in s9234, one of ISCAS'89 benchmarks. We collaborate multiple scan chains architecture with our methodology and obtain good results as well","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128105235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power consumption and enhancing evaluation speed and noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full voltage swing signals are maintained at inputs and outputs for robust and high speed operation. Power supply, ground, and threshold voltages are simultaneously optimized to minimize the power-delay product (PDP). The proposed technique reduces the PDP by up to 51.9% as compared to the standard full-swing circuits in a 45nm CMOS technology. The active mode power consumption is reduced by up to 40.4% due to the lower switching power required to charge/discharge the dynamic node. Furthermore, the evaluation speed and noise immunity are enhanced by up to 19.4% and 39.1%, respectively, as compared to the standard full-swing circuits. The proposed low swing technique also reduces the idle mode leakage power consumption of high fan-in domino gates by up to 84.2%
{"title":"Robust dynamic node low voltage swing domino logic with multiple threshold voltages","authors":"Zhiyu Liu, V. Kursun","doi":"10.1109/ISQED.2006.112","DOIUrl":"https://doi.org/10.1109/ISQED.2006.112","url":null,"abstract":"A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power consumption and enhancing evaluation speed and noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full voltage swing signals are maintained at inputs and outputs for robust and high speed operation. Power supply, ground, and threshold voltages are simultaneously optimized to minimize the power-delay product (PDP). The proposed technique reduces the PDP by up to 51.9% as compared to the standard full-swing circuits in a 45nm CMOS technology. The active mode power consumption is reduced by up to 40.4% due to the lower switching power required to charge/discharge the dynamic node. Furthermore, the evaluation speed and noise immunity are enhanced by up to 19.4% and 39.1%, respectively, as compared to the standard full-swing circuits. The proposed low swing technique also reduces the idle mode leakage power consumption of high fan-in domino gates by up to 84.2%","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131511348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
On-chip serial link buses have been previously proposed as a strong solution to reduce the complexity and/or the energy dissipation of on-chip interconnect fabrics. However, it was noticed that serializing m-bits on a single interconnect (serial-link) increases the overall data switching activity. This paper presents a quantitative analysis of the switching activity of serial links, and provides closed form expressions for the average activity factors. Two transition encoding schemes, to reduce the activity factor of serial links, are discussed and analyzed. The impact of the encoding schemes on the MCF between neighboring interconnects is also discussed. The analysis shows that both of the schemes provide significant reduction in the average activity factor and energy dissipation reduction, but each in a different range of input activity factors. The two encoding bus schemes were modeled in a 70nm CMOS technology, and compared to an unencoded serial link bus and a parallel line bus. Simulation results show that the transition encoded bus schemes reduce the overall energy dissipation of the unencoded serial link bus by up to 96%
{"title":"Reducing the data switching activity on serial link buses","authors":"M. Ghoneima, Y. Ismail, M. Khellah, V. De","doi":"10.1109/ISQED.2006.111","DOIUrl":"https://doi.org/10.1109/ISQED.2006.111","url":null,"abstract":"On-chip serial link buses have been previously proposed as a strong solution to reduce the complexity and/or the energy dissipation of on-chip interconnect fabrics. However, it was noticed that serializing m-bits on a single interconnect (serial-link) increases the overall data switching activity. This paper presents a quantitative analysis of the switching activity of serial links, and provides closed form expressions for the average activity factors. Two transition encoding schemes, to reduce the activity factor of serial links, are discussed and analyzed. The impact of the encoding schemes on the MCF between neighboring interconnects is also discussed. The analysis shows that both of the schemes provide significant reduction in the average activity factor and energy dissipation reduction, but each in a different range of input activity factors. The two encoding bus schemes were modeled in a 70nm CMOS technology, and compared to an unencoded serial link bus and a parallel line bus. Simulation results show that the transition encoded bus schemes reduce the overall energy dissipation of the unencoded serial link bus by up to 96%","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133624048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we illustrate that the traditional N-detect ATPG is unoptimized in terms of the size of the generated pattern set. The optimization problem is formulated as a minimum covering problem. Integer linear programming (ILP) is applied to obtain an N-detection ATPG pattern set with the minimum number of patterns. A heuristic method is also proposed to obtain sub-optimal solutions efficiently. Experimental results demonstrate that by using the proposed method, the number of N-detection patterns can be reduced by about 18% for N=3 and about 13% for N=5 without compromising N-detection objective
{"title":"On N-detect pattern set optimization","authors":"Yu Huang","doi":"10.1109/ISQED.2006.94","DOIUrl":"https://doi.org/10.1109/ISQED.2006.94","url":null,"abstract":"In this paper, we illustrate that the traditional N-detect ATPG is unoptimized in terms of the size of the generated pattern set. The optimization problem is formulated as a minimum covering problem. Integer linear programming (ILP) is applied to obtain an N-detection ATPG pattern set with the minimum number of patterns. A heuristic method is also proposed to obtain sub-optimal solutions efficiently. Experimental results demonstrate that by using the proposed method, the number of N-detection patterns can be reduced by about 18% for N=3 and about 13% for N=5 without compromising N-detection objective","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115767505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance improvements. While high power consumption brings many problems with it, high power density and thermal hotspots are maybe two of the most important ones. Current architectures provide several circuit based solutions to cope with thermal emergencies when they occur but exercising them frequently can lead to significant performance losses. This paper proposes a compiler-based approach that balances the computational workload across the processors of a NoC based chip multiprocessor such that the chances of experiencing a thermal emergency at runtime are reduced. Our results show that the proposed approach cuts the number of runtime thermal emergencies by 42% on the average on benchmarks tested
{"title":"Compiler-directed power density reduction in NoC-based multicore designs","authors":"S. Narayanan, M. Kandemir, O. Ozturk","doi":"10.1109/ISQED.2006.36","DOIUrl":"https://doi.org/10.1109/ISQED.2006.36","url":null,"abstract":"As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance improvements. While high power consumption brings many problems with it, high power density and thermal hotspots are maybe two of the most important ones. Current architectures provide several circuit based solutions to cope with thermal emergencies when they occur but exercising them frequently can lead to significant performance losses. This paper proposes a compiler-based approach that balances the computational workload across the processors of a NoC based chip multiprocessor such that the chances of experiencing a thermal emergency at runtime are reduced. Our results show that the proposed approach cuts the number of runtime thermal emergencies by 42% on the average on benchmarks tested","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124253368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the future, the peak temperature of a chip will be a primary design constraint. In order to meet this constraint, temperature must be considered in the earliest phases of the design process. Using a newly developed thermal analysis tool, HS3d, this work explores the thermal profile of devices as technology varies. We show that as technology scales, the hotspot locations can shift from the units with the most switching activity to those with the most low-threshold transistors. We further note that process variations in leakage dominated technologies can result in significant variations in the hotspot locations, indicating that feedback from thermal sensors will be very important. Finally, this work examines the thermal effects of multi-layer device stacking technologies, and finds that the vertical temperature difference between layers is much less significant than the horizontal differences due to power density, and as such, vertical placement optimizations will have much smaller impact on hotspot development than a uniform power distribution
{"title":"Thermal trends in emerging technologies","authors":"G. Link, N. Vijaykrishnan","doi":"10.1109/ISQED.2006.136","DOIUrl":"https://doi.org/10.1109/ISQED.2006.136","url":null,"abstract":"In the future, the peak temperature of a chip will be a primary design constraint. In order to meet this constraint, temperature must be considered in the earliest phases of the design process. Using a newly developed thermal analysis tool, HS3d, this work explores the thermal profile of devices as technology varies. We show that as technology scales, the hotspot locations can shift from the units with the most switching activity to those with the most low-threshold transistors. We further note that process variations in leakage dominated technologies can result in significant variations in the hotspot locations, indicating that feedback from thermal sensors will be very important. Finally, this work examines the thermal effects of multi-layer device stacking technologies, and finds that the vertical temperature difference between layers is much less significant than the horizontal differences due to power density, and as such, vertical placement optimizations will have much smaller impact on hotspot development than a uniform power distribution","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123957232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bhaskar J. Karmakar, V. Chakravarty, R. Venkatraman, J. Rao
Design of state-of-the-art SoCs often require multiple design data handoffs between sub-teams involved in its development. Handoff quality issues account for a significant portion of the wasted effort during SoC development-principally due to completeness, correctness and consistency of different elements of the handoff. Such issues impact silicon quality and schedule predictability, due to the re-work effort involved. HandoffQC has been developed as an integrated QC system to qualify incoming handoffs, which ensures handoff and silicon issues are detected and fixed up-front. HandoffQC also allows for applying learnings from one design to the next, promoting continuous process improvement. The system has been architected to be easily extensible in terms of the quality checks, is user configurable and can easily be integrated into design flows. HandoffQC has been deployed on many production designs where it has successfully identified several handoff and potential silicon issues before they resulted in downstream design re-work
{"title":"Enabling quality and schedule predictability in SoC design using HandoffQC","authors":"Bhaskar J. Karmakar, V. Chakravarty, R. Venkatraman, J. Rao","doi":"10.1109/ISQED.2006.59","DOIUrl":"https://doi.org/10.1109/ISQED.2006.59","url":null,"abstract":"Design of state-of-the-art SoCs often require multiple design data handoffs between sub-teams involved in its development. Handoff quality issues account for a significant portion of the wasted effort during SoC development-principally due to completeness, correctness and consistency of different elements of the handoff. Such issues impact silicon quality and schedule predictability, due to the re-work effort involved. HandoffQC has been developed as an integrated QC system to qualify incoming handoffs, which ensures handoff and silicon issues are detected and fixed up-front. HandoffQC also allows for applying learnings from one design to the next, promoting continuous process improvement. The system has been architected to be easily extensible in terms of the quality checks, is user configurable and can easily be integrated into design flows. HandoffQC has been deployed on many production designs where it has successfully identified several handoff and potential silicon issues before they resulted in downstream design re-work","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125833189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an automatic structure synthesis technique by partitioning of the analog and mixed-signal circuit models. It translates a behavioral-level analog description written in VHDL-AMS into a structure-level VHDL-AMS specification based on a set of behavioral analog primitives. It is one of the three techniques in our proposed hierarchical methodology for supporting high-level analog synthesis
{"title":"Structure synthesis of analog and mixed-signal circuits using partition techniques","authors":"K. Zeng, S. Huss","doi":"10.1109/ISQED.2006.125","DOIUrl":"https://doi.org/10.1109/ISQED.2006.125","url":null,"abstract":"This paper presents an automatic structure synthesis technique by partitioning of the analog and mixed-signal circuit models. It translates a behavioral-level analog description written in VHDL-AMS into a structure-level VHDL-AMS specification based on a set of behavioral analog primitives. It is one of the three techniques in our proposed hierarchical methodology for supporting high-level analog synthesis","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125072171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a novel methodology for improving the leakage yield of digital circuits in the presence of process variations and under probabilistic timing constraints. The leakage minimization problem is formulated as a discrete optimization problem, where a suitable configuration for each gate in the circuit is selected from a standard-cell library consisting of different implementations of each type of gate. A function of mean and variance of the circuit leakage is minimized with constraint on a-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables in addition to gate sizes can provide significant power savings. We propose efficient techniques for computing delay and leakage power gradients which form the basis of the optimization algorithm. Results on various trade-offs such as between leakage and delay, and mean and variance of the leakage are discussed
{"title":"LOTUS: leakage optimization under timing uncertainty for standard-cell designs","authors":"Sarvesh Bhardwaj, Yu Cao, S. Vrudhula","doi":"10.1109/ISQED.2006.83","DOIUrl":"https://doi.org/10.1109/ISQED.2006.83","url":null,"abstract":"This paper proposes a novel methodology for improving the leakage yield of digital circuits in the presence of process variations and under probabilistic timing constraints. The leakage minimization problem is formulated as a discrete optimization problem, where a suitable configuration for each gate in the circuit is selected from a standard-cell library consisting of different implementations of each type of gate. A function of mean and variance of the circuit leakage is minimized with constraint on a-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables in addition to gate sizes can provide significant power savings. We propose efficient techniques for computing delay and leakage power gradients which form the basis of the optimization algorithm. Results on various trade-offs such as between leakage and delay, and mean and variance of the leakage are discussed","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129139970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper a technique is proposed to estimate the level of difficulty of formally verifying an RTL circuit. The technique is based on extensive experimental data generated from a wide range of industrial and academic benchmarks. Statistical as well as intuitive inferences have been drawn from the data to obtain an algorithm that can classify the level of difficulty of formally verifying a property on a particular circuit into five broad categories. The difficulty of verifying the whole circuit is a weighted average of the difficulty of verifying its individual properties. The level of coverage generated by the properties gives us a confidence level on the accuracy of the metric
{"title":"A technique for estimating the difficulty of a formal verification problem","authors":"Indradeep Ghosh, M. Prasad","doi":"10.1109/ISQED.2006.17","DOIUrl":"https://doi.org/10.1109/ISQED.2006.17","url":null,"abstract":"In this paper a technique is proposed to estimate the level of difficulty of formally verifying an RTL circuit. The technique is based on extensive experimental data generated from a wide range of industrial and academic benchmarks. Statistical as well as intuitive inferences have been drawn from the data to obtain an algorithm that can classify the level of difficulty of formally verifying a property on a particular circuit into five broad categories. The difficulty of verifying the whole circuit is a weighted average of the difficulty of verifying its individual properties. The level of coverage generated by the properties gives us a confidence level on the accuracy of the metric","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126959383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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