In this paper, we propose a via distribution model for yield estimation. The proposed model expresses a relationship between the number of vias and wire length. We can also estimate the total number of vias in a circuit, which is derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from a gate-level netlist and layout area. We extract model parameters from the commercial chips designed for 0.18-mum and 0.13-mum CMOS processes, and demonstrate yield degradation caused by vias
在本文中，我们提出了一个通过分布模型来估计产量。所提出的模型表达了过孔数与导线长度之间的关系。我们还可以估计电路中的通孔总数，这是由通孔分布和导线长度分布得出的。通道分布是轨道利用率的函数，线长分布可以从门级网表和布局区域导出。我们从为0.18和0.13 μ m CMOS工艺设计的商用芯片中提取模型参数，并证明了过孔导致的良率下降
{"title":"Via distribution model for yield estimation","authors":"T. Uezono, K. Okada, K. Masu","doi":"10.1109/ISQED.2006.144","DOIUrl":"https://doi.org/10.1109/ISQED.2006.144","url":null,"abstract":"In this paper, we propose a via distribution model for yield estimation. The proposed model expresses a relationship between the number of vias and wire length. We can also estimate the total number of vias in a circuit, which is derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from a gate-level netlist and layout area. We extract model parameters from the commercial chips designed for 0.18-mum and 0.13-mum CMOS processes, and demonstrate yield degradation caused by vias","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122420774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design for manufacturability (DfM) is a design verification methodology linked to a set of requirements that can be perceived as gray area within the design rule check (DRC) approach based on rigid pass/fail criteria. This is because the DfM rules, unlike DRC, are not directly responsible for the functionality of individual devices, but are broadly scoped to address the die yield over the process corners. At the same time, all design rules are to ensure high performance and profit margins. Therefore, the distinction between DfM and DRC rules is often artificial and confusing. In this paper, we propose how to combine all design rules into one enforceable deck, regardless of their origin, and introduce an implementation cutoff lines decided by technology and business factors. This new methodology is based on the failure mode and effect analysis (FMEA) and return on investment (RoI). FMEA, involving the criticality, occurrence, and detectability of failure modes, is demonstrated for DfM rules focused on system on chip (SoC). The results are then correlated to those of the RoI approach for the same set of rules
{"title":"Question: DRC or DfM? Answer: FMEA and ROI","authors":"A. Balasinski","doi":"10.1109/ISQED.2006.110","DOIUrl":"https://doi.org/10.1109/ISQED.2006.110","url":null,"abstract":"Design for manufacturability (DfM) is a design verification methodology linked to a set of requirements that can be perceived as gray area within the design rule check (DRC) approach based on rigid pass/fail criteria. This is because the DfM rules, unlike DRC, are not directly responsible for the functionality of individual devices, but are broadly scoped to address the die yield over the process corners. At the same time, all design rules are to ensure high performance and profit margins. Therefore, the distinction between DfM and DRC rules is often artificial and confusing. In this paper, we propose how to combine all design rules into one enforceable deck, regardless of their origin, and introduce an implementation cutoff lines decided by technology and business factors. This new methodology is based on the failure mode and effect analysis (FMEA) and return on investment (RoI). FMEA, involving the criticality, occurrence, and detectability of failure modes, is demonstrated for DfM rules focused on system on chip (SoC). The results are then correlated to those of the RoI approach for the same set of rules","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121313318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Although industry-wide adoption of 65nm technology is in its infancy, major foundries have started developing design kits for the 65nm base. For designers, this means managing new and complex process variability and interconnect issues, relevant to specific design flows, using advanced parasitic extraction methodologies
{"title":"The challenges and impact of parasitic extraction at 65 nm","authors":"K. Chow","doi":"10.1109/ISQED.2006.133","DOIUrl":"https://doi.org/10.1109/ISQED.2006.133","url":null,"abstract":"Although industry-wide adoption of 65nm technology is in its infancy, major foundries have started developing design kits for the 65nm base. For designers, this means managing new and complex process variability and interconnect issues, relevant to specific design flows, using advanced parasitic extraction methodologies","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127885184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design of a low input (0.75 to 1.75V) and low power dissipation pipelined CMOS ADC. The 8 bits ADC consumes 78.3mW power at 2.5V supply voltage. The DNL and INL are 0.6LSB and 0.7LSB respectively, and SFDR is 51.259dB at 195kHz input frequency. The chip area is 1.023 mm times 0.795 mm with TSMC0.25mum CMOS technology
本文设计了一种低输入(0.75 ~ 1.75V)、低功耗的流水线CMOS ADC。8位ADC在2.5V电源电压下消耗78.3mW功率。在195kHz输入频率下，DNL和INL分别为0.6LSB和0.7LSB, SFDR为51.259dB。采用TSMC0.25mum CMOS技术，芯片面积为1.023 mm × 0.795 mm
{"title":"A low input, low-power dissipation CMOS ADC","authors":"Biye Wang, Lili He, Morris Jones","doi":"10.1109/ISQED.2006.11","DOIUrl":"https://doi.org/10.1109/ISQED.2006.11","url":null,"abstract":"This paper presents the design of a low input (0.75 to 1.75V) and low power dissipation pipelined CMOS ADC. The 8 bits ADC consumes 78.3mW power at 2.5V supply voltage. The DNL and INL are 0.6LSB and 0.7LSB respectively, and SFDR is 51.259dB at 195kHz input frequency. The chip area is 1.023 mm times 0.795 mm with TSMC0.25mum CMOS technology","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132807273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and physical correlations among model parameters, must be included. In addition, predictions across technology generations should be smooth to make continuous extrapolations. In this work, a new generation of predictive technology model (PTM) is developed to accomplish these goals. Based on physical models and early stage silicon data, PTM of bulk CMOS for 130nm to 32nm technology nodes is successfully generated. By tuning ten parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified: for NMOS, the error of Ion is 2% and for PMOS, it is 5%. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. A webpage has been established for the release of PTM (http://www.eas.asu.edu/~ptm)
{"title":"New generation of predictive technology model for sub-45nm design exploration","authors":"Wei Zhao, Yu Cao","doi":"10.1109/ISQED.2006.91","DOIUrl":"https://doi.org/10.1109/ISQED.2006.91","url":null,"abstract":"Predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and physical correlations among model parameters, must be included. In addition, predictions across technology generations should be smooth to make continuous extrapolations. In this work, a new generation of predictive technology model (PTM) is developed to accomplish these goals. Based on physical models and early stage silicon data, PTM of bulk CMOS for 130nm to 32nm technology nodes is successfully generated. By tuning ten parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified: for NMOS, the error of Ion is 2% and for PMOS, it is 5%. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. A webpage has been established for the release of PTM (http://www.eas.asu.edu/~ptm)","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131615491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chao-Yang Yeh, G. Wilke, Hongyu Chen, S. Reddy, Hoa-van Nguyen, T. Miyoshi, W. Walker, R. Murgai
This paper evaluates and compares different clock architectures such as mesh, tree and their hybrids, on several industrial designs. The goal of our study is to gain a quantitative understanding of engineering trade-offs between different architectures with respect to clock skew, latency, timing uncertainty, and power. This understanding will lead to guidelines for determining the best clock architecture for the design specification and constraints. To the best of our knowledge, no work has been published on evaluating and comparing these architectures on real industrial designs. Our study shows that mesh-based architectures are better than tree architectures for skew (< 1ps skew) and are more robust to variations (18% reduction in timing uncertainty as compared to tree). The power penalty associated with a mesh as compared to a tree was found to be between 10-40%. Use of multiple meshes can help reduce the power penalty
{"title":"Clock distribution architectures: a comparative study","authors":"Chao-Yang Yeh, G. Wilke, Hongyu Chen, S. Reddy, Hoa-van Nguyen, T. Miyoshi, W. Walker, R. Murgai","doi":"10.1109/ISQED.2006.33","DOIUrl":"https://doi.org/10.1109/ISQED.2006.33","url":null,"abstract":"This paper evaluates and compares different clock architectures such as mesh, tree and their hybrids, on several industrial designs. The goal of our study is to gain a quantitative understanding of engineering trade-offs between different architectures with respect to clock skew, latency, timing uncertainty, and power. This understanding will lead to guidelines for determining the best clock architecture for the design specification and constraints. To the best of our knowledge, no work has been published on evaluating and comparing these architectures on real industrial designs. Our study shows that mesh-based architectures are better than tree architectures for skew (< 1ps skew) and are more robust to variations (18% reduction in timing uncertainty as compared to tree). The power penalty associated with a mesh as compared to a tree was found to be between 10-40%. Use of multiple meshes can help reduce the power penalty","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122565895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Bickford, J. Hibbeler, Markus Bühler, J. Koehl, D. Müller, Sven Peyer, C. Schulte
Technology migration from 130 nm to 90 nm has resulted in increased yield loss caused by opens in wiring interconnects and vias. Sensitivity to these defects can be significantly reduced through the use of design methodologies that use arbitrary networks with high degrees of redundancy instead of trees for signal wires. In this paper we describe a technique that improves yield by adding via redundancy through the use of local loops. The commonly used practice of inserting a second via adjacent to an existing via can only be applied to a limited number of vias, generates wrong-way wiring, and does not significantly reduce critical area because of the proximity of the two vias. Industry examples are cited to show that use of local loops to create redundancy reduces critical area, does not require wrong-way wiring, and achieves a higher percent of redundant vias. Addition of local loops does not impact timing or wireability of the design
{"title":"Yield improvement by local wiring redundancy","authors":"J. Bickford, J. Hibbeler, Markus Bühler, J. Koehl, D. Müller, Sven Peyer, C. Schulte","doi":"10.1109/ISQED.2006.148","DOIUrl":"https://doi.org/10.1109/ISQED.2006.148","url":null,"abstract":"Technology migration from 130 nm to 90 nm has resulted in increased yield loss caused by opens in wiring interconnects and vias. Sensitivity to these defects can be significantly reduced through the use of design methodologies that use arbitrary networks with high degrees of redundancy instead of trees for signal wires. In this paper we describe a technique that improves yield by adding via redundancy through the use of local loops. The commonly used practice of inserting a second via adjacent to an existing via can only be applied to a limited number of vias, generates wrong-way wiring, and does not significantly reduce critical area because of the proximity of the two vias. Industry examples are cited to show that use of local loops to create redundancy reduces critical area, does not require wrong-way wiring, and achieves a higher percent of redundant vias. Addition of local loops does not impact timing or wireability of the design","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122998139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating fill can be reliably extracted by 3D field solvers only. Due to poor understanding of the impact of floating fill on capacitance, designers insert floating fill conservatively. In this paper we study the impact of floating fill insertion on coupling and total capacitance when the fill geometry, and both the interconnects between which the capacitance is measured are on the same layer. We show that the capacitance with same-layer neighboring interconnects is a large fraction of total capacitance, and that it is significantly affected by fill geometries on the same layer. We analyze the effect of fill configuration parameters such as fill size, fill location, interconnect width, interconnect spacing, etc. and consider edge effects and effects occurring due to insertion of several fill geometries in close proximity. Based on our findings, we propose certain guidelines to achieve high metal density while having smaller impact on interconnect capacitance. Finally, we validate the proposed guidelines using representative process parameters and a 3D field solver. On average coupling capacitance increase due to floating-fill insertion decreases by ~ 53% on using the proposed guidelines
{"title":"Study of floating fill impact on interconnect capacitance","authors":"A. Kahng, K. Samadi, P. Sharma","doi":"10.1109/ISQED.2006.126","DOIUrl":"https://doi.org/10.1109/ISQED.2006.126","url":null,"abstract":"It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating fill can be reliably extracted by 3D field solvers only. Due to poor understanding of the impact of floating fill on capacitance, designers insert floating fill conservatively. In this paper we study the impact of floating fill insertion on coupling and total capacitance when the fill geometry, and both the interconnects between which the capacitance is measured are on the same layer. We show that the capacitance with same-layer neighboring interconnects is a large fraction of total capacitance, and that it is significantly affected by fill geometries on the same layer. We analyze the effect of fill configuration parameters such as fill size, fill location, interconnect width, interconnect spacing, etc. and consider edge effects and effects occurring due to insertion of several fill geometries in close proximity. Based on our findings, we propose certain guidelines to achieve high metal density while having smaller impact on interconnect capacitance. Finally, we validate the proposed guidelines using representative process parameters and a 3D field solver. On average coupling capacitance increase due to floating-fill insertion decreases by ~ 53% on using the proposed guidelines","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121203633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. The key idea is thus to realize and deploy different types of six-transistor SRAM cells corresponding to different threshold voltage assignments for individual transistors in the cell. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs no area or delay overhead. In addition, it results only in a slight change in the SRAM design flow. Finally, it improves the static noise margin under process variations. Experimental results show that this technique can reduce the leakage-power dissipation of a 64Kb SRAM by more than 35%
{"title":"Low-leakage SRAM design with dual V/sub t/ transistors","authors":"B. Amelifard, F. Fallah, Massoud Pedram","doi":"10.1109/ISQED.2006.84","DOIUrl":"https://doi.org/10.1109/ISQED.2006.84","url":null,"abstract":"This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. The key idea is thus to realize and deploy different types of six-transistor SRAM cells corresponding to different threshold voltage assignments for individual transistors in the cell. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs no area or delay overhead. In addition, it results only in a slight change in the SRAM design flow. Finally, it improves the static noise margin under process variations. Experimental results show that this technique can reduce the leakage-power dissipation of a 64Kb SRAM by more than 35%","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128653112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents two new single stuck-at fault collapsing methods to reduce the number of tests required for fault diagnosis. The impact of the proposed collapsing methods on diagnosis is evaluated in terms of time and space requirements for the diagnosis process. Experimental comparisons on the ISCAS'85 benchmarks demonstrate the impact of the proposed generalization over the traditional fault collapsing method
{"title":"Evaluation of collapsing methods for fault diagnosis","authors":"R. Adapa, S. Tragoudas, M. Michael","doi":"10.1109/ISQED.2006.62","DOIUrl":"https://doi.org/10.1109/ISQED.2006.62","url":null,"abstract":"This paper presents two new single stuck-at fault collapsing methods to reduce the number of tests required for fault diagnosis. The impact of the proposed collapsing methods on diagnosis is evaluated in terms of time and space requirements for the diagnosis process. Experimental comparisons on the ISCAS'85 benchmarks demonstrate the impact of the proposed generalization over the traditional fault collapsing method","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115758492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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