A direct boundary element method (BEM) was recently proposed for inductance extraction. Though faster than other volume integral methods, it still suffers from as many as 7N unknowns where N is the number of panels. A mixed BEM for inductance extraction is proposed in this paper, which combines indirect boundary integral equations (BIEs) of double layer potentials within conductors and direct BIEs within dielectric (between conductors). With this mixed BEM, the number of unknowns is remarkably cut down from 7N to 4N, and correspondingly, the CPU time spent on solving the linear system decreases greatly. Two interconnect structures are simulated to demonstrate the validity of this method
{"title":"A mixed boundary element method for extracting frequency-dependent inductances of 3D interconnects","authors":"Changhao Yan, Wenjian Yu, Zeyi Wang","doi":"10.1109/ISQED.2006.14","DOIUrl":"https://doi.org/10.1109/ISQED.2006.14","url":null,"abstract":"A direct boundary element method (BEM) was recently proposed for inductance extraction. Though faster than other volume integral methods, it still suffers from as many as 7N unknowns where N is the number of panels. A mixed BEM for inductance extraction is proposed in this paper, which combines indirect boundary integral equations (BIEs) of double layer potentials within conductors and direct BIEs within dielectric (between conductors). With this mixed BEM, the number of unknowns is remarkably cut down from 7N to 4N, and correspondingly, the CPU time spent on solving the linear system decreases greatly. Two interconnect structures are simulated to demonstrate the validity of this method","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121605167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cable discharge event (CDE) has been the main cause which damages the Ethernet interface in field applications. The transmission line pulsing (TLP) system has been the most popular method to observe electric characteristics of the device under human-body-model (HEM) electrostatic discharge (ESD) stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate CDE reliability of the Ethernet integrated circuits, and the results are compared with the conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-mum CMOS technology is worse than its HBMESD robustness
电缆放电事件(CDE)是现场应用中造成以太网接口损坏的主要原因。传输线脉冲(TLP)系统已成为观察人体模型(HEM)静电放电(ESD)应力下器件电特性的最常用方法。本文提出了长脉冲传输线脉冲(LP-TLP)系统来模拟以太网集成电路的CDE可靠性，并与传统的100-ns TLP系统进行了比较。实验结果表明，采用0.25 μ m CMOS技术的NMOS器件的CDE鲁棒性比HBMESD鲁棒性差
{"title":"Method to evaluate cable discharge event (CDE) reliability of integrated circuits in CMOS technology","authors":"Tai-Xiang Lai, M. Ker","doi":"10.1109/ISQED.2006.85","DOIUrl":"https://doi.org/10.1109/ISQED.2006.85","url":null,"abstract":"Cable discharge event (CDE) has been the main cause which damages the Ethernet interface in field applications. The transmission line pulsing (TLP) system has been the most popular method to observe electric characteristics of the device under human-body-model (HEM) electrostatic discharge (ESD) stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate CDE reliability of the Ethernet integrated circuits, and the results are compared with the conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-mum CMOS technology is worse than its HBMESD robustness","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114597817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a power gating technique with multiple sleep modes where each mode represents a trade-off between wake-up overhead and leakage savings. We show that high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. Our simulations and data traces show that multiple sleep mode capability provides an extra 17% reduction in overall leakage as compared to single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit
{"title":"Power gating with multiple sleep modes","authors":"K. Agarwal, K. Nowka, H. Singh, D. Sylvester","doi":"10.1109/ISQED.2006.102","DOIUrl":"https://doi.org/10.1109/ISQED.2006.102","url":null,"abstract":"This paper describes a power gating technique with multiple sleep modes where each mode represents a trade-off between wake-up overhead and leakage savings. We show that high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. Our simulations and data traces show that multiple sleep mode capability provides an extra 17% reduction in overall leakage as compared to single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"56 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120849830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Contrary to ASIC design where resources can be tuned with respect to the need of the designer, systems on programmable chip SoPC (FPGA) have to make best use of 'off the shelf devices', where main resources are fixed. In this regard, embedded memories are of tremendous value because of their low latency. These embedded memories are not only used for data and program storage but also for all sorts of memory usage e.g. FIFO used by IP interfaces for bus and network on chip connection. The problem addressed by this paper is the optimal sizing of queues in the framework of SoPC. Current SoC design tools are of little help to define the most adequate size for these FIFOs and the large design space coupled with excessive simulation times make it even more difficult. We propose in this paper an automatic tuning technique of queue sizes in IP interfaces for system on programmable chip with hardware in the loop execution. An application of our technique on Virtex-II SoPC is described
{"title":"System-level design methodology with direct execution for multiprocessors on SoPC","authors":"R. B. Mouhoub, O. Hammami","doi":"10.1109/ISQED.2006.128","DOIUrl":"https://doi.org/10.1109/ISQED.2006.128","url":null,"abstract":"Contrary to ASIC design where resources can be tuned with respect to the need of the designer, systems on programmable chip SoPC (FPGA) have to make best use of 'off the shelf devices', where main resources are fixed. In this regard, embedded memories are of tremendous value because of their low latency. These embedded memories are not only used for data and program storage but also for all sorts of memory usage e.g. FIFO used by IP interfaces for bus and network on chip connection. The problem addressed by this paper is the optimal sizing of queues in the framework of SoPC. Current SoC design tools are of little help to define the most adequate size for these FIFOs and the large design space coupled with excessive simulation times make it even more difficult. We propose in this paper an automatic tuning technique of queue sizes in IP interfaces for system on programmable chip with hardware in the loop execution. An application of our technique on Virtex-II SoPC is described","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121955663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. D. Guglielmo, F. Fummi, C. Marconcini, G. Pravadelli
The EFSM paradigm can be efficiently adopted to model complex designs without incurring in the state explosion problem typical of the traditional FSM paradigm. However, traversing an EFSM can be more difficult than an FSM because the guards of transitions involve both primary inputs and internal registers. Hard-to-traverse transitions represent a problem when a simulation-based approach is applied to perform functional validation. In fact, they do not allow a complete exploration of the state space. In this paper, EFSM hard-to-traverse transitions are classified, and a set of transformations is proposed to generate an EFSM model which is easy to be traversed. This allows pseudo-deterministic ATPGs to more uniformly analyze the state space of the resulting EFSM
{"title":"EFSM manipulation to increase high-level ATPG effectiveness","authors":"G. D. Guglielmo, F. Fummi, C. Marconcini, G. Pravadelli","doi":"10.1109/ISQED.2006.58","DOIUrl":"https://doi.org/10.1109/ISQED.2006.58","url":null,"abstract":"The EFSM paradigm can be efficiently adopted to model complex designs without incurring in the state explosion problem typical of the traditional FSM paradigm. However, traversing an EFSM can be more difficult than an FSM because the guards of transitions involve both primary inputs and internal registers. Hard-to-traverse transitions represent a problem when a simulation-based approach is applied to perform functional validation. In fact, they do not allow a complete exploration of the state space. In this paper, EFSM hard-to-traverse transitions are classified, and a set of transformations is proposed to generate an EFSM model which is easy to be traversed. This allows pseudo-deterministic ATPGs to more uniformly analyze the state space of the resulting EFSM","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114949219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a framework for calculating the data capacity of long on chip interconnects. This framework is based on the Shannon's capacity theorem. The extension of this theorem into binary symmetric channels (BSC) is studied and applied to the VLSI interconnects. This paper presents a simulation study that shows the variation of capacity with a variety physical and operating conditions of long wires. The results show that the operating frequency, that was arrived at using a worst case delay analysis, can be vastly increased through use of error correction coding. This capacity can also be used as a benchmark for evaluation of coding schemes on interconnects
{"title":"Information theoretic capacity of long on-chip interconnects in the presence of crosstalk","authors":"R. Singhal, G. Choi, R. Mahapatra","doi":"10.1109/ISQED.2006.76","DOIUrl":"https://doi.org/10.1109/ISQED.2006.76","url":null,"abstract":"This paper presents a framework for calculating the data capacity of long on chip interconnects. This framework is based on the Shannon's capacity theorem. The extension of this theorem into binary symmetric channels (BSC) is studied and applied to the VLSI interconnects. This paper presents a simulation study that shows the variation of capacity with a variety physical and operating conditions of long wires. The results show that the operating frequency, that was arrived at using a worst case delay analysis, can be vastly increased through use of error correction coding. This capacity can also be used as a benchmark for evaluation of coding schemes on interconnects","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123150555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Salman, E. Friedman, Ali Dasdan, F. Taraporevala, Kayhan Küçükçakar
A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static timing analysis tool is described. The proposed methodology prevents optimism and reduces unnecessary pessimism, both of which exist due to independent characterization. Furthermore, the tradeoff between interdependent setup and hold times is exploited to significantly reduce slack violations. These benefits are validated using industrial circuits and tools
{"title":"Pessimism reduction in static timing analysis using interdependent setup and hold times","authors":"E. Salman, E. Friedman, Ali Dasdan, F. Taraporevala, Kayhan Küçükçakar","doi":"10.1109/ISQED.2006.100","DOIUrl":"https://doi.org/10.1109/ISQED.2006.100","url":null,"abstract":"A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static timing analysis tool is described. The proposed methodology prevents optimism and reduces unnecessary pessimism, both of which exist due to independent characterization. Furthermore, the tradeoff between interdependent setup and hold times is exploited to significantly reduce slack violations. These benefits are validated using industrial circuits and tools","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129784352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jin He, Xing Zhang, Ganggang Zhang, M. Chan, Yangyuan Wang
A complete carrier-based non-charge-sheet analytic theory for the nano-scale undoped surrounding-gate MOSFETs is presented in this paper based on the basic device physics. The formulation is based on the Poisson's equation to solve directly for the mobile carrier-the electron concentration. Therefore, the distribution of the potential, the field and the charge density in the channel away from the surface is also expressed in terms of the carrier concentration, giving a carrier-based non-charge-sheet model for nano-scale undoped surrounding-gate MOSFETs including the short-channel effects. The formulated theory has an analytic form that does not need to solve the transcendent equation as in the conventional surface potential model or classical Pao-Sah formulation. As a result, the theory can analytically predict the analytical IV and CV characteristics of the undoped surrounding-gate MOSFETs. The validity of the theory results has also been demonstrated by extensive comparison with 3D numerical simulation
{"title":"A complete carrier-based non-charge-sheet analytic theory for nano-scale undoped surrounding-gate MOSFETs","authors":"Jin He, Xing Zhang, Ganggang Zhang, M. Chan, Yangyuan Wang","doi":"10.1109/ISQED.2006.8","DOIUrl":"https://doi.org/10.1109/ISQED.2006.8","url":null,"abstract":"A complete carrier-based non-charge-sheet analytic theory for the nano-scale undoped surrounding-gate MOSFETs is presented in this paper based on the basic device physics. The formulation is based on the Poisson's equation to solve directly for the mobile carrier-the electron concentration. Therefore, the distribution of the potential, the field and the charge density in the channel away from the surface is also expressed in terms of the carrier concentration, giving a carrier-based non-charge-sheet model for nano-scale undoped surrounding-gate MOSFETs including the short-channel effects. The formulated theory has an analytic form that does not need to solve the transcendent equation as in the conventional surface potential model or classical Pao-Sah formulation. As a result, the theory can analytically predict the analytical IV and CV characteristics of the undoped surrounding-gate MOSFETs. The validity of the theory results has also been demonstrated by extensive comparison with 3D numerical simulation","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128549668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of sub-100nm VLSI technologies, variation effects greatly increase the unwanted skew in clock distribution networks (CDNs), thereby reducing the performance of the chip. Recent works on link based non-tree CDN propose cross-link insertion in a given clock tree to reduce skew variation. However, the current methods suffer from the drawback that they are empirical in nature, requiring the user to experiment with different parameter values. Also, the methods of ignore the interaction between the different links while selecting the links for insertion. The method of (W.D. Lam et al., 2005) attempts to overcome this drawback using a statistical link insertion methodology. However, (W.D. Lam et al., 2005) is very slow even for relatively small circuits. In this paper, we propose a fast link insertion methodology which does not require selecting empirical parameters for link insertion. Our method also incrementally considers the effect of previously inserted links before choosing the next link. SPICE based Monte Carlo simulations show that our approach obtains comparable skew reduction to that of the existing approaches while drastically reducing the time taken to obtain a good link-based non-tree CDN
随着sub-100nm VLSI技术的出现，变化效应大大增加了时钟分配网络(cdn)中不必要的倾斜，从而降低了芯片的性能。最近基于链路的非树CDN研究提出在给定时钟树中插入交叉链路以减少偏差。然而，目前的方法有一个缺点，即它们本质上是经验性的，需要用户用不同的参数值进行实验。此外，在选择要插入的链接时，方法忽略了不同链接之间的交互。(W.D. Lam et al.， 2005)的方法试图使用统计链接插入方法来克服这一缺点。然而，(W.D. Lam et al.， 2005)即使对于相对较小的电路也是非常慢的。在本文中，我们提出了一种不需要选择经验参数的快速链路插入方法。我们的方法还在选择下一个链接之前，增量地考虑先前插入的链接的影响。基于SPICE的蒙特卡罗模拟表明，我们的方法获得了与现有方法相当的倾斜减少，同时大大减少了获得良好的基于链接的非树CDN所需的时间
{"title":"Fast incremental link insertion in clock networks for skew variability reduction","authors":"A. Rajaram, D. Pan","doi":"10.1109/ISQED.2006.66","DOIUrl":"https://doi.org/10.1109/ISQED.2006.66","url":null,"abstract":"With the advent of sub-100nm VLSI technologies, variation effects greatly increase the unwanted skew in clock distribution networks (CDNs), thereby reducing the performance of the chip. Recent works on link based non-tree CDN propose cross-link insertion in a given clock tree to reduce skew variation. However, the current methods suffer from the drawback that they are empirical in nature, requiring the user to experiment with different parameter values. Also, the methods of ignore the interaction between the different links while selecting the links for insertion. The method of (W.D. Lam et al., 2005) attempts to overcome this drawback using a statistical link insertion methodology. However, (W.D. Lam et al., 2005) is very slow even for relatively small circuits. In this paper, we propose a fast link insertion methodology which does not require selecting empirical parameters for link insertion. Our method also incrementally considers the effect of previously inserted links before choosing the next link. SPICE based Monte Carlo simulations show that our approach obtains comparable skew reduction to that of the existing approaches while drastically reducing the time taken to obtain a good link-based non-tree CDN","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121216857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper quantifies the approximation error in Clark's approach presented in C. E. Clark (1961) to computing the maximum (max) of Gaussian random variables; a fundamental operation in statistical timing. We show that a finite look up table can be used to store these errors. Based on the error computations, approaches to different orderings for pair-wise max operations on a set of Gaussians are proposed. Experiments show accuracy improvements in the computation of the max of multiple Gaussians by up to 50% in comparison to the traditional approach. To the best of our knowledge, this is the first work addressing the mentioned issues
本文量化了C. E. Clark(1961)中提出的计算高斯随机变量最大值(max)的Clark方法中的近似误差;统计计时中的一种基本操作。我们展示了一个有限查找表可以用来存储这些错误。在误差计算的基础上，提出了对一组高斯函数进行成对最大运算的不同排序方法。实验表明，与传统方法相比，该方法计算多个高斯函数最大值的精度提高了50%。据我们所知，这是针对上述问题的第一次工作
{"title":"Advances in computation of the maximum of a set of random variables","authors":"D. Sinha, H. Zhou, Narendra V. Shenoy","doi":"10.1109/ISQED.2006.22","DOIUrl":"https://doi.org/10.1109/ISQED.2006.22","url":null,"abstract":"This paper quantifies the approximation error in Clark's approach presented in C. E. Clark (1961) to computing the maximum (max) of Gaussian random variables; a fundamental operation in statistical timing. We show that a finite look up table can be used to store these errors. Based on the error computations, approaches to different orderings for pair-wise max operations on a set of Gaussians are proposed. Experiments show accuracy improvements in the computation of the max of multiple Gaussians by up to 50% in comparison to the traditional approach. To the best of our knowledge, this is the first work addressing the mentioned issues","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115829872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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