The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which needs to be modeled accurately in circuit design and verification. Meanwhile, the huge size of power grid requires its analysis to be fast and highly scalable. Algebraic multigrid (AMG) has been recognized as a promising approach for fast power grid analysis. We propose several techniques to improve AMG-based power grid analysis: (1) dynamic reduction threshold; (2) weighted interpolation; and (3) a new error smoothing scheme. Experimental results on power grid with up to 1.6 million nodes show that these techniques can improve accuracy by over 10 times compared to a reported industrial method while retaining the same fast speed
{"title":"An improved AMG-based method for fast power grid analysis","authors":"Cheng Zhuo, Jiang Hu, Kangsheng Chen","doi":"10.1109/ISQED.2006.23","DOIUrl":"https://doi.org/10.1109/ISQED.2006.23","url":null,"abstract":"The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which needs to be modeled accurately in circuit design and verification. Meanwhile, the huge size of power grid requires its analysis to be fast and highly scalable. Algebraic multigrid (AMG) has been recognized as a promising approach for fast power grid analysis. We propose several techniques to improve AMG-based power grid analysis: (1) dynamic reduction threshold; (2) weighted interpolation; and (3) a new error smoothing scheme. Experimental results on power grid with up to 1.6 million nodes show that these techniques can improve accuracy by over 10 times compared to a reported industrial method while retaining the same fast speed","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123795987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yi-Le Huang, Chun-Yao Wang, R. Yeh, Shih-Chieh Chang, Yung-Chih Chen
With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of the main problems in SoC verification is to verify whether the interface of a block works properly in its intended system. Transaction-based verification methodologies have been proposed to deal with this problem, and they allow users creating tests and writing test benches more easily. Furthermore, verifying interface designs in transaction level is very efficient. Previous work creates extractor manually for one on-chip bus (OCB), and the extra efforts are needed for other OCBs. In this paper, we present a language-based methodology to specify the bus behaviors in transaction level. Then the actual signals on the buses can be extracted to a higher level of abstraction. The bus behaviors displayed in transaction level significantly reduce the verification efforts for verification engineers. Furthermore, the corresponding transaction extractors are automatically generated. We demonstrate the success of our approach on AMBA AHB and Sonics' OCP buses
{"title":"Language-based high level transaction extraction on on-chip buses","authors":"Yi-Le Huang, Chun-Yao Wang, R. Yeh, Shih-Chieh Chang, Yung-Chih Chen","doi":"10.1109/ISQED.2006.79","DOIUrl":"https://doi.org/10.1109/ISQED.2006.79","url":null,"abstract":"With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of the main problems in SoC verification is to verify whether the interface of a block works properly in its intended system. Transaction-based verification methodologies have been proposed to deal with this problem, and they allow users creating tests and writing test benches more easily. Furthermore, verifying interface designs in transaction level is very efficient. Previous work creates extractor manually for one on-chip bus (OCB), and the extra efforts are needed for other OCBs. In this paper, we present a language-based methodology to specify the bus behaviors in transaction level. Then the actual signals on the buses can be extracted to a higher level of abstraction. The bus behaviors displayed in transaction level significantly reduce the verification efforts for verification engineers. Furthermore, the corresponding transaction extractors are automatically generated. We demonstrate the success of our approach on AMBA AHB and Sonics' OCP buses","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126199825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new signal integrity verification method of integrated circuit interconnects with asynchronous circuit switching is presented. A ramp input is modeled with delayed step inputs. Then signal transient variations due to asynchronous input signal switching are accurately as well as efficiently determined by using traveling-wave-based waveform approximation (TWA) technique. It is shown that using 90nm technology, the signal timing and crosstalk of multi-coupled lines with asynchronous switching inputs have an excellent agreement with SPICE simulation but its computation time is several thousand times faster than that of SPICE simulation using generic segment-based RLC circuit model
{"title":"Efficient signal integrity verification method of multi-coupled RLC interconnect lines with asynchronous circuit switching","authors":"Taeyong Je, Y. Eo","doi":"10.1109/ISQED.2006.57","DOIUrl":"https://doi.org/10.1109/ISQED.2006.57","url":null,"abstract":"A new signal integrity verification method of integrated circuit interconnects with asynchronous circuit switching is presented. A ramp input is modeled with delayed step inputs. Then signal transient variations due to asynchronous input signal switching are accurately as well as efficiently determined by using traveling-wave-based waveform approximation (TWA) technique. It is shown that using 90nm technology, the signal timing and crosstalk of multi-coupled lines with asynchronous switching inputs have an excellent agreement with SPICE simulation but its computation time is several thousand times faster than that of SPICE simulation using generic segment-based RLC circuit model","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"80 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125920230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jitter decomposition is important for accurately deriving the bit-error-rate in a system and for aiding in identifying the root causes of jitter. Limits of conventional solutions to this problem are discussed and a new approach to overcome the limitations is proposed. Our method uses time lag correlation functions to decompose different jitter components. The approach is validated by hardware measurements by applying the techniques to a phase locked loop into which jitter is injected
{"title":"Jitter decomposition by time lag correlation","authors":"Qingqi Dou, J. Abraham","doi":"10.1109/ISQED.2006.78","DOIUrl":"https://doi.org/10.1109/ISQED.2006.78","url":null,"abstract":"Jitter decomposition is important for accurately deriving the bit-error-rate in a system and for aiding in identifying the root causes of jitter. Limits of conventional solutions to this problem are discussed and a new approach to overcome the limitations is proposed. Our method uses time lag correlation functions to decompose different jitter components. The approach is validated by hardware measurements by applying the techniques to a phase locked loop into which jitter is injected","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131968180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Network-on-chip (NoC) has been proposed as a solution for the interconnection architecture design problem of system-on-chip (SoC) design in nanoscale technologies. NoC architecture for application specific SoC can be optimized by constructing custom topologies that are more suitable for the given application. In nanoscale technologies, the link energy consumption constitute a considerable part of the total communication energy. Therefore, the total energy consumption of the NoC is strongly influenced by system-level floorplan. In this paper, we present a novel integer linear programming (ILP) based technique for joint optimization of NoC with system-level floorplan. We also present a clustering based heuristic technique to reduce the runtime of the ILP formulation. Experimental results with realistic benchmarks applications demonstrate superiority of custom NoC topologies generated by our techniques over mesh based networks, and high quality of the clustering based technique when compared with the ILP formulation
{"title":"A methodology for layout aware design and optimization of custom network-on-chip architectures","authors":"K. Srinivasan, Karam S. Chatha","doi":"10.1109/ISQED.2006.13","DOIUrl":"https://doi.org/10.1109/ISQED.2006.13","url":null,"abstract":"Network-on-chip (NoC) has been proposed as a solution for the interconnection architecture design problem of system-on-chip (SoC) design in nanoscale technologies. NoC architecture for application specific SoC can be optimized by constructing custom topologies that are more suitable for the given application. In nanoscale technologies, the link energy consumption constitute a considerable part of the total communication energy. Therefore, the total energy consumption of the NoC is strongly influenced by system-level floorplan. In this paper, we present a novel integer linear programming (ILP) based technique for joint optimization of NoC with system-level floorplan. We also present a clustering based heuristic technique to reduce the runtime of the ILP formulation. Experimental results with realistic benchmarks applications demonstrate superiority of custom NoC topologies generated by our techniques over mesh based networks, and high quality of the clustering based technique when compared with the ILP formulation","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131971989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, O. Callen, S. Fabre, R. Ross, P. Simon, Robin Wilson
In order to maximize the yield of random logic in today's advanced deep sub-micron CMOS technologies we have developed a complete yield enhancement methodology for CMOS standard cells. This methodology based on a test vehicle approach covers design, industrial test, data collection and volume analysis, design debug, failure location and analysis. It has proven to be successful on three consecutive technology nodes down to 65nm. This paper explains the methodology and demonstrate the results and benefits of this work through illustrated examples
{"title":"Yield enhancement methodology for CMOS standard cells","authors":"Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, O. Callen, S. Fabre, R. Ross, P. Simon, Robin Wilson","doi":"10.1109/ISQED.2006.147","DOIUrl":"https://doi.org/10.1109/ISQED.2006.147","url":null,"abstract":"In order to maximize the yield of random logic in today's advanced deep sub-micron CMOS technologies we have developed a complete yield enhancement methodology for CMOS standard cells. This methodology based on a test vehicle approach covers design, industrial test, data collection and volume analysis, design debug, failure location and analysis. It has proven to be successful on three consecutive technology nodes down to 65nm. This paper explains the methodology and demonstrate the results and benefits of this work through illustrated examples","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133701889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Tirumala, Y. Mahotin, Xiao Lin, V. Moroz, Lee Smith, S. Krishnamurthy, L. Bomholt, D. Pramanik
This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parameters from silicon calibrated TCAD simulations. The model is validated by comparing device characteristics from the extracted SPICE parameters with those from TCAD simulations. The analysis demonstrates an excellent goodness of fit over the full range of process parameter variations. The process-dependant SPICE models allow direct access to process parameter variations in circuit design. The extracted models are employed in rudimentary digital circuits to investigate the delay variation in response to process deviations. The proposed approach significantly improves design-for-manufacturing (DFM) by allowing for accurate design sensitivity analysis and parametric yield assessment, as a function of statistically independent and measurable process variations
{"title":"Bringing manufacturing into design via process-dependent SPICE models","authors":"S. Tirumala, Y. Mahotin, Xiao Lin, V. Moroz, Lee Smith, S. Krishnamurthy, L. Bomholt, D. Pramanik","doi":"10.1109/ISQED.2006.31","DOIUrl":"https://doi.org/10.1109/ISQED.2006.31","url":null,"abstract":"This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parameters from silicon calibrated TCAD simulations. The model is validated by comparing device characteristics from the extracted SPICE parameters with those from TCAD simulations. The analysis demonstrates an excellent goodness of fit over the full range of process parameter variations. The process-dependant SPICE models allow direct access to process parameter variations in circuit design. The extracted models are employed in rudimentary digital circuits to investigate the delay variation in response to process deviations. The proposed approach significantly improves design-for-manufacturing (DFM) by allowing for accurate design sensitivity analysis and parametric yield assessment, as a function of statistically independent and measurable process variations","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131474481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we analyze the effect of manufacturing process variations on the SRAM stability in the read operation. We analyze the SRAM's read operation and the DC voltage-transfer characteristics (VTCs). Based on the VTCs, we define the read margin to characterize the SRAM cell's read stability. We calculate the read margin based on the transistor's current model using the BSIM3v3 model. Experimental results show that the read margin accurately captures the SRAM's read stability as a function of the transistors threshold voltage and the power supply voltage variations
{"title":"Analysis of process variation's effect on SRAM's read stability","authors":"Chung-Kuan Tsai, M. Marek-Sadowska","doi":"10.1109/ISQED.2006.26","DOIUrl":"https://doi.org/10.1109/ISQED.2006.26","url":null,"abstract":"In this paper we analyze the effect of manufacturing process variations on the SRAM stability in the read operation. We analyze the SRAM's read operation and the DC voltage-transfer characteristics (VTCs). Based on the VTCs, we define the read margin to characterize the SRAM cell's read stability. We calculate the read margin based on the transistor's current model using the BSIM3v3 model. Experimental results show that the read margin accurately captures the SRAM's read stability as a function of the transistors threshold voltage and the power supply voltage variations","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129323007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a core network interface (CNI) architecture to interface IP cores with on-chip networks. Besides the basic functionality of packetizing communication requests and responses, we expect the CNI to provide additional services critical to communication in complex systems-on-a-chip (SoC). A CNI for interfacing with OCP-compliant core interfaces was developed for architecture validation. With the support of a modified on-chip router, the CNI was setup to bound on-chip communication latency jitter. We observed that jitter due to inefficient virtual channel allocation in a particular configuration of an on-chip interconnection network lead to latency variations of up to 400%. Using a class-based virtual channel allocation scheme in a 2D torus network, we provide for predictable end-to-end latency. While the proposed scheme does not guarantee least possible end-to-end latency, it provides for constrained bounds
{"title":"Core network interface architecture and latency constrained on-chip communication","authors":"Praveen Bhojwani, R. Mahapatra","doi":"10.1109/ISQED.2006.41","DOIUrl":"https://doi.org/10.1109/ISQED.2006.41","url":null,"abstract":"This paper proposes a core network interface (CNI) architecture to interface IP cores with on-chip networks. Besides the basic functionality of packetizing communication requests and responses, we expect the CNI to provide additional services critical to communication in complex systems-on-a-chip (SoC). A CNI for interfacing with OCP-compliant core interfaces was developed for architecture validation. With the support of a modified on-chip router, the CNI was setup to bound on-chip communication latency jitter. We observed that jitter due to inefficient virtual channel allocation in a particular configuration of an on-chip interconnection network lead to latency variations of up to 400%. Using a class-based virtual channel allocation scheme in a 2D torus network, we provide for predictable end-to-end latency. While the proposed scheme does not guarantee least possible end-to-end latency, it provides for constrained bounds","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130421493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Concepción Sanz, M. Prieto, A. Papanikolaou, M. Corbalan, F. Catthoor
Process variability and the dynamism of new applications have a tremendous impact on both the performance and the energy consumption of memory organizations of embedded systems. In this paper, we explore the combination of code transformations at compilation time and architectural-level techniques to tackle both problems, introducing a new methodology to combine them in an integrated and coordinated way. Our approach manages to reduce significantly the energy overhead associated to both variability and application dynamism (up to 50% according to our simulations) without compromising the application timing constraints
{"title":"System-level process variability compensation on memory organizations of dynamic applications: a case study","authors":"Concepción Sanz, M. Prieto, A. Papanikolaou, M. Corbalan, F. Catthoor","doi":"10.1109/ISQED.2006.129","DOIUrl":"https://doi.org/10.1109/ISQED.2006.129","url":null,"abstract":"Process variability and the dynamism of new applications have a tremendous impact on both the performance and the energy consumption of memory organizations of embedded systems. In this paper, we explore the combination of code transformations at compilation time and architectural-level techniques to tackle both problems, introducing a new methodology to combine them in an integrated and coordinated way. Our approach manages to reduce significantly the energy overhead associated to both variability and application dynamism (up to 50% according to our simulations) without compromising the application timing constraints","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122205743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：