Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646586
A. Sinha, M. Mehendale
In this paper we present techniques for improving area efficiency of FIR filters implemented using the distributed arithmetic (DA) approach. These techniques exploit the flexibility in partitioning the filter coefficients for a two lookup-table (LUT) based DA implementation. The first technique is targeted at a ROM based implementation of LUTs and aims at minimizing number of columns/outputs of the ROMs. The second technique is targeted at a hardwired implementation of LUTs. We have developed an estimation technique for relative area comparisons of hardwired LUTs having the same number of inputs and outputs. We present a heuristic approach, based on this estimation technique, to optimally partition coefficients so as to achieve area-efficient hardwired implementation of LUTs. We present results to show these techniques can result in 10% to 15% area reduction for ROM based implementations and 20% to 25% area reduction for hardwired implementations.
{"title":"Improving area efficiency of FIR filters implemented using distributed arithmetic","authors":"A. Sinha, M. Mehendale","doi":"10.1109/ICVD.1998.646586","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646586","url":null,"abstract":"In this paper we present techniques for improving area efficiency of FIR filters implemented using the distributed arithmetic (DA) approach. These techniques exploit the flexibility in partitioning the filter coefficients for a two lookup-table (LUT) based DA implementation. The first technique is targeted at a ROM based implementation of LUTs and aims at minimizing number of columns/outputs of the ROMs. The second technique is targeted at a hardwired implementation of LUTs. We have developed an estimation technique for relative area comparisons of hardwired LUTs having the same number of inputs and outputs. We present a heuristic approach, based on this estimation technique, to optimally partition coefficients so as to achieve area-efficient hardwired implementation of LUTs. We present results to show these techniques can result in 10% to 15% area reduction for ROM based implementations and 20% to 25% area reduction for hardwired implementations.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114545456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646579
S. Majumder, S. Nandy, B. Bhattacharya
This paper identifies a new problem of geometric partitioning of VLSI floorplans, called mincost staircase partitioning. We propose a framework for channel definition in global routing. In a VLSI floorplan, the isothetic rectangular circuit modules are placed on a 2-D floor with nets attached to each block. The objective of global routing is to determine the channels through which the terminals attached to different modules belonging to the same net are connected. Here we have mapped the global routing problem into a series of hierarchical staircase channel routing. To minimize the routing congestion, in each level of hierarchy we find a monotone staircase channel minimizing the number of distinct nets, having terminals on both sides of the channel. We give an O(n/spl times/k) time algorithm for the two-terminal net problem, where n and k are the number of blocks and distinct nets respectively. For multi-terminal nets the time complexity is O((n+k)/spl times/T), T being the total number of terminals on the floor.
{"title":"Partitioning VLSI floorplans by staircase channels for global routing","authors":"S. Majumder, S. Nandy, B. Bhattacharya","doi":"10.1109/ICVD.1998.646579","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646579","url":null,"abstract":"This paper identifies a new problem of geometric partitioning of VLSI floorplans, called mincost staircase partitioning. We propose a framework for channel definition in global routing. In a VLSI floorplan, the isothetic rectangular circuit modules are placed on a 2-D floor with nets attached to each block. The objective of global routing is to determine the channels through which the terminals attached to different modules belonging to the same net are connected. Here we have mapped the global routing problem into a series of hierarchical staircase channel routing. To minimize the routing congestion, in each level of hierarchy we find a monotone staircase channel minimizing the number of distinct nets, having terminals on both sides of the channel. We give an O(n/spl times/k) time algorithm for the two-terminal net problem, where n and k are the number of blocks and distinct nets respectively. For multi-terminal nets the time complexity is O((n+k)/spl times/T), T being the total number of terminals on the floor.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121785143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646651
S. Majumder, M. Bushnell, V. Agrawal
There are two methods for applying path delay tests to a sequential circuit. We show that all path delay faults that can affect the rated-clock operation of the circuit are testable by the variable-clock method. Also, all path delay faults that are untestable by the variable-clock method are, in fact, untestable by the rated-clock method. However, some faults tested by the variable-clock method may be incapable of affecting the rated-clock operation. Our study is based on a finite-state machine model in which fault-free transitions are shown by green arcs. Faulty transitions are shown by red arcs. A test traverses successive arcs until a faulty output occurs. A variable-clock test can exercise more flexibility in selecting from green and red arcs. It can cover all functional paths, but may find only a proper subset of untestable paths. Our analysis assumes a delay fault, consisting of either a singly-testable path or multiply-testable paths, and hence corresponds to non-robust detection.
{"title":"Path delay testing: variable-clock versus rated-clock","authors":"S. Majumder, M. Bushnell, V. Agrawal","doi":"10.1109/ICVD.1998.646651","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646651","url":null,"abstract":"There are two methods for applying path delay tests to a sequential circuit. We show that all path delay faults that can affect the rated-clock operation of the circuit are testable by the variable-clock method. Also, all path delay faults that are untestable by the variable-clock method are, in fact, untestable by the rated-clock method. However, some faults tested by the variable-clock method may be incapable of affecting the rated-clock operation. Our study is based on a finite-state machine model in which fault-free transitions are shown by green arcs. Faulty transitions are shown by red arcs. A test traverses successive arcs until a faulty output occurs. A variable-clock test can exercise more flexibility in selecting from green and red arcs. It can cover all functional paths, but may find only a proper subset of untestable paths. Our analysis assumes a delay fault, consisting of either a singly-testable path or multiply-testable paths, and hence corresponds to non-robust detection.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130505388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646624
S. Srivastava, S. C. Bose, B. P. Mathur, A. Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, C. Shekhar, Sudhir Kumar, Amit K. Agarwal
Microprocessors constitute one of the most important classes of VLSI chips. Over the last 25 years their architectures and capabilities have evolved rapidly to pack enormous computing power in them. However, this has made the task of designing successive generations of microprocessors increasingly complex. Methodologies used to design microprocessors have also accordingly changed from generation to generation. The purpose of this paper is to summarize these evolutions in architecture and design methodologies of microprocessors and present a microprocessors design example using a methodology that makes efficient use of the HDL-based design approach to create portable microprocessor designs for use in system-level integrated products.
{"title":"Evolution of architectural concepts and design methods of microprocessors","authors":"S. Srivastava, S. C. Bose, B. P. Mathur, A. Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, C. Shekhar, Sudhir Kumar, Amit K. Agarwal","doi":"10.1109/ICVD.1998.646624","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646624","url":null,"abstract":"Microprocessors constitute one of the most important classes of VLSI chips. Over the last 25 years their architectures and capabilities have evolved rapidly to pack enormous computing power in them. However, this has made the task of designing successive generations of microprocessors increasingly complex. Methodologies used to design microprocessors have also accordingly changed from generation to generation. The purpose of this paper is to summarize these evolutions in architecture and design methodologies of microprocessors and present a microprocessors design example using a methodology that makes efficient use of the HDL-based design approach to create portable microprocessor designs for use in system-level integrated products.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129290558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646645
P. Prabhakaran, P. Banerjee
With small device features in sub-micron technologies, interconnection delays play a dominant part in cycle time. Therefore, it is important to consider the impact of physical design during high level synthesis. In this paper, an efficient floorplanning algorithm which takes into account the effect of interconnect delays on the overall cycle time of a given schedule is presented. A simultaneous scheduling, binding and floorplanning algorithm is also presented. In comparison to a traditional approach which separates high-level synthesis from physical design, our algorithm is able to make these stages interact very closely, resulting in solutions with lower latency and area. In addition, a detailed model is considered, taking into account multiplexer and register areas and delays.
{"title":"Simultaneous scheduling, binding and floorplanning in high-level synthesis","authors":"P. Prabhakaran, P. Banerjee","doi":"10.1109/ICVD.1998.646645","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646645","url":null,"abstract":"With small device features in sub-micron technologies, interconnection delays play a dominant part in cycle time. Therefore, it is important to consider the impact of physical design during high level synthesis. In this paper, an efficient floorplanning algorithm which takes into account the effect of interconnect delays on the overall cycle time of a given schedule is presented. A simultaneous scheduling, binding and floorplanning algorithm is also presented. In comparison to a traditional approach which separates high-level synthesis from physical design, our algorithm is able to make these stages interact very closely, resulting in solutions with lower latency and area. In addition, a detailed model is considered, taking into account multiplexer and register areas and delays.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125849589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646585
S. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee
In this paper we study a collision detection algorithm and partition it into hardware and software parts to enhance the performance of the system and achieve the real time goal (25 frames/sec). We explore the design space to identify various feasible implementations on software, hardware, firmware and mixed platforms. The platforms considered are the Intel's processors and Sun ULTRA1 for software, Motorola DSP56002 for firmware XILINX FPGAs for hardware. The mixed implementations include combinations of the above. A number of implementations discussed establish that factors such as time constraint, pin count and interface requirements strongly influence the design options.
{"title":"Real time collision detection and avoidance. A case study for design space exploration in HW-SW codesign","authors":"S. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee","doi":"10.1109/ICVD.1998.646585","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646585","url":null,"abstract":"In this paper we study a collision detection algorithm and partition it into hardware and software parts to enhance the performance of the system and achieve the real time goal (25 frames/sec). We explore the design space to identify various feasible implementations on software, hardware, firmware and mixed platforms. The platforms considered are the Intel's processors and Sun ULTRA1 for software, Motorola DSP56002 for firmware XILINX FPGAs for hardware. The mixed implementations include combinations of the above. A number of implementations discussed establish that factors such as time constraint, pin count and interface requirements strongly influence the design options.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128872776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646622
J. Rabaey
Energy considerations are at the heart of important paradigm shifts in next-generation designs, especially in systems-on-a-chip era. With multimedia and communication functions becoming more and more prominent, coming up with low-power solutions for these signal-processing applications is a clear must. Harvard-style architectures, as used in traditional signal processors, incur a significant overhead in power dissipation. It is therefore worthwhile to explore novel and different architectures and to quantify their impact on energy efficiency. Recently, reconfigurable programmable engines have received a lot of attention. In this paper, the opportunity for substantial power reduction by using hybrid reconfigurable processors is explored. With the aid of a number of small benchmarks, it is demonstrated that power reductions of orders of magnitude are attainable.
{"title":"Hybrid reconfigurable processors-the road to low-power consumption","authors":"J. Rabaey","doi":"10.1109/ICVD.1998.646622","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646622","url":null,"abstract":"Energy considerations are at the heart of important paradigm shifts in next-generation designs, especially in systems-on-a-chip era. With multimedia and communication functions becoming more and more prominent, coming up with low-power solutions for these signal-processing applications is a clear must. Harvard-style architectures, as used in traditional signal processors, incur a significant overhead in power dissipation. It is therefore worthwhile to explore novel and different architectures and to quantify their impact on energy efficiency. Recently, reconfigurable programmable engines have received a lot of attention. In this paper, the opportunity for substantial power reduction by using hybrid reconfigurable processors is explored. With the aid of a number of small benchmarks, it is demonstrated that power reductions of orders of magnitude are attainable.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123506860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646580
Sandip Das, S. Sur-Kolay, B. Bhattacharya
New techniques are presented for routing L-shaped channels, switchboxes and staircases in 2-layer Manhattan-diagonal (MD) model with tracks in horizontal, vertical and /spl plusmn/45/spl deg/ directions. First, a simple O(l.d) time algorithm is proposed which routes any L-shaped channel with length l, density d and no cyclic vertical constraints, in w (d/spl les/w/spl les/d+1) tracks. Next, an O(l.w) time greedy method for routing an L-shaped channel with cyclic vertical constraints, is described. Then, the switchbox routing problem in the MD model is solved elegantly. These techniques, easily extendible to the routing of staircase channels, yield efficient solutions to detailed routing in general floorplans. Experimental results show significantly low via-count and reduced wire length, thus establishing the superiority of MD-routing over classical strategies.
{"title":"Routing of L-shaped channels, switchboxes and staircases in Manhattan-diagonal model","authors":"Sandip Das, S. Sur-Kolay, B. Bhattacharya","doi":"10.1109/ICVD.1998.646580","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646580","url":null,"abstract":"New techniques are presented for routing L-shaped channels, switchboxes and staircases in 2-layer Manhattan-diagonal (MD) model with tracks in horizontal, vertical and /spl plusmn/45/spl deg/ directions. First, a simple O(l.d) time algorithm is proposed which routes any L-shaped channel with length l, density d and no cyclic vertical constraints, in w (d/spl les/w/spl les/d+1) tracks. Next, an O(l.w) time greedy method for routing an L-shaped channel with cyclic vertical constraints, is described. Then, the switchbox routing problem in the MD model is solved elegantly. These techniques, easily extendible to the routing of staircase channels, yield efficient solutions to detailed routing in general floorplans. Experimental results show significantly low via-count and reduced wire length, thus establishing the superiority of MD-routing over classical strategies.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116719365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646629
R. Jain, C. Chien, E. Cohen, Leader Ho
This paper describes CAD tools for communication system design. The tools allow for rapid algorithm development using a functional model library and scripting procedures that automate iterative optimization of algorithm parameters. Implementation tools are linked into the algorithm design environment to allow efficiency in generating hardware designs from algorithm descriptions. Examples from channel coding and from modern design illustrate how the data flow simulation in the CAD environment can be exploited for simulating and designing each of these components.
{"title":"Simulation and synthesis of VLSI communication systems","authors":"R. Jain, C. Chien, E. Cohen, Leader Ho","doi":"10.1109/ICVD.1998.646629","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646629","url":null,"abstract":"This paper describes CAD tools for communication system design. The tools allow for rapid algorithm development using a functional model library and scripting procedures that automate iterative optimization of algorithm parameters. Implementation tools are linked into the algorithm design environment to allow efficiency in generating hardware designs from algorithm descriptions. Examples from channel coding and from modern design illustrate how the data flow simulation in the CAD environment can be exploited for simulating and designing each of these components.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115445839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646614
G. Beers, L. John
A high-speed memory bus interface which enables greater throughput for data reads and writes is described in this paper. Current mode CMOS logic synthesis methods are used to implement multi-valued logic (MVL) functions to create a high bandwidth bus. First, a fundamental bi-directional data bus for multiple logic levels is presented. Then a bi-directional data bus with impedance matching terminators is presented. Finally a novel Adaptive Multi-Level Simultaneous bi-directional Transceiver (AMLST) bus structure for cache or main memory is proposed. The proposed bus can balance the memory channel bandwidth with the instruction execution rate of modern processors. Despite the problems encountered in implementing complete systems with MVL circuits, among which are circuit speed and design automation support, there is great potential in the future for this approach.
{"title":"A novel memory bus driver/receiver architecture for higher throughput","authors":"G. Beers, L. John","doi":"10.1109/ICVD.1998.646614","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646614","url":null,"abstract":"A high-speed memory bus interface which enables greater throughput for data reads and writes is described in this paper. Current mode CMOS logic synthesis methods are used to implement multi-valued logic (MVL) functions to create a high bandwidth bus. First, a fundamental bi-directional data bus for multiple logic levels is presented. Then a bi-directional data bus with impedance matching terminators is presented. Finally a novel Adaptive Multi-Level Simultaneous bi-directional Transceiver (AMLST) bus structure for cache or main memory is proposed. The proposed bus can balance the memory channel bandwidth with the instruction execution rate of modern processors. Despite the problems encountered in implementing complete systems with MVL circuits, among which are circuit speed and design automation support, there is great potential in the future for this approach.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116487599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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