Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646653
C. S. Raghu, S. Sundaram
Parallel processing offers a viable alternative to improve the enormous execution time of logic simulation of large VLSI designs. Various parallel logic simulation schemes have been proposed in recent years on achieving speedup using conservative and optimistic asynchronous algorithms. In this paper, we have proposed a new algorithm, capable of preempting inconsistent events and also reducing the number of messages sent among processors, resulting in faster simulation. Usage of prediction time, in both sequential and combinational circuits, gives capability of preempting inconsistent events and thereby supporting the rise/fall delay model for conservative event driven simulation. Implementation of the proposed algorithm has been carried out in a network of IBM RISC 6000/300 system workstations. Results of the proposed algorithm is compared with the null message based CM algorithm, and it was found that proposed algorithm more efficiently compared to the CM algorithm in case of sequential circuits and works as good as CM algorithm in combinational circuits.
{"title":"Distributed logic simulation algorithm using preemption of inconsistent events","authors":"C. S. Raghu, S. Sundaram","doi":"10.1109/ICVD.1998.646653","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646653","url":null,"abstract":"Parallel processing offers a viable alternative to improve the enormous execution time of logic simulation of large VLSI designs. Various parallel logic simulation schemes have been proposed in recent years on achieving speedup using conservative and optimistic asynchronous algorithms. In this paper, we have proposed a new algorithm, capable of preempting inconsistent events and also reducing the number of messages sent among processors, resulting in faster simulation. Usage of prediction time, in both sequential and combinational circuits, gives capability of preempting inconsistent events and thereby supporting the rise/fall delay model for conservative event driven simulation. Implementation of the proposed algorithm has been carried out in a network of IBM RISC 6000/300 system workstations. Results of the proposed algorithm is compared with the null message based CM algorithm, and it was found that proposed algorithm more efficiently compared to the CM algorithm in case of sequential circuits and works as good as CM algorithm in combinational circuits.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128517003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646642
P. Rao, C.S. Jayathirtha, C.S. Raghavendraprasad
Spectral approaches for partitioning netlists that use the eigenvectors of a matrix derived from a weighted graph model of the netlist (hypergraph) have been attracting considerable attention. There are several known ways in which a weighted graph could be derived from the netlist. However, the effectiveness of these alternate net models for netlist partitioning has remained unexplored. In this paper we first evaluate the relative performance of these approaches and establish that the quality of the partition is sensitive to the choice of the model. We also propose and investigate a number of new approaches for deriving a weighted graph model for a netlist. We show through test results on benchmark partitioning problems that one of the new models proposed here, performs consistently better than all the other models.
{"title":"New net models for spectral netlist partitioning","authors":"P. Rao, C.S. Jayathirtha, C.S. Raghavendraprasad","doi":"10.1109/ICVD.1998.646642","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646642","url":null,"abstract":"Spectral approaches for partitioning netlists that use the eigenvectors of a matrix derived from a weighted graph model of the netlist (hypergraph) have been attracting considerable attention. There are several known ways in which a weighted graph could be derived from the netlist. However, the effectiveness of these alternate net models for netlist partitioning has remained unexplored. In this paper we first evaluate the relative performance of these approaches and establish that the quality of the partition is sensitive to the choice of the model. We also propose and investigate a number of new approaches for deriving a weighted graph model for a netlist. We show through test results on benchmark partitioning problems that one of the new models proposed here, performs consistently better than all the other models.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129617812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646592
S. Venkatraman, S. Natarajan, K. Rao
A second order Gm-C filter designed in 1 /spl mu/m MOS technology is presented. The main characteristics of the filter are high linearity and low power operation at 5 V supply. This circuit uses MOS gate capacitance for the filter. Circuit performance shows a THD of 55 dB for 1 volt (pk-pk differential) at 1 MHz. The area of the filter is 320 sq. mils. and its power dissipation is 18 mW.
{"title":"A low power video frequency continuous time filter","authors":"S. Venkatraman, S. Natarajan, K. Rao","doi":"10.1109/ICVD.1998.646592","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646592","url":null,"abstract":"A second order Gm-C filter designed in 1 /spl mu/m MOS technology is presented. The main characteristics of the filter are high linearity and low power operation at 5 V supply. This circuit uses MOS gate capacitance for the filter. Circuit performance shows a THD of 55 dB for 1 volt (pk-pk differential) at 1 MHz. The area of the filter is 320 sq. mils. and its power dissipation is 18 mW.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123339872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646635
Amey Karkare, M. Singla, Ajai Jain
Multilevel logic optimization transformations for DFT (design for testability) used in existing logic systems, are characterized with respect to their testability preserving and testability enhancing properties. In this paper, we propose three new transformations which preserve or improve path delay testability with reduction in circuitry. The paper also includes a theorem showing the condition under which a testability preserving transformation (TPT) will be a testability enhancing transformations (TET).
{"title":"Testability preserving and enhancing transformations for robust delay fault testability","authors":"Amey Karkare, M. Singla, Ajai Jain","doi":"10.1109/ICVD.1998.646635","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646635","url":null,"abstract":"Multilevel logic optimization transformations for DFT (design for testability) used in existing logic systems, are characterized with respect to their testability preserving and testability enhancing properties. In this paper, we propose three new transformations which preserve or improve path delay testability with reduction in circuitry. The paper also includes a theorem showing the condition under which a testability preserving transformation (TPT) will be a testability enhancing transformations (TET).","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133701071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646593
C. Srinivasan
A new technique to improve the capture range of a Phase Locked Loop (PLL) in the context of partial response signalling is presented. A known preamble is transmitted at the beginning to aid phase and frequency locking. Previous timing recovery techniques have a false locking problem for large initial frequency errors. The new technique eliminates this problem by using information available in the sampled preamble sequence. The improvement obtained is demonstrated using computer simulations.
{"title":"A technique to improve capture range of a PLL in PRML read channel","authors":"C. Srinivasan","doi":"10.1109/ICVD.1998.646593","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646593","url":null,"abstract":"A new technique to improve the capture range of a Phase Locked Loop (PLL) in the context of partial response signalling is presented. A known preamble is transmitted at the beginning to aid phase and frequency locking. Previous timing recovery techniques have a false locking problem for large initial frequency errors. The new technique eliminates this problem by using information available in the sampled preamble sequence. The improvement obtained is demonstrated using computer simulations.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"516 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133035951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646587
M. Mehendale, S. B. Roy, S. Sherlekar, G. Venkatesh
Techniques based on common sub-computation extraction can be used to minimize number of additions in the multiplier-less implementations of Finite Impulse Response (FIR) filters. We present two types of coefficient transforms which used in conjunction with these techniques enable area-efficient realization of multiplier-less FIR filters. (i) Number theoretic transforms-that use redundant binary representations such as Canonical Sign Digit (CSD) (ii) Signal Flow Graph transformations that modify the coefficient values while retaining the output functionality. We demonstrate this with results of 6 different coefficient transforms for 14 low pass FIR filters with number of taps ranging from 16 to 128.
{"title":"Coefficient transformations for area-efficient implementation of multiplier-less FIR filters","authors":"M. Mehendale, S. B. Roy, S. Sherlekar, G. Venkatesh","doi":"10.1109/ICVD.1998.646587","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646587","url":null,"abstract":"Techniques based on common sub-computation extraction can be used to minimize number of additions in the multiplier-less implementations of Finite Impulse Response (FIR) filters. We present two types of coefficient transforms which used in conjunction with these techniques enable area-efficient realization of multiplier-less FIR filters. (i) Number theoretic transforms-that use redundant binary representations such as Canonical Sign Digit (CSD) (ii) Signal Flow Graph transformations that modify the coefficient values while retaining the output functionality. We demonstrate this with results of 6 different coefficient transforms for 14 low pass FIR filters with number of taps ranging from 16 to 128.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"292 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132035300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646605
P. Chavda, J. Jacob, V. Agrawal
When a Boolean function is transformed by exclusive-OR with a suitably selected transform function, the new function is often synthesized with significantly reduced hardware. The transform function is separately synthesized and the original function is recovered as an exclusive-OR of the two functions. We select the transform to reduce the number of cubes in the function to be synthesized. The function is represented as a Shannon expansion about selected variables. A transform function is constructed such that a selected set of cofactors is complemented to minimize the overall number of cubes. Examples of single-output functions show an average area reduction of 19%. For a multiple-output function, transformations can be customized for each output.
{"title":"Optimizing logic design using Boolean transforms","authors":"P. Chavda, J. Jacob, V. Agrawal","doi":"10.1109/ICVD.1998.646605","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646605","url":null,"abstract":"When a Boolean function is transformed by exclusive-OR with a suitably selected transform function, the new function is often synthesized with significantly reduced hardware. The transform function is separately synthesized and the original function is recovered as an exclusive-OR of the two functions. We select the transform to reduce the number of cubes in the function to be synthesized. The function is represented as a Shannon expansion about selected variables. A transform function is constructed such that a selected set of cofactors is complemented to minimize the overall number of cubes. Examples of single-output functions show an average area reduction of 19%. For a multiple-output function, transformations can be customized for each output.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131719440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646622
J. Rabaey
Energy considerations are at the heart of important paradigm shifts in next-generation designs, especially in systems-on-a-chip era. With multimedia and communication functions becoming more and more prominent, coming up with low-power solutions for these signal-processing applications is a clear must. Harvard-style architectures, as used in traditional signal processors, incur a significant overhead in power dissipation. It is therefore worthwhile to explore novel and different architectures and to quantify their impact on energy efficiency. Recently, reconfigurable programmable engines have received a lot of attention. In this paper, the opportunity for substantial power reduction by using hybrid reconfigurable processors is explored. With the aid of a number of small benchmarks, it is demonstrated that power reductions of orders of magnitude are attainable.
{"title":"Hybrid reconfigurable processors-the road to low-power consumption","authors":"J. Rabaey","doi":"10.1109/ICVD.1998.646622","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646622","url":null,"abstract":"Energy considerations are at the heart of important paradigm shifts in next-generation designs, especially in systems-on-a-chip era. With multimedia and communication functions becoming more and more prominent, coming up with low-power solutions for these signal-processing applications is a clear must. Harvard-style architectures, as used in traditional signal processors, incur a significant overhead in power dissipation. It is therefore worthwhile to explore novel and different architectures and to quantify their impact on energy efficiency. Recently, reconfigurable programmable engines have received a lot of attention. In this paper, the opportunity for substantial power reduction by using hybrid reconfigurable processors is explored. With the aid of a number of small benchmarks, it is demonstrated that power reductions of orders of magnitude are attainable.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123506860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646640
M. B. Sherigar, A. Mahadevan, K. S. Kumar, D. S. Sumam
The paper presents a pipelined parallel processor architecture design to implement the MD4 message digest algorithm which computes the message digest or the fingerprint of 128 bit fixed length, for any arbitrary length of input message. The processor implements the arithmetic, logic and circular shift operations by a pipelined parallel process. The architecture is designed to suit the design flexibility of the Xilinx Field Programmable Gate Arrays (FPGAs) The processor reads the message from an external RAM, 16-bit at a time and internal operations are performed with 32-bit data. The major advantage of the design is increased speed of computation and minimum hardware. The processor computes the digest with a speed approximately three times faster than the software version implemented in DSP processors.
{"title":"A pipelined parallel processor to implement MD4 message digest algorithm on Xilinx FPGA","authors":"M. B. Sherigar, A. Mahadevan, K. S. Kumar, D. S. Sumam","doi":"10.1109/ICVD.1998.646640","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646640","url":null,"abstract":"The paper presents a pipelined parallel processor architecture design to implement the MD4 message digest algorithm which computes the message digest or the fingerprint of 128 bit fixed length, for any arbitrary length of input message. The processor implements the arithmetic, logic and circular shift operations by a pipelined parallel process. The architecture is designed to suit the design flexibility of the Xilinx Field Programmable Gate Arrays (FPGAs) The processor reads the message from an external RAM, 16-bit at a time and internal operations are performed with 32-bit data. The major advantage of the design is increased speed of computation and minimum hardware. The processor computes the digest with a speed approximately three times faster than the software version implemented in DSP processors.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123705402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646586
A. Sinha, M. Mehendale
In this paper we present techniques for improving area efficiency of FIR filters implemented using the distributed arithmetic (DA) approach. These techniques exploit the flexibility in partitioning the filter coefficients for a two lookup-table (LUT) based DA implementation. The first technique is targeted at a ROM based implementation of LUTs and aims at minimizing number of columns/outputs of the ROMs. The second technique is targeted at a hardwired implementation of LUTs. We have developed an estimation technique for relative area comparisons of hardwired LUTs having the same number of inputs and outputs. We present a heuristic approach, based on this estimation technique, to optimally partition coefficients so as to achieve area-efficient hardwired implementation of LUTs. We present results to show these techniques can result in 10% to 15% area reduction for ROM based implementations and 20% to 25% area reduction for hardwired implementations.
{"title":"Improving area efficiency of FIR filters implemented using distributed arithmetic","authors":"A. Sinha, M. Mehendale","doi":"10.1109/ICVD.1998.646586","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646586","url":null,"abstract":"In this paper we present techniques for improving area efficiency of FIR filters implemented using the distributed arithmetic (DA) approach. These techniques exploit the flexibility in partitioning the filter coefficients for a two lookup-table (LUT) based DA implementation. The first technique is targeted at a ROM based implementation of LUTs and aims at minimizing number of columns/outputs of the ROMs. The second technique is targeted at a hardwired implementation of LUTs. We have developed an estimation technique for relative area comparisons of hardwired LUTs having the same number of inputs and outputs. We present a heuristic approach, based on this estimation technique, to optimally partition coefficients so as to achieve area-efficient hardwired implementation of LUTs. We present results to show these techniques can result in 10% to 15% area reduction for ROM based implementations and 20% to 25% area reduction for hardwired implementations.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114545456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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