Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816808
A. Liotta, G. Frattini, P. Giannelli, E. Bonizzoni, P. Malcovati
This paper presents an LLC resonant DC-DC converter suitable for low voltage applications. The circuit, designed and simulated in a standard 180-nm BCD process, employs a MOSFET-based active rectifier in order to minimize conduction losses, thus increasing the efficiency at heavy load. The circuit operates with an input voltage of 5 V (±10%), an output voltage of 12 V, and provides to the output a maximum power of 2 W. Transistor level simulation results show an efficiency of 84% at full output power.
{"title":"Design of an LLC Resonant DC-DC Converter with MOSFET-Based Active Rectifier","authors":"A. Liotta, G. Frattini, P. Giannelli, E. Bonizzoni, P. Malcovati","doi":"10.1109/prime55000.2022.9816808","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816808","url":null,"abstract":"This paper presents an LLC resonant DC-DC converter suitable for low voltage applications. The circuit, designed and simulated in a standard 180-nm BCD process, employs a MOSFET-based active rectifier in order to minimize conduction losses, thus increasing the efficiency at heavy load. The circuit operates with an input voltage of 5 V (±10%), an output voltage of 12 V, and provides to the output a maximum power of 2 W. Transistor level simulation results show an efficiency of 84% at full output power.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126210436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816810
Luca Zulberti, Matteo Monopoli, P. Nannipieri, L. Fanucci
Reconfigurable computing has become very popular in recent years. Among all available architectures, Coarse-Grained Reconfigurable Arrays are the most prominent ones. They permit to efficiently accelerate several classes of data-intensive algorithms without giving up architecture versatility, and their use in machine learning applications is becoming increasingly widespread. In particular, the typical workload of Convolutional Neural Networks fits very well on this kind of architecture. Unfortunately, their use in Graph Neural Networks is not well investigated. Graph Neural Network algorithms apply to use cases that are characterized by non-euclidean data, such as computer vision, natural language processing, traffic forecasting, chemistry, and recommendation systems. In this work, we analyse the most relevant Coarse-Grained Reconfigurable Array devices and Graph Neural Network models. Our contribution includes a comparison between the hardware architectures and their use for the inference of Graph Neural Network models. We highlight their limitations and discuss possible directions that the development of these architectures could take.
{"title":"Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators","authors":"Luca Zulberti, Matteo Monopoli, P. Nannipieri, L. Fanucci","doi":"10.1109/prime55000.2022.9816810","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816810","url":null,"abstract":"Reconfigurable computing has become very popular in recent years. Among all available architectures, Coarse-Grained Reconfigurable Arrays are the most prominent ones. They permit to efficiently accelerate several classes of data-intensive algorithms without giving up architecture versatility, and their use in machine learning applications is becoming increasingly widespread. In particular, the typical workload of Convolutional Neural Networks fits very well on this kind of architecture. Unfortunately, their use in Graph Neural Networks is not well investigated. Graph Neural Network algorithms apply to use cases that are characterized by non-euclidean data, such as computer vision, natural language processing, traffic forecasting, chemistry, and recommendation systems. In this work, we analyse the most relevant Coarse-Grained Reconfigurable Array devices and Graph Neural Network models. Our contribution includes a comparison between the hardware architectures and their use for the inference of Graph Neural Network models. We highlight their limitations and discuss possible directions that the development of these architectures could take.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129274960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816828
Matthiew Franks, N. Massari, L. Parmesan, G. Casse
In the presented paper we describe an innovative pixel topology designed for particle tracking. The proposed approach is based on a fully digital concept. When ionising particles traverse detector material, charges collected by the pixel are converted to a single bit to obtain a binary image. This digital approach allows a simplified pixel schematic to be used, reducing the pixel size to 2.5 μm × 2.5 μm and optimises the power consumption and the speed of the readout. An array of 256×256 pixels have been fabricated in a 65 nm standard CMOS technology as a proof of concept. Preliminary results on pixel performance are reported, demonstrating the potential of the approach.
{"title":"A novel fully digital particle detector with high spatial resolution","authors":"Matthiew Franks, N. Massari, L. Parmesan, G. Casse","doi":"10.1109/prime55000.2022.9816828","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816828","url":null,"abstract":"In the presented paper we describe an innovative pixel topology designed for particle tracking. The proposed approach is based on a fully digital concept. When ionising particles traverse detector material, charges collected by the pixel are converted to a single bit to obtain a binary image. This digital approach allows a simplified pixel schematic to be used, reducing the pixel size to 2.5 μm × 2.5 μm and optimises the power consumption and the speed of the readout. An array of 256×256 pixels have been fabricated in a 65 nm standard CMOS technology as a proof of concept. Preliminary results on pixel performance are reported, demonstrating the potential of the approach.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116390128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816816
A. Migali, F. Spagnolo, P. Corsonello
Drowsiness detection is a key feature in modern Advanced Driver Assistance Systems (ADAS). State-of-the-art approaches rely on machine learning techniques and neural networks to monitor unusual movements of the head and eyes activities. Unfortunately, due to their computationally intensive operations, integrating such algorithms in real-time and low-power operating scenarios, like auto-motive applications, is still quite challenging. This paper proposes an efficient hardware architecture for real-time drowsiness detection based on monitoring the driver’s eye blinking behaviour through the PERcentage of eye CLOSure (PERCLOS) metric. Experimental results obtained on the Xilinx Zynq XC7Z020 FPGA SoC show that the proposed system is up to 33.3 times faster and 2.6 times less area consuming than state-of-the-art competitors.
{"title":"Heterogeneous FPGA-based System for Real-Time Drowsiness Detection","authors":"A. Migali, F. Spagnolo, P. Corsonello","doi":"10.1109/prime55000.2022.9816816","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816816","url":null,"abstract":"Drowsiness detection is a key feature in modern Advanced Driver Assistance Systems (ADAS). State-of-the-art approaches rely on machine learning techniques and neural networks to monitor unusual movements of the head and eyes activities. Unfortunately, due to their computationally intensive operations, integrating such algorithms in real-time and low-power operating scenarios, like auto-motive applications, is still quite challenging. This paper proposes an efficient hardware architecture for real-time drowsiness detection based on monitoring the driver’s eye blinking behaviour through the PERcentage of eye CLOSure (PERCLOS) metric. Experimental results obtained on the Xilinx Zynq XC7Z020 FPGA SoC show that the proposed system is up to 33.3 times faster and 2.6 times less area consuming than state-of-the-art competitors.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133448643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816759
Angelo Lucio Bella, G. Giustolisi, M. L. Rosa, G. Sicurella
In this work, a design methodology of a step-down (buck) DC-DC converter is presented focusing on the output power stage. The target system is a synchronous buck converter for general purpose applications, which works in a wide range of input and output voltages. The analysis has been focused on the power conversion efficiency that represents one of the major features of this device. Its efficiency is strictly related to the power MOS losses, both conduction and switching ones. The design methodology has been organized into three steps: the first one is the characterization of the power MOS parasites (both resistive and capacitive) with particular attention to temperature and gate driving voltage; in the second step, the power losses are evaluated according to parasitic at different temperature and driving condition of the power MOS; in the last step, the theoretical calculation is verified with the simulation. In particular, the technology used in this work is a 0.16 $mu mathrm{m}$ Advanced BCD Technology and the simulation environment used is the Cadence Virtuoso suite.
{"title":"Design Methodology of the Output Power Stage of a Step-Down DC-DC Converter","authors":"Angelo Lucio Bella, G. Giustolisi, M. L. Rosa, G. Sicurella","doi":"10.1109/prime55000.2022.9816759","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816759","url":null,"abstract":"In this work, a design methodology of a step-down (buck) DC-DC converter is presented focusing on the output power stage. The target system is a synchronous buck converter for general purpose applications, which works in a wide range of input and output voltages. The analysis has been focused on the power conversion efficiency that represents one of the major features of this device. Its efficiency is strictly related to the power MOS losses, both conduction and switching ones. The design methodology has been organized into three steps: the first one is the characterization of the power MOS parasites (both resistive and capacitive) with particular attention to temperature and gate driving voltage; in the second step, the power losses are evaluated according to parasitic at different temperature and driving condition of the power MOS; in the last step, the theoretical calculation is verified with the simulation. In particular, the technology used in this work is a 0.16 $mu mathrm{m}$ Advanced BCD Technology and the simulation environment used is the Cadence Virtuoso suite.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124584708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816841
S. Spanò, L. Canese, G. Cardarilli
In this paper we assess the performance of the new MATLAB Deep Learning Processor. It is a hardware architecture meant for FPGA devices which is able to infer Convolutional Neural Networks. The system is deployed on a Xilinx ZCU102 SoC and we customize it with the aim to maximize its processing performance. We evaluate the hardware resources utilization, the maximum achievable clock frequency, and the power dissipation of the system. Our goal is to find the best performing networks on FPGA and, eventually, to compare the results with a GPU-based counterpart. We conduct an experimental campaign where the FPGA execution time of several CNNs is profiled and compared to the execution time on the NVIDIA Titan RTX GPU platform. This allows a comparative performance analysis when the same network is inferred on different systems. We consider all the available CNNs of the MATLAB suite which have been pretrained with the ImageNet dataset. Finally, to pinpoint the most cost-effective network, the FPGA prediction time is put in relation with the accuracy on the aforementioned dataset.
{"title":"Profiling of CNNs using the MATLAB FPGA-based Deep Learning Processor","authors":"S. Spanò, L. Canese, G. Cardarilli","doi":"10.1109/prime55000.2022.9816841","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816841","url":null,"abstract":"In this paper we assess the performance of the new MATLAB Deep Learning Processor. It is a hardware architecture meant for FPGA devices which is able to infer Convolutional Neural Networks. The system is deployed on a Xilinx ZCU102 SoC and we customize it with the aim to maximize its processing performance. We evaluate the hardware resources utilization, the maximum achievable clock frequency, and the power dissipation of the system. Our goal is to find the best performing networks on FPGA and, eventually, to compare the results with a GPU-based counterpart. We conduct an experimental campaign where the FPGA execution time of several CNNs is profiled and compared to the execution time on the NVIDIA Titan RTX GPU platform. This allows a comparative performance analysis when the same network is inferred on different systems. We consider all the available CNNs of the MATLAB suite which have been pretrained with the ImageNet dataset. Finally, to pinpoint the most cost-effective network, the FPGA prediction time is put in relation with the accuracy on the aforementioned dataset.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127772754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816756
Francesco Gagliardi, Andrea Ria, G. Manfredini, M. Piotto, P. Bruschi
This paper presents a simple and original CMOS, sub-threshold bandgap voltage reference capable of operating with extremely reduced supply voltage values. The circuit capability is demonstrated by means of accurate electrical simulations performed on a prototype designed with a standard 0.18 $mu$m CMOS process. A reference voltage of 190 mV has been obtained with a minimum supply voltage of only 223 mV and a line regulation close to 8 mV/V.
{"title":"A Triode-Compensated CMOS Bandgap Core for Sub-250 mV Supply Voltages","authors":"Francesco Gagliardi, Andrea Ria, G. Manfredini, M. Piotto, P. Bruschi","doi":"10.1109/prime55000.2022.9816756","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816756","url":null,"abstract":"This paper presents a simple and original CMOS, sub-threshold bandgap voltage reference capable of operating with extremely reduced supply voltage values. The circuit capability is demonstrated by means of accurate electrical simulations performed on a prototype designed with a standard 0.18 $mu$m CMOS process. A reference voltage of 190 mV has been obtained with a minimum supply voltage of only 223 mV and a line regulation close to 8 mV/V.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116032779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816752
M. Privitera, A. Ballo, A. D. Grasso
Battery-less implantable medical devices (IMDs) are encountering an always growing interest in recent years. The ability to monitor body-organs activities using electrical stimulators requires the establishment of a Data Down-Link, while a Data Up-Link is an ubiquitous feature to monitor health conditions by acquiring biological signals. Under this scenario, this work deals with the design and the simulations of a Fully-Digital Binary Phase-Shift Keying (BPSK) demodulator for the Downlink in Ultrasound (US)-powered IMDs. The system presents low area occupation, ultra-low power consumption down to 1.25 $mu mathrm{W}$. It is implemented in a 28-nm bulk CMOS technology provided by TSMC. Its data rate rises up 2 Mbit/s and a minimum energy-per-bit equals to 0.63 pJ/bit.
{"title":"A 0.63 pJ/bit Fully-Digital BPSK Demodulator for US-powered IMDs downlink in a 28-nm bulk CMOS technology","authors":"M. Privitera, A. Ballo, A. D. Grasso","doi":"10.1109/prime55000.2022.9816752","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816752","url":null,"abstract":"Battery-less implantable medical devices (IMDs) are encountering an always growing interest in recent years. The ability to monitor body-organs activities using electrical stimulators requires the establishment of a Data Down-Link, while a Data Up-Link is an ubiquitous feature to monitor health conditions by acquiring biological signals. Under this scenario, this work deals with the design and the simulations of a Fully-Digital Binary Phase-Shift Keying (BPSK) demodulator for the Downlink in Ultrasound (US)-powered IMDs. The system presents low area occupation, ultra-low power consumption down to 1.25 $mu mathrm{W}$. It is implemented in a 28-nm bulk CMOS technology provided by TSMC. Its data rate rises up 2 Mbit/s and a minimum energy-per-bit equals to 0.63 pJ/bit.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"356 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115727340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816776
A. M. Elgani, Matteo D'Addato, Luca Perilli, E. Franchi, R. Canegallo
This paper presents a design flow for an active low-pass (LP) Envelope Detector (ED) for Wake-Up Radio (WUR) receivers and provides insight on the well-known bitrate-sensitivity-current trade-off and on additional aspects which may be critical in Internet of Things (IoT) applications, such as maximum receivable input power and robustness against Continuous Wave (CW) interferers. The implemented LP ED, designed using the STMicroelectronics 90-nm BCD technology, receives 400-bit OOK-modulated packets with an 868-MHz carrier frequency and achieves −35.5-dBm sensitivity with a 2.7-nW power consumption. Finally, it receives input power levels up to 15 dBm and achieves 22-dB Signal-to-Interference Ratio (SIR) with a CW interferer with a 100-kHz frequency offset.
{"title":"Design and Characterization of an Active Low-Pass Envelope Detector for Wake-Up Radio Receivers","authors":"A. M. Elgani, Matteo D'Addato, Luca Perilli, E. Franchi, R. Canegallo","doi":"10.1109/prime55000.2022.9816776","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816776","url":null,"abstract":"This paper presents a design flow for an active low-pass (LP) Envelope Detector (ED) for Wake-Up Radio (WUR) receivers and provides insight on the well-known bitrate-sensitivity-current trade-off and on additional aspects which may be critical in Internet of Things (IoT) applications, such as maximum receivable input power and robustness against Continuous Wave (CW) interferers. The implemented LP ED, designed using the STMicroelectronics 90-nm BCD technology, receives 400-bit OOK-modulated packets with an 868-MHz carrier frequency and achieves −35.5-dBm sensitivity with a 2.7-nW power consumption. Finally, it receives input power levels up to 15 dBm and achieves 22-dB Signal-to-Interference Ratio (SIR) with a CW interferer with a 100-kHz frequency offset.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127117322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816787
I. Nunziata, Efstratios Zacharelos, Gerardo Saggese, A. Strollo, E. Napoli
Approximate computing is a fast-emerging paradigm promising higher circuit performances in error tolerant applications. Binary multipliers are a common target for approximate computing due to their complexity and the multitude of their applications. In this paper, we investigate approximate recursive multipliers based on novel 4x4 multiplier blocks. We present three approximate 4x4 multipliers, with different error-precision trade-off, obtained by carry truncation and error compensation. These basic blocks are exploited to design 8x8 approximate multipliers. The proposed circuits are implemented in a 14 nm FinFET technology and show improved performance compared to the state-of-the-art.
{"title":"Approximate Recursive Multipliers Using Carry Truncation and Error Compensation","authors":"I. Nunziata, Efstratios Zacharelos, Gerardo Saggese, A. Strollo, E. Napoli","doi":"10.1109/prime55000.2022.9816787","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816787","url":null,"abstract":"Approximate computing is a fast-emerging paradigm promising higher circuit performances in error tolerant applications. Binary multipliers are a common target for approximate computing due to their complexity and the multitude of their applications. In this paper, we investigate approximate recursive multipliers based on novel 4x4 multiplier blocks. We present three approximate 4x4 multipliers, with different error-precision trade-off, obtained by carry truncation and error compensation. These basic blocks are exploited to design 8x8 approximate multipliers. The proposed circuits are implemented in a 14 nm FinFET technology and show improved performance compared to the state-of-the-art.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123747093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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