Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816805
D.S. Gorni, G. Deptuch, S. Miryala
The large number of data generating sources (data channels) on a single chip requires appropriate techniques to manage a readout from these channels. One of the main methods is sharing a medium of transmission, which requires arbitration to avoid collisions or deadlocks. Existing solutions face several problems such as a dead time, unintended prioritization or metastability. That is why we decided to create a new readout architecture named EDWARD i.e., Event Driven with Access and Reset Decoder. The EDWARD architecture gets rid of the earlier mentioned problems and mitigates the other ones. However, due to the use of logic circuits outside a standard cell library, which are hard to characterize, we were challenged to perform an additional transient analysis to validate the architecture. Here we show a methodology and the results of the simulations. Based on the results obtained we can confirm the functional correctness of the system and plan the optimization of operating conditions in order to achieve better performance. Our goal is to use the EDWARD architecture in the future radiation detectors to be built at Brookhaven National Laboratory.
{"title":"Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array","authors":"D.S. Gorni, G. Deptuch, S. Miryala","doi":"10.1109/prime55000.2022.9816805","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816805","url":null,"abstract":"The large number of data generating sources (data channels) on a single chip requires appropriate techniques to manage a readout from these channels. One of the main methods is sharing a medium of transmission, which requires arbitration to avoid collisions or deadlocks. Existing solutions face several problems such as a dead time, unintended prioritization or metastability. That is why we decided to create a new readout architecture named EDWARD i.e., Event Driven with Access and Reset Decoder. The EDWARD architecture gets rid of the earlier mentioned problems and mitigates the other ones. However, due to the use of logic circuits outside a standard cell library, which are hard to characterize, we were challenged to perform an additional transient analysis to validate the architecture. Here we show a methodology and the results of the simulations. Based on the results obtained we can confirm the functional correctness of the system and plan the optimization of operating conditions in order to achieve better performance. Our goal is to use the EDWARD architecture in the future radiation detectors to be built at Brookhaven National Laboratory.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128360365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816833
Riccardo Della Sala, F. Centurelli, P. Monsurrò, G. Scotti
Multi-channel neural recording systems are more and more required for neuroscience research and to cope with neurological disorders. Such systems are based on brain-implantable integrated devices with stringent requirements on supply voltage, power consumption and area footprint. A very low power, low noise fully differential front-end amplifier for neural signals processing is presented in this paper. The proposed amplifier architecture exploits two fully differential OTAs with Arbel topology operating in sub-threshold, and allows AC coupling with a high offset electrode while guaranteeing a very low high-pass cut-off frequency without increasing the equivalent input noise. The neural recording front-end has been designed referring to a 0.13-μm CMOS process. The proposed amplifier operates with a supply voltage as low as 0. 3V with a mid-band gain of 40dB and a -3dB bandwidth from 0.1 Hz to 10 kHz. Input referred noise and total power consumption are 11 μVrms and 277nW respectively.
{"title":"Sub-μW Front-End Low Noise Amplifier for Neural Recording Applications","authors":"Riccardo Della Sala, F. Centurelli, P. Monsurrò, G. Scotti","doi":"10.1109/prime55000.2022.9816833","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816833","url":null,"abstract":"Multi-channel neural recording systems are more and more required for neuroscience research and to cope with neurological disorders. Such systems are based on brain-implantable integrated devices with stringent requirements on supply voltage, power consumption and area footprint. A very low power, low noise fully differential front-end amplifier for neural signals processing is presented in this paper. The proposed amplifier architecture exploits two fully differential OTAs with Arbel topology operating in sub-threshold, and allows AC coupling with a high offset electrode while guaranteeing a very low high-pass cut-off frequency without increasing the equivalent input noise. The neural recording front-end has been designed referring to a 0.13-μm CMOS process. The proposed amplifier operates with a supply voltage as low as 0. 3V with a mid-band gain of 40dB and a -3dB bandwidth from 0.1 Hz to 10 kHz. Input referred noise and total power consumption are 11 μVrms and 277nW respectively.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131834999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816824
Riccardo Della Sala, G. Scotti
In this work we demonstrate that the DD-cell, previously proposed by the authors to implement weak PUFs, can behave also as a TRNG, thus allowing the implementation of PUF and TRNG primitives based on the same entropy source. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA device, and both PUF and TRNG functions have been verified through an extensive measurement campaign involving PVT variations. Measurements results have shown that the entropy of a DD-cell can reach a value higher than 0.99 without requiring any post-processing.
{"title":"The DD-Cell: a Double Side Entropic Source exploitable as PUF and TRNG","authors":"Riccardo Della Sala, G. Scotti","doi":"10.1109/prime55000.2022.9816824","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816824","url":null,"abstract":"In this work we demonstrate that the DD-cell, previously proposed by the authors to implement weak PUFs, can behave also as a TRNG, thus allowing the implementation of PUF and TRNG primitives based on the same entropy source. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA device, and both PUF and TRNG functions have been verified through an extensive measurement campaign involving PVT variations. Measurements results have shown that the entropy of a DD-cell can reach a value higher than 0.99 without requiring any post-processing.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128778021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816764
I. Cusini, Riccardo Rinaldi, P. Castiglioni, A. Faini, F. Villa
Continuous and real-time monitoring of cardiorespiratory signals by portable and accurate instrumentation is very important for the early diagnosis of cardiovascular diseases. We aim to present a novel photoplethysmography device to assess changes in blood oxygen saturation and beat-by-beat pulse waves of finger blood volumes not affected by possibly occurring variations in oxygen saturation. For this purpose, our device works at three light wavelengths simultaneously and is based on a Single-Photon Avalanche Diode to evaluate the feasibility of using this technology in contact photoplethysmography. Our preliminary validation shows that the device is robust against movement artifacts and provides measures that reflect the physiological cardiorespiratory adaptations to the Valsalva maneuver, suggesting its overall reliability and possible use in cardiovascular monitoring.
{"title":"Three-wavelength SPAD-based photoplethysmography","authors":"I. Cusini, Riccardo Rinaldi, P. Castiglioni, A. Faini, F. Villa","doi":"10.1109/prime55000.2022.9816764","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816764","url":null,"abstract":"Continuous and real-time monitoring of cardiorespiratory signals by portable and accurate instrumentation is very important for the early diagnosis of cardiovascular diseases. We aim to present a novel photoplethysmography device to assess changes in blood oxygen saturation and beat-by-beat pulse waves of finger blood volumes not affected by possibly occurring variations in oxygen saturation. For this purpose, our device works at three light wavelengths simultaneously and is based on a Single-Photon Avalanche Diode to evaluate the feasibility of using this technology in contact photoplethysmography. Our preliminary validation shows that the device is robust against movement artifacts and provides measures that reflect the physiological cardiorespiratory adaptations to the Valsalva maneuver, suggesting its overall reliability and possible use in cardiovascular monitoring.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125450793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816802
C. Nardi, R. Wunderlich, S. Heinen
This paper presents the design of an integrated active band-pass filter for 1ow-IF or direct down-conversion wake-up receivers suited for IEEE 802.11ba. Two gyrator-based second-order gm-C structures are used to achieve an overall low-pass filtering order of at least 4. Fully differential operational transconductance amplifiers (OTA) with capacitive source degeneration and capacitive load result in a band-pass frequency response. This way, the down-converted signal is filtered and DC offsets from previous stages are suppressed. By adding two programmable gain amplifiers (PGA) that show first-order low-pass behavior as well, the whole structure also acts as a gain stage and the filtering is slightly improved. The band-pass filters and PGAs are arranged in an alternating fashion in order to prevent possible DC offsets from propagating through the chain. Every stage features a common-mode feedback (CMFB) loop. The nominal filter bandwidth is from 150kHz to 2MHz and the upper band edge can be varied between 1.5 MHz and 4. 5MHz. The overall gain is adjustable between 0dB and 42dB and the whole structure only needs 25 $mu$A at 900mV supply voltage. The filter is implemented in a 28nm CMOS technology. The design was verified by post-layout simulations.
{"title":"A Configurable Active Bandpass Filter with DC Offset Suppression for Direct Down-Conversion Wake-Up Receivers in 28 nm","authors":"C. Nardi, R. Wunderlich, S. Heinen","doi":"10.1109/prime55000.2022.9816802","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816802","url":null,"abstract":"This paper presents the design of an integrated active band-pass filter for 1ow-IF or direct down-conversion wake-up receivers suited for IEEE 802.11ba. Two gyrator-based second-order gm-C structures are used to achieve an overall low-pass filtering order of at least 4. Fully differential operational transconductance amplifiers (OTA) with capacitive source degeneration and capacitive load result in a band-pass frequency response. This way, the down-converted signal is filtered and DC offsets from previous stages are suppressed. By adding two programmable gain amplifiers (PGA) that show first-order low-pass behavior as well, the whole structure also acts as a gain stage and the filtering is slightly improved. The band-pass filters and PGAs are arranged in an alternating fashion in order to prevent possible DC offsets from propagating through the chain. Every stage features a common-mode feedback (CMFB) loop. The nominal filter bandwidth is from 150kHz to 2MHz and the upper band edge can be varied between 1.5 MHz and 4. 5MHz. The overall gain is adjustable between 0dB and 42dB and the whole structure only needs 25 $mu$A at 900mV supply voltage. The filter is implemented in a 28nm CMOS technology. The design was verified by post-layout simulations.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"121 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123247027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816757
Sebastian Doliwa, Andreas Erbslöh, K. Seidl, Ioannis Iossifidis
In the context of the development of an implantable embedded system interfacing brain activity and enabling paralyzed patients to interact with devices that are usable on an everyday basis, we designed a real-time-suitable, low-power hardware architecture with an artifact-suppressing analog front-end, connected to a neural signal processing pipeline. As part of the ultra low-noise analog front-end (four-channel), the common average referencing (CAR) algorithm is implemented to reduce spurious signals from the environment by recording the adjacent electrodes of an invasive microelectrode array (MEA). A Field-Programmable Gate Array (FPGA) is used for data acquisition of extracellular spike activity and data transmission via Ethernet to a host computer for external processing of neural signals. The presented prototype achieves an SNR of 38 dB by applying spike inputs with amplitudes of 100 $mu$V using commercially available components.
{"title":"Development of an Analog Front-End for Brain-Computer Interfaces","authors":"Sebastian Doliwa, Andreas Erbslöh, K. Seidl, Ioannis Iossifidis","doi":"10.1109/prime55000.2022.9816757","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816757","url":null,"abstract":"In the context of the development of an implantable embedded system interfacing brain activity and enabling paralyzed patients to interact with devices that are usable on an everyday basis, we designed a real-time-suitable, low-power hardware architecture with an artifact-suppressing analog front-end, connected to a neural signal processing pipeline. As part of the ultra low-noise analog front-end (four-channel), the common average referencing (CAR) algorithm is implemented to reduce spurious signals from the environment by recording the adjacent electrodes of an invasive microelectrode array (MEA). A Field-Programmable Gate Array (FPGA) is used for data acquisition of extracellular spike activity and data transmission via Ethernet to a host computer for external processing of neural signals. The presented prototype achieves an SNR of 38 dB by applying spike inputs with amplitudes of 100 $mu$V using commercially available components.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"265 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123106159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816779
Bram Veraverbeke, Tim Thielemans, Tuur Van Daele, F. Tavernier
This paper presents a fully integrated high-voltage switched-capacitor DC-DC converter in a GaN-on-SOI process. This technology offers high-quality GaN HEMTs with a higher breakdown voltage and lower parasitic capacitances for the same on-resistance as conventional silicon transistors. The presented series-parallel converter integrates the whole converter on a single GaN-die, including the power switches, the gate drivers, and the capacitors. Simulations show an efficiency of 62.6% at a power density of 220 mW/m$text{m}^{2}$ while converting a 240 V input voltage into an output voltage of 47.5 V. To the author’s knowledge, the proposed converter is the first fully integrated DC-DC converter in GaN. Additionally, it has a 3x higher power density and a higher efficiency compared to previously reported monolithic high-voltage converters.
{"title":"A 240V to 47.5 V Fully Integrated Switched-Capacitor Converter in GaN Achieving 62.6% Efficiency at 220 mW/mm2","authors":"Bram Veraverbeke, Tim Thielemans, Tuur Van Daele, F. Tavernier","doi":"10.1109/prime55000.2022.9816779","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816779","url":null,"abstract":"This paper presents a fully integrated high-voltage switched-capacitor DC-DC converter in a GaN-on-SOI process. This technology offers high-quality GaN HEMTs with a higher breakdown voltage and lower parasitic capacitances for the same on-resistance as conventional silicon transistors. The presented series-parallel converter integrates the whole converter on a single GaN-die, including the power switches, the gate drivers, and the capacitors. Simulations show an efficiency of 62.6% at a power density of 220 mW/m$text{m}^{2}$ while converting a 240 V input voltage into an output voltage of 47.5 V. To the author’s knowledge, the proposed converter is the first fully integrated DC-DC converter in GaN. Additionally, it has a 3x higher power density and a higher efficiency compared to previously reported monolithic high-voltage converters.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127751514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816767
M. Garcia-Bosque, R. Aparicio, Guillermo Díez-Señorans, C. Sánchez-Azqueta, S. Celma
In this paper, an analysis regarding the influence of the chosen locations of the ring oscillators in the performance of a ring oscillator Physically Unclonable Function has been carried out. For this purpose, five different strategies to select a small set of locations out of a big set of locations to construct a PUF have been proposed and compared. The analysis reflects that, depending on the chosen selection strategy, the quality of the PUF can be greatly affected, especially in terms of uniqueness.
{"title":"An analysis of the behaviour of a PUF based on ring oscillators depending on their locations","authors":"M. Garcia-Bosque, R. Aparicio, Guillermo Díez-Señorans, C. Sánchez-Azqueta, S. Celma","doi":"10.1109/prime55000.2022.9816767","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816767","url":null,"abstract":"In this paper, an analysis regarding the influence of the chosen locations of the ring oscillators in the performance of a ring oscillator Physically Unclonable Function has been carried out. For this purpose, five different strategies to select a small set of locations out of a big set of locations to construct a PUF have been proposed and compared. The analysis reflects that, depending on the chosen selection strategy, the quality of the PUF can be greatly affected, especially in terms of uniqueness.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"803 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816830
Federico D'Aniello, Andreas Ott, A. Baschirotto
A PLC receiver based on a StrongArm Latch with tunable hysteresis is developed to realize a supply line embedded transceiver for automotive application. Modern cars are complex systems with a huge number of distributed Electronic Control Units (ECUs) with several sensors and actuators. As automotive systems became more complex, new solutions to drastically reduce the amount of cabling must be developed. A supply embedded communication method can be used to decrease weight, cost, and raw materials usage. A key block of the required transceiver is the here proposed receiver that is based on a StrongArm Latch with tunable hysteresis to guarantee performance robustness and circuit sensitivity. A differential buffer and an input divider are used in front of the Latch to provide a fast, stable, and manageable signal. The full transceiver is developed in a 180nm CMOS SOI technology. Extended simulations in an automotive environment model validate the receiver proposal.
{"title":"StrongArm-Latch-Based Receiver for Supply Line Embedded Communication","authors":"Federico D'Aniello, Andreas Ott, A. Baschirotto","doi":"10.1109/prime55000.2022.9816830","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816830","url":null,"abstract":"A PLC receiver based on a StrongArm Latch with tunable hysteresis is developed to realize a supply line embedded transceiver for automotive application. Modern cars are complex systems with a huge number of distributed Electronic Control Units (ECUs) with several sensors and actuators. As automotive systems became more complex, new solutions to drastically reduce the amount of cabling must be developed. A supply embedded communication method can be used to decrease weight, cost, and raw materials usage. A key block of the required transceiver is the here proposed receiver that is based on a StrongArm Latch with tunable hysteresis to guarantee performance robustness and circuit sensitivity. A differential buffer and an input divider are used in front of the Latch to provide a fast, stable, and manageable signal. The full transceiver is developed in a 180nm CMOS SOI technology. Extended simulations in an automotive environment model validate the receiver proposal.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121794904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816770
G. Meo, D. Caro, N. Petra, A. Strollo
In this paper we propose a novel approximate implementation for the Delayed Least Mean Square (DLMS) filter, able to improve the power consumption while preserving the learning capabilities. In order to minimize the switching activity, we exploit the magnitude of the error signal to update the filter coefficients. Moreover, the FIR section of the adaptive filter is approximated by using a novel approximate fused multipliers-adder tree, exploiting a partial products cancellation and correction technique. Simulation results show that the convergence properties of the proposed filters are practically unchanged with respect to the original DLMS algorithm. Syntheses in 28 nm technology show a power saving of 53.7% that surpass the state of the art.
{"title":"A novel low-power DLMS adaptive filter with sign-magnitude learning and approximated FIR section","authors":"G. Meo, D. Caro, N. Petra, A. Strollo","doi":"10.1109/prime55000.2022.9816770","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816770","url":null,"abstract":"In this paper we propose a novel approximate implementation for the Delayed Least Mean Square (DLMS) filter, able to improve the power consumption while preserving the learning capabilities. In order to minimize the switching activity, we exploit the magnitude of the error signal to update the filter coefficients. Moreover, the FIR section of the adaptive filter is approximated by using a novel approximate fused multipliers-adder tree, exploiting a partial products cancellation and correction technique. Simulation results show that the convergence properties of the proposed filters are practically unchanged with respect to the original DLMS algorithm. Syntheses in 28 nm technology show a power saving of 53.7% that surpass the state of the art.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124251847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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