Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816822
H. Lotfi, Mohamed Atef Hassan, M. Kern, J. Anders
We present a chip-integrated C-band transceiver for electron paramagnetic resonance (EPR) spectroscopy, implemented in a 130-nm SiGe BiCMOS technology. The presented EPR-on-a-chip transceiver displays an excellent minimum in-band noise Figure of 0.82 dB and a peak in-band output power $P_{mathrm{sat}}$ of 9.8 dBm. Furthermore, the presented chip provides a wide operating frequency range from 6 GHz to 8 GHz, which is crucial for detecting wideband EPR signals. The receiver and two-stage four-way combined power amplifier provide (conversion) gains of 32.8 dB and 13 dB, respectively. In proof-of-concept EPR measurements using an off-chip PCB coil as a detector and the standard EPR sample BDPA ($alpha,gamma$-bisdiphenylene-$beta$-phenylallyl), the presented chip achieves a competitive spin sensitivity of $8times 10^{10}$ spins/$sqrt{mathrm{Hz}}$ over an active volume of 31 n1.
{"title":"A Compact C-band EPR-on-a-chip Transceiver in 130-nm SiGe BiCMOS","authors":"H. Lotfi, Mohamed Atef Hassan, M. Kern, J. Anders","doi":"10.1109/prime55000.2022.9816822","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816822","url":null,"abstract":"We present a chip-integrated C-band transceiver for electron paramagnetic resonance (EPR) spectroscopy, implemented in a 130-nm SiGe BiCMOS technology. The presented EPR-on-a-chip transceiver displays an excellent minimum in-band noise Figure of 0.82 dB and a peak in-band output power $P_{mathrm{sat}}$ of 9.8 dBm. Furthermore, the presented chip provides a wide operating frequency range from 6 GHz to 8 GHz, which is crucial for detecting wideband EPR signals. The receiver and two-stage four-way combined power amplifier provide (conversion) gains of 32.8 dB and 13 dB, respectively. In proof-of-concept EPR measurements using an off-chip PCB coil as a detector and the standard EPR sample BDPA ($alpha,gamma$-bisdiphenylene-$beta$-phenylallyl), the presented chip achieves a competitive spin sensitivity of $8times 10^{10}$ spins/$sqrt{mathrm{Hz}}$ over an active volume of 31 n1.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130372801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816744
S. Böller, T. Grenter, A. Hennig, A. Grabmaier
In this work we combine the retrodirectivity of Van Atta arrays with the direction-independent power reception capability of rectenna arrays to compensate for the high free-space path loss in the super high frequency (SHF) band. Currently the range of SHF systems using modulated backscattering at passive transponders is limited by this effect. To overcome this problem we propose a new array structure connecting multiple antennas and rectifiers through a passive network. By using the proposed approach on an ${N}times{N}$ array, energy and backscatter range can both be increased by a factor of N. This enables radio frequency identification (RFID) systems in the SHF band to achieve similar coverage as ultra high frequency (UHF)-RFID systems, while gaining the advantage of higher available bandwidth. Influences from the direct environment of the transponders can be compensated for and the possibility of high accuracy transponder localization arises.
{"title":"Retrodirective Rectenna Arrays for passive SHF-RFID Transponders","authors":"S. Böller, T. Grenter, A. Hennig, A. Grabmaier","doi":"10.1109/prime55000.2022.9816744","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816744","url":null,"abstract":"In this work we combine the retrodirectivity of Van Atta arrays with the direction-independent power reception capability of rectenna arrays to compensate for the high free-space path loss in the super high frequency (SHF) band. Currently the range of SHF systems using modulated backscattering at passive transponders is limited by this effect. To overcome this problem we propose a new array structure connecting multiple antennas and rectifiers through a passive network. By using the proposed approach on an ${N}times{N}$ array, energy and backscatter range can both be increased by a factor of N. This enables radio frequency identification (RFID) systems in the SHF band to achieve similar coverage as ultra high frequency (UHF)-RFID systems, while gaining the advantage of higher available bandwidth. Influences from the direct environment of the transponders can be compensated for and the possibility of high accuracy transponder localization arises.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130548847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816826
Alessandro Tontini, L. Gasparini, Enrico Manuzzato, M. Perenzoni, R. Passerone
We present the results of Montecarlo simulations and measurements focusing on the analysis of two techniques aimed at reducing the negative effect of background light in Single Photon Avalanche Diode (SPAD)-based Light Detection And Ranging (LiDAR) systems. The first technique, known as photon coincidence technique, exploits the temporal proximity of multiple detections to reject background light and maximize the detection of photons belonging to the target reflection. The second technique, named Auto-Sensitivity (AS) technique, reduces the photon-detection probability (PDP) if a certain background illumination level is detected, to avoid the risk of saturating SPADs due to intense background level. The two methods are first compared to each other, showing that the photon coincidence technique outperforms the AS technique. Then, the two techniques are operated together, resulting in an increase of the maximum achievable measurement range if the AS technique is applied on top of the photon coincidence technique.
{"title":"Comparison of background-rejection techniques for SPAD-based LiDAR systems","authors":"Alessandro Tontini, L. Gasparini, Enrico Manuzzato, M. Perenzoni, R. Passerone","doi":"10.1109/prime55000.2022.9816826","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816826","url":null,"abstract":"We present the results of Montecarlo simulations and measurements focusing on the analysis of two techniques aimed at reducing the negative effect of background light in Single Photon Avalanche Diode (SPAD)-based Light Detection And Ranging (LiDAR) systems. The first technique, known as photon coincidence technique, exploits the temporal proximity of multiple detections to reject background light and maximize the detection of photons belonging to the target reflection. The second technique, named Auto-Sensitivity (AS) technique, reduces the photon-detection probability (PDP) if a certain background illumination level is detected, to avoid the risk of saturating SPADs due to intense background level. The two methods are first compared to each other, showing that the photon coincidence technique outperforms the AS technique. Then, the two techniques are operated together, resulting in an increase of the maximum achievable measurement range if the AS technique is applied on top of the photon coincidence technique.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133947345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816763
F. Gagliardi, Andrea Ria, G. Manfredini, P. Bruschi, M. Piotto
In this work, we present a novel approach for the on-chip synthesis of sinusoidal signals for low-size and low-power applications. The original aspect of the proposed solution is the ability to generate linearly interpolated signals by means of analog interpolation. This gives rise to notable distortion performances with a low circuit complexity. The potentiality of the proposed approach was verified by means of electrical simulations performed on a prototype designed with a standard $0.18mu{mathrm m}$ CMOS process. A THD as low as 0.59%, calculated considering also the aliasing effect implied by the linear interpolation, was obtained at a 100 kHz sinewave frequency. The power consumption is around 300 $mu{mathrm W}$. The possibility of varying the sinewave frequency in a 3-decade wide range was also assessed. Results obtained from 50 Monte Carlo runs at $f_{0}=100 {mathrm kHz}$ indicated a worst-case THD around 1.3%.
{"title":"A 3-decade-frequency-range Sinewave Synthesizer with Analog Piecewise-linear Interpolation","authors":"F. Gagliardi, Andrea Ria, G. Manfredini, P. Bruschi, M. Piotto","doi":"10.1109/prime55000.2022.9816763","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816763","url":null,"abstract":"In this work, we present a novel approach for the on-chip synthesis of sinusoidal signals for low-size and low-power applications. The original aspect of the proposed solution is the ability to generate linearly interpolated signals by means of analog interpolation. This gives rise to notable distortion performances with a low circuit complexity. The potentiality of the proposed approach was verified by means of electrical simulations performed on a prototype designed with a standard $0.18mu{mathrm m}$ CMOS process. A THD as low as 0.59%, calculated considering also the aliasing effect implied by the linear interpolation, was obtained at a 100 kHz sinewave frequency. The power consumption is around 300 $mu{mathrm W}$. The possibility of varying the sinewave frequency in a 3-decade wide range was also assessed. Results obtained from 50 Monte Carlo runs at $f_{0}=100 {mathrm kHz}$ indicated a worst-case THD around 1.3%.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133311906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816807
Katia Samperi, S. Pennisi, F. Pulvirenti, G. Palmisano
This paper presents the design of a GaN constant-Gm transconductor for smart-power applications. The proposed solution exploits source degeneration to linearize the transconductance and three cascode current mirrors to increase the transconductance and provide differential to single-ended conversion. Moreover, a biasing section is added to cope with the wide process spread, especially in threshold voltages, of both enhancement and depletion GaN transistors. Nominal simulation results show that the proposed transconductor, supplied from 6-V and biased with 655 μ A provides 1 mS transconductance, within a linear differential input range of ±100 mV up to more than 10 MHz.
{"title":"1-mS constant-Gm GaN transconductor with embedded process compensation","authors":"Katia Samperi, S. Pennisi, F. Pulvirenti, G. Palmisano","doi":"10.1109/prime55000.2022.9816807","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816807","url":null,"abstract":"This paper presents the design of a GaN constant-Gm transconductor for smart-power applications. The proposed solution exploits source degeneration to linearize the transconductance and three cascode current mirrors to increase the transconductance and provide differential to single-ended conversion. Moreover, a biasing section is added to cope with the wide process spread, especially in threshold voltages, of both enhancement and depletion GaN transistors. Nominal simulation results show that the proposed transconductor, supplied from 6-V and biased with 655 μ A provides 1 mS transconductance, within a linear differential input range of ±100 mV up to more than 10 MHz.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133327282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816809
Xiao Liu, Mark Zwolinski
Many cache designs have been proposed to guard against last-level cache, contention-based, side-channel attacks. One of the most well-known implementations, CEASER-S, applies an encryption cypher with a periodically changing key as a cache indexing function. By increasing the re-keying frequency, CEASER-S can defeat an attack. However, this can lead to performance degradation. In this paper, we propose cache logical associativity. By combining this approach with CEASER-S, our cache, CEASER-SH, sacrifices less performance while maintaining the same security level against more advanced contention-based side-channel attacks. For example, compared with CEASER-S, CEASER-SH with a logical associativity of 3 can reduce the miss rate degradation by about 30% and that of the CPI by 1% while maintaining the same security level against a strong Prime+Probe attack.
{"title":"Mitigating Cache Contention-Based Attacks by Logical Associativity","authors":"Xiao Liu, Mark Zwolinski","doi":"10.1109/prime55000.2022.9816809","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816809","url":null,"abstract":"Many cache designs have been proposed to guard against last-level cache, contention-based, side-channel attacks. One of the most well-known implementations, CEASER-S, applies an encryption cypher with a periodically changing key as a cache indexing function. By increasing the re-keying frequency, CEASER-S can defeat an attack. However, this can lead to performance degradation. In this paper, we propose cache logical associativity. By combining this approach with CEASER-S, our cache, CEASER-SH, sacrifices less performance while maintaining the same security level against more advanced contention-based side-channel attacks. For example, compared with CEASER-S, CEASER-SH with a logical associativity of 3 can reduce the miss rate degradation by about 30% and that of the CPI by 1% while maintaining the same security level against a strong Prime+Probe attack.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115014281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816765
S. Tedesco
The design of a low-power, 64-channels front-end ASIC for Silicon Photomultipliers is presented. The chip is being developed in a 65 nm CMOS technology and it is optimised for space applications. In each channel, the current pulse delivered by the sensor is amplified, converted into a voltage and sampled at 200 MS/s by an array of 256 cells, each containing a storage capacitor and a single-slope ADC. If a trigger signal is received, the analog samples are digitised in parallel and sent off-chip, otherwise the memory cells are overwritten. The ADC resolution can be programmed in the 7-12 bit range, trading-off dead time with amplitude resolution. The target power consumption is 5 mW/channel. The chip can thus take snapshots of relatively rare events at high sampling rate with low power. The analog memory can be partitioned in shorter slots that work in a time-interleaved configuration. In this way, the input data stream, which usually follows a Poisson distribution, can be derandomized. The chip is scheduled to be submitted for fabrication in the second quarter of 2022. In the paper, the design concept is presented and the ongoing verifications are discussed.
{"title":"A Low-Power, Short Dead-Time ASIC for SiPMs Readout with 200 MS/s Sampling Rate","authors":"S. Tedesco","doi":"10.1109/prime55000.2022.9816765","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816765","url":null,"abstract":"The design of a low-power, 64-channels front-end ASIC for Silicon Photomultipliers is presented. The chip is being developed in a 65 nm CMOS technology and it is optimised for space applications. In each channel, the current pulse delivered by the sensor is amplified, converted into a voltage and sampled at 200 MS/s by an array of 256 cells, each containing a storage capacitor and a single-slope ADC. If a trigger signal is received, the analog samples are digitised in parallel and sent off-chip, otherwise the memory cells are overwritten. The ADC resolution can be programmed in the 7-12 bit range, trading-off dead time with amplitude resolution. The target power consumption is 5 mW/channel. The chip can thus take snapshots of relatively rare events at high sampling rate with low power. The analog memory can be partitioned in shorter slots that work in a time-interleaved configuration. In this way, the input data stream, which usually follows a Poisson distribution, can be derandomized. The chip is scheduled to be submitted for fabrication in the second quarter of 2022. In the paper, the design concept is presented and the ongoing verifications are discussed.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134625692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816823
Riccardo Della Sala, F. Centurelli, P. Monsurrò, G. Scotti
This paper presents a novel ultra-low-power ultra-low-voltage operational transconductance amplifier (OTA). The OTA operates with a 0. 3V supply voltage and shows remarkable bandwidth performance with very limited power consumption, owing to the use of current mirrors with gain. Low impedance internal nodes of the current mirrors allow to boost gain and bandwidth, adding only high-frequency poles to the frequency response. Therefore, the compensation of the proposed OTA can be achieved through a dominant pole at the output, as in conventional cascode amplifiers. The circuit employs two identical input stages with cross-coupled inputs to improve common-mode rejection ratio (CMRR) performance, and a differential-to-single-ended output stage. The resulting architecture achieves a remarkable FOMs value, as demonstrated by the simulations performed in a commercial 130nm CMOS technology.
{"title":"High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain","authors":"Riccardo Della Sala, F. Centurelli, P. Monsurrò, G. Scotti","doi":"10.1109/prime55000.2022.9816823","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816823","url":null,"abstract":"This paper presents a novel ultra-low-power ultra-low-voltage operational transconductance amplifier (OTA). The OTA operates with a 0. 3V supply voltage and shows remarkable bandwidth performance with very limited power consumption, owing to the use of current mirrors with gain. Low impedance internal nodes of the current mirrors allow to boost gain and bandwidth, adding only high-frequency poles to the frequency response. Therefore, the compensation of the proposed OTA can be achieved through a dominant pole at the output, as in conventional cascode amplifiers. The circuit employs two identical input stages with cross-coupled inputs to improve common-mode rejection ratio (CMRR) performance, and a differential-to-single-ended output stage. The resulting architecture achieves a remarkable FOMs value, as demonstrated by the simulations performed in a commercial 130nm CMOS technology.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116398554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816831
Stefan Reich, Gunnar Kunze, Mark A. Sporer, M. Ortmanns
Chopping is widely used to mitigate 1/f noise and offset of amplifiers, e.g., in implantable biomedical devices where very-low-frequency signals are of interest. The main disadvantages of chopping is the degradation of input impedance and the presence of chopping ripples superposing the recorded neural signal. These ripples are especially critical in sampled systems, as back-folding into the baseband should be avoided. Additionally, loop linearity and stability can be compromised by chopping ripples in feedback systems. This article compares ripple reduction strategies from prior art and presents a mathematical analysis of a simple and effective technique by delayed sampling. A description of the signal chain is derived in order to develop a model, which is subsequently used to demonstrate the effectiveness of the presented method. System-level simulations verify the functionality and yield a 30 dB ripple reduction at virtually no additional hardware expense.
{"title":"Analysis of Chopper Ripple Reduction by Delayed Sampling","authors":"Stefan Reich, Gunnar Kunze, Mark A. Sporer, M. Ortmanns","doi":"10.1109/prime55000.2022.9816831","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816831","url":null,"abstract":"Chopping is widely used to mitigate 1/f noise and offset of amplifiers, e.g., in implantable biomedical devices where very-low-frequency signals are of interest. The main disadvantages of chopping is the degradation of input impedance and the presence of chopping ripples superposing the recorded neural signal. These ripples are especially critical in sampled systems, as back-folding into the baseband should be avoided. Additionally, loop linearity and stability can be compromised by chopping ripples in feedback systems. This article compares ripple reduction strategies from prior art and presents a mathematical analysis of a simple and effective technique by delayed sampling. A description of the signal chain is derived in order to develop a model, which is subsequently used to demonstrate the effectiveness of the presented method. System-level simulations verify the functionality and yield a 30 dB ripple reduction at virtually no additional hardware expense.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122234372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816812
Xiaowei Liu, E. Bonizzoni, Yao Liu, F. Maloberti
The linearity of a coherent TIA for optical transceivers is studied. The goal of the transimpedance gain is $ 74mathrm{d}mathrm{B}Omega$. The study of the design parameters that limit each block’s linearity provides design directions for a TIA with THD equal to or lower than 1%. The analytical study uses the Ebers-Moll model and achieves design criteria confirmed by transistor-level simulations, carried out using a $130mathrm{n}mathrm{m}$ BiCMOS process.
{"title":"Linearity Analysis of BiCMOS Coherent TIAs","authors":"Xiaowei Liu, E. Bonizzoni, Yao Liu, F. Maloberti","doi":"10.1109/prime55000.2022.9816812","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816812","url":null,"abstract":"The linearity of a coherent TIA for optical transceivers is studied. The goal of the transimpedance gain is $ 74mathrm{d}mathrm{B}Omega$. The study of the design parameters that limit each block’s linearity provides design directions for a TIA with THD equal to or lower than 1%. The analytical study uses the Ebers-Moll model and achieves design criteria confirmed by transistor-level simulations, carried out using a $130mathrm{n}mathrm{m}$ BiCMOS process.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125117894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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