Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816792
Giuseppe Barbalace, D. Natali, Martina Scolari
Silver-ink tracks features deposited through piezoelectric Drop-on-Demand printing, thanks to an innovative state-of-art printer, are described. Precise printing-trajectories are implemented to limit track-width and to increase thickness with the purpose of manufacturing high-conductivity spirals in order to create inductors for Very High Frequency power transfer applications. More layers are deposited onto polyimide without provoking noticeable track-width variations. The described printing methodology enabled a rapid and effective thickness increase, essential to manufacture high quality components characterized by low values of sheet resistance together with high values of quality factor.
{"title":"Manufacturing of silver-ink micrometer inductors through multilayer D.O.D. printing for VHF Power Transfer","authors":"Giuseppe Barbalace, D. Natali, Martina Scolari","doi":"10.1109/prime55000.2022.9816792","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816792","url":null,"abstract":"Silver-ink tracks features deposited through piezoelectric Drop-on-Demand printing, thanks to an innovative state-of-art printer, are described. Precise printing-trajectories are implemented to limit track-width and to increase thickness with the purpose of manufacturing high-conductivity spirals in order to create inductors for Very High Frequency power transfer applications. More layers are deposited onto polyimide without provoking noticeable track-width variations. The described printing methodology enabled a rapid and effective thickness increase, essential to manufacture high quality components characterized by low values of sheet resistance together with high values of quality factor.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132210570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816806
Andrea Costamagna, G. Micheli
Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessary overuse of resources or is hardly possible to meet. The latter case is typical of incompletely specified synthesis problems, targeting the hardware implementation of a Boolean function from a partial knowledge of its care set. The missing elements of the care set are named don’t knows. Previous works identified information theory-based decomposition strategies as powerful synthesis tools. Nonetheless, the definition of an automatic method for approximate synthesis is an open problem, and the approximate counterpart of many logic synthesis techniques is still missing. In this paper, we extend a disjoint support decomposition algorithm to target Boolean functions in the presence of don’t knows. Furthermore, we integrate the decomposition in an information theory-based synthesis flow. Relative experiments on the IWLS2020 benchmarks show that, on average, the addition of the designed decomposition to the flow reduces by 15.81% the number of gates and by 9.66% the depth.
{"title":"Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition","authors":"Andrea Costamagna, G. Micheli","doi":"10.1109/prime55000.2022.9816806","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816806","url":null,"abstract":"Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessary overuse of resources or is hardly possible to meet. The latter case is typical of incompletely specified synthesis problems, targeting the hardware implementation of a Boolean function from a partial knowledge of its care set. The missing elements of the care set are named don’t knows. Previous works identified information theory-based decomposition strategies as powerful synthesis tools. Nonetheless, the definition of an automatic method for approximate synthesis is an open problem, and the approximate counterpart of many logic synthesis techniques is still missing. In this paper, we extend a disjoint support decomposition algorithm to target Boolean functions in the presence of don’t knows. Furthermore, we integrate the decomposition in an information theory-based synthesis flow. Relative experiments on the IWLS2020 benchmarks show that, on average, the addition of the designed decomposition to the flow reduces by 15.81% the number of gates and by 9.66% the depth.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134145199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816827
A. Bettini, T. Cosnier, A. Magnani, O. Syshchyk, M. Borga, S. Decoutere, A. Neviani
The design of an integrated 40A pulsed driver for ToF LiDAR in GaN-on-SOI technology is presented. The produced laser current, generated by a resonant circuit, can achieve sub-nanosecond rise time. The design aims to optimally exploit GaN technology, mitigating source bounce effects and compensating the lack of complementary devices, while preserving reliability. The integration process minimizes parasitics via wafer-level-chip-scale packaging (WLCSP), enhancing the performance of the driver.
{"title":"Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology","authors":"A. Bettini, T. Cosnier, A. Magnani, O. Syshchyk, M. Borga, S. Decoutere, A. Neviani","doi":"10.1109/prime55000.2022.9816827","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816827","url":null,"abstract":"The design of an integrated 40A pulsed driver for ToF LiDAR in GaN-on-SOI technology is presented. The produced laser current, generated by a resonant circuit, can achieve sub-nanosecond rise time. The design aims to optimally exploit GaN technology, mitigating source bounce effects and compensating the lack of complementary devices, while preserving reliability. The integration process minimizes parasitics via wafer-level-chip-scale packaging (WLCSP), enhancing the performance of the driver.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134232827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816813
F. Malena, X. Aragonès, D. Mateo, Michele Caselli, A. Boni
This paper presents the design of an RF receiver front-end for IoT application, integrating a low noise amplifier (LNA) and an active mixer. The circuit is designed in 28-nm FDSOI technology, to operate on the ISM 2.4-2.5 GHz band. The inductor-less LNA exploits the parasitic package inductance as resonant load, limiting chip area and costs. The receiver, designed for the stringent requirements of the application, operates with a voltage supply of 0.35 V, and it exhibits in simulation a power consumption below 45 μW. Besides, it achieves a voltage gain of 27.4 dB, a Third Order Input Intercept Point (IIP3) of -26.8dBm, and a noise Figure (NF) of 12.8 dB, with an intermediate frequency (FI) of 2 MHz. The small area of only 0.0021 mm2, combined with the low power consumption and operating voltage, makes the proposed RF receiver well-suited for the IoT application domain.
{"title":"An Ultra Low-Voltage RF Front-end Receiver for IoT Devices","authors":"F. Malena, X. Aragonès, D. Mateo, Michele Caselli, A. Boni","doi":"10.1109/prime55000.2022.9816813","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816813","url":null,"abstract":"This paper presents the design of an RF receiver front-end for IoT application, integrating a low noise amplifier (LNA) and an active mixer. The circuit is designed in 28-nm FDSOI technology, to operate on the ISM 2.4-2.5 GHz band. The inductor-less LNA exploits the parasitic package inductance as resonant load, limiting chip area and costs. The receiver, designed for the stringent requirements of the application, operates with a voltage supply of 0.35 V, and it exhibits in simulation a power consumption below 45 μW. Besides, it achieves a voltage gain of 27.4 dB, a Third Order Input Intercept Point (IIP3) of -26.8dBm, and a noise Figure (NF) of 12.8 dB, with an intermediate frequency (FI) of 2 MHz. The small area of only 0.0021 mm2, combined with the low power consumption and operating voltage, makes the proposed RF receiver well-suited for the IoT application domain.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131612635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816825
Jingjing Li, Xingchen Chao, Qiang Li
Fast fourier transform (FFT) is indispensable in multi-carrier radio frequency transform systems, especially in the Orthogonal Frequency Division Multiplexing (OFDM) system. And almost all transform systems implement FFT algorithms in the digital domain. Compared with the realization in digital domain, the implementation in analog domain brings greater advantages in speed and power consumption. This paper proposes a new type of analog Fast fourier transform (AFFT) system, analyzes the algorithm choice and compares the advantages and disadvantages of different algorithms, sets up the system model with non-ideal factors, constructs the specific circuit and compares the performance with different systems.
{"title":"16- and 64-Point Analog Computing of FFT with Improved Performance and Efficiency","authors":"Jingjing Li, Xingchen Chao, Qiang Li","doi":"10.1109/prime55000.2022.9816825","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816825","url":null,"abstract":"Fast fourier transform (FFT) is indispensable in multi-carrier radio frequency transform systems, especially in the Orthogonal Frequency Division Multiplexing (OFDM) system. And almost all transform systems implement FFT algorithms in the digital domain. Compared with the realization in digital domain, the implementation in analog domain brings greater advantages in speed and power consumption. This paper proposes a new type of analog Fast fourier transform (AFFT) system, analyzes the algorithm choice and compares the advantages and disadvantages of different algorithms, sets up the system model with non-ideal factors, constructs the specific circuit and compares the performance with different systems.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131185966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816821
David Palomeque-Mangut, A. Schmid, Á. Rodríguez-Vázquez, M. Delgado-Restituto
This paper proposes a system to transfer both mW-power and Mbps-data over an inductive link using a single pair of coils. The system is able to handle a wide range of loads by implementing a load adapter block that divides the operation into two phases: a Power Transfer Phase (PTP) and a Data Transfer Phase (DTP). On the one hand, during PTP, a constant amount of power is drawn from the inductive link, regardless of the current demanded by the load. On the other hand, during DTP, the load is powered with external capacitors, allowing the inductive link to be used for data transmission. With this architecture, intended to be used in a neural implant, power can be delivered to a wide range of loads without affecting the uplink/downlink data communication reliability and with no need of extra coils. Thus, the proposed solution permits minimizing the overall size of the neural implant. An electrical mixed-signal model of the system is described and implemented in MATLAB Simulink through Simscape Electrical and Stateflow toolboxes. Simulations performed on the electrical model of the system are shown and discussed.
{"title":"Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils","authors":"David Palomeque-Mangut, A. Schmid, Á. Rodríguez-Vázquez, M. Delgado-Restituto","doi":"10.1109/prime55000.2022.9816821","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816821","url":null,"abstract":"This paper proposes a system to transfer both mW-power and Mbps-data over an inductive link using a single pair of coils. The system is able to handle a wide range of loads by implementing a load adapter block that divides the operation into two phases: a Power Transfer Phase (PTP) and a Data Transfer Phase (DTP). On the one hand, during PTP, a constant amount of power is drawn from the inductive link, regardless of the current demanded by the load. On the other hand, during DTP, the load is powered with external capacitors, allowing the inductive link to be used for data transmission. With this architecture, intended to be used in a neural implant, power can be delivered to a wide range of loads without affecting the uplink/downlink data communication reliability and with no need of extra coils. Thus, the proposed solution permits minimizing the overall size of the neural implant. An electrical mixed-signal model of the system is described and implemented in MATLAB Simulink through Simscape Electrical and Stateflow toolboxes. Simulations performed on the electrical model of the system are shown and discussed.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132148236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816800
Emanuel Marrazzo, F. Spagnolo, S. Perri
Transposed convolution is a crucial operation in several computer vision applications, including emerging Convolutional Neural Networks for super-resolution, generative adversarial and segmentation tasks. Such algorithms deal with high computational loads and memory requirements, which hinder their implementation in real-time and power-constrained embedded systems. In addition, they may adopt different kernel sizes along the network, thus making the design of flexible yet efficient hardware architectures highly desirable. This paper presents a reconfigurable accelerator able to runtime adapt its computational capabilities to perform transposed convolution with different kernel sizes. When accommodated within the Xilinx XC7Z020 and XC7K410T chips, the proposed design dissipates less than 95 mW at 125MHz and 179 mW at 250MHz, exhibiting a throughput of 1.95 and 3.9 Giga output per second, respectively. Both the implementations overcome state-of-the-art counterparts, achieving an energy efficiency up to 4.4 times higher. When used to accelerate the Fast Super Resolution Convolutional Neural Networks, the novel reconfigurable architecture achieves an energy efficiency at least 23% better than the competitors.
{"title":"Runtime Reconfigurable Hardware Accelerator for Energy-Efficient Transposed Convolutions","authors":"Emanuel Marrazzo, F. Spagnolo, S. Perri","doi":"10.1109/prime55000.2022.9816800","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816800","url":null,"abstract":"Transposed convolution is a crucial operation in several computer vision applications, including emerging Convolutional Neural Networks for super-resolution, generative adversarial and segmentation tasks. Such algorithms deal with high computational loads and memory requirements, which hinder their implementation in real-time and power-constrained embedded systems. In addition, they may adopt different kernel sizes along the network, thus making the design of flexible yet efficient hardware architectures highly desirable. This paper presents a reconfigurable accelerator able to runtime adapt its computational capabilities to perform transposed convolution with different kernel sizes. When accommodated within the Xilinx XC7Z020 and XC7K410T chips, the proposed design dissipates less than 95 mW at 125MHz and 179 mW at 250MHz, exhibiting a throughput of 1.95 and 3.9 Giga output per second, respectively. Both the implementations overcome state-of-the-art counterparts, achieving an energy efficiency up to 4.4 times higher. When used to accelerate the Fast Super Resolution Convolutional Neural Networks, the novel reconfigurable architecture achieves an energy efficiency at least 23% better than the competitors.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128853860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816803
Simone Giroletti, L. Ratti, C. Vacchi
This work is concerned with the definition of an algorithm for the design of fast parallel counters suitable for counting 1’s in large arrays of binary signal sources. One example of such systems is the silicon photomultiplier (SiPM), consisting of an array of SPADs (single photon avalanche diodes) each one providing a high output level when hit by a photon. The paper, besides describing the algorithm, will present and discuss a set of computational tools for estimating the design parameters of interest, such as area, power and delay, as a function of the number of cells to read out.
{"title":"Design Algorithm for N-bit Input Parallel Counters in Application to dSiPM Readout","authors":"Simone Giroletti, L. Ratti, C. Vacchi","doi":"10.1109/prime55000.2022.9816803","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816803","url":null,"abstract":"This work is concerned with the definition of an algorithm for the design of fast parallel counters suitable for counting 1’s in large arrays of binary signal sources. One example of such systems is the silicon photomultiplier (SiPM), consisting of an array of SPADs (single photon avalanche diodes) each one providing a high output level when hit by a photon. The paper, besides describing the algorithm, will present and discuss a set of computational tools for estimating the design parameters of interest, such as area, power and delay, as a function of the number of cells to read out.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124305782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816819
Sebastian Simmich, R. Rieger
This paper presents the analysis of two low-power noise-efficient multichannel amplifier topologies, the current-reuse and the split-voltage amplifier, using lateral BJT input transistors. The calculated noise, noise-efficiency factor (NEF), and power consumption is compared with simulation results in a 350nm CMOS technology. The designed current-reuse amplifier has a NEF of 3.19 with an input referred noise floor of 8.3 nV/√Hz and the split-voltage amplifier has a NEF of 2.2 and a noise floor of 5.7 nV/√Hz.
{"title":"Analysis of Current-Reuse and Split-Voltage Topology for Biomedical Amplifier Arrays","authors":"Sebastian Simmich, R. Rieger","doi":"10.1109/prime55000.2022.9816819","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816819","url":null,"abstract":"This paper presents the analysis of two low-power noise-efficient multichannel amplifier topologies, the current-reuse and the split-voltage amplifier, using lateral BJT input transistors. The calculated noise, noise-efficiency factor (NEF), and power consumption is compared with simulation results in a 350nm CMOS technology. The designed current-reuse amplifier has a NEF of 3.19 with an input referred noise floor of 8.3 nV/√Hz and the split-voltage amplifier has a NEF of 2.2 and a noise floor of 5.7 nV/√Hz.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114437673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816818
Michele Castriotta, Alexander Falbo, Luca Orsenigo, Fabio Olivieri, G. Ferrari
A fully-integrated CMOS driving circuit for single-photon emitting diodes in silicon, optimized for space applications, is presented. The electronics comprises two 10-bit DACs in order to precisely set the on and off voltages of the diode based on the measured temperature by an integrated temperature sensor. A large driving voltage range of 0-5 V guarantees the maximum flexibility in the working temperature range from 77 K to 300 K. The chip also contains a pulse generator, capable of driving the diode with short pulses down to 20 ns triggered by an external signal, which is essential in a single-photon light source. The integrated circuit is realized in standard 150-nm CMOS technology, with a chip area of 1.2 mm2 and a power consumption less than 6mW.
{"title":"CMOS driving circuit operating down to 77 K for single-photon emitting diode","authors":"Michele Castriotta, Alexander Falbo, Luca Orsenigo, Fabio Olivieri, G. Ferrari","doi":"10.1109/prime55000.2022.9816818","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816818","url":null,"abstract":"A fully-integrated CMOS driving circuit for single-photon emitting diodes in silicon, optimized for space applications, is presented. The electronics comprises two 10-bit DACs in order to precisely set the on and off voltages of the diode based on the measured temperature by an integrated temperature sensor. A large driving voltage range of 0-5 V guarantees the maximum flexibility in the working temperature range from 77 K to 300 K. The chip also contains a pulse generator, capable of driving the diode with short pulses down to 20 ns triggered by an external signal, which is essential in a single-photon light source. The integrated circuit is realized in standard 150-nm CMOS technology, with a chip area of 1.2 mm2 and a power consumption less than 6mW.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116339531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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