Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357935
Qui-Ting Chen, Yen-Chuan Huang, Tai-Cheng Lee
Limitations of frequency response in backplane interconnections impede high-speed data transmission beyond Gbps. A 14-Gb/s 4-PAM adaptive analog equalizer is proposed to compensate the 40-inch backplane interconnections by using a sum-feedback filter (SFF), relaxing the design requirement of the conventional analog feed-forward equalizers (FFE). 4-level pulse amplitude modulation (PAM) is also adopted to increase the transmission data rate over bandwidth-limited channel. The 4-PAM adaptive equalizer has been fabricated in a 0.18-mum CMOS technology, while dissipating 121 mW from a single 1.8-V power supply.
背板互连中频率响应的限制阻碍了超过Gbps的高速数据传输。提出了一种14gb /s的4-PAM自适应模拟均衡器，利用和反馈滤波器(SFF)补偿40英寸背板互连，降低了传统模拟前馈均衡器(FFE)的设计要求。为了在带宽有限的信道中提高传输数据速率，还采用了4级脉冲幅度调制(PAM)。4-PAM自适应均衡器采用0.18 μ m CMOS技术制造，同时从单个1.8 v电源消耗121 mW。
{"title":"A 14-Gb/s 4-PAM Adaptive Analog Equalizer for 40-inch Backplane Interconnections","authors":"Qui-Ting Chen, Yen-Chuan Huang, Tai-Cheng Lee","doi":"10.1109/ASSCC.2006.357935","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357935","url":null,"abstract":"Limitations of frequency response in backplane interconnections impede high-speed data transmission beyond Gbps. A 14-Gb/s 4-PAM adaptive analog equalizer is proposed to compensate the 40-inch backplane interconnections by using a sum-feedback filter (SFF), relaxing the design requirement of the conventional analog feed-forward equalizers (FFE). 4-level pulse amplitude modulation (PAM) is also adopted to increase the transmission data rate over bandwidth-limited channel. The 4-PAM adaptive equalizer has been fabricated in a 0.18-mum CMOS technology, while dissipating 121 mW from a single 1.8-V power supply.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131238491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357868
K. Onizuka, H. Kawaguchi, M. Takamiya, T. Sakurai
An on-chip buck converter which is implemented by stacking chips and which is suitable for on-chip distributed power supply systems is proposed and the operation is experimentally verified for the first time. The manufactured converter achieves the maximum power efficiency of 62% for an output current of 70 mA with a switching frequency of 200 MHz with a 2times2 mm on-chip LC output filter. The active part and the passive LC output filter are implemented on separate chips fabricated in 0.35-mum CMOS and connected with metal bumps. The optimization and improvement of the power efficiency and implementation structure are also discussed.
提出了一种适用于片上分布式电源系统的片上降压变换器，并对其工作原理进行了首次实验验证。该变换器在输出电流为70 mA、开关频率为200 MHz、片上LC输出滤波器为2times2 mm时的最大功率效率为62%。有源部分和无源LC输出滤波器分别在0.35 μ m CMOS芯片上实现，并通过金属凸点连接。本文还讨论了功率效率和实现结构的优化和改进。
{"title":"Stacked-chip Implementation of On-Chip Buck Converter for Power-Aware Distributed Power Supply Systems","authors":"K. Onizuka, H. Kawaguchi, M. Takamiya, T. Sakurai","doi":"10.1109/ASSCC.2006.357868","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357868","url":null,"abstract":"An on-chip buck converter which is implemented by stacking chips and which is suitable for on-chip distributed power supply systems is proposed and the operation is experimentally verified for the first time. The manufactured converter achieves the maximum power efficiency of 62% for an output current of 70 mA with a switching frequency of 200 MHz with a 2times2 mm on-chip LC output filter. The active part and the passive LC output filter are implemented on separate chips fabricated in 0.35-mum CMOS and connected with metal bumps. The optimization and improvement of the power efficiency and implementation structure are also discussed.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122822723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357919
Chien-Kai Hung, Jian-Feng Shiu, I. Chen, Hsin-Shu Chen
A 6-bit 1.6 GS/s CMOS flash ADC using reversed-reference dummy method is demonstrated in a standard 0.18-μm CMOS process. The proposed method improves linearity error at the boundary of offset averaging networks. The prototype circuit exhibits an INL of +0.32/-0.28 LSB and a DNL of +0.28/-0.28 LSB. The SNDR and SFDR achieve 32 and 44 dB at 1.6 GS/s for Nyquist input frequency. The ADC consumes 350 mW at 1.8 V supply and occupies an active chip area of 0.46 mm2.
{"title":"A 6-bit 1.6 GS/s Flash ADC in 0.18-μm CMOS with Reversed-Reference Dummy","authors":"Chien-Kai Hung, Jian-Feng Shiu, I. Chen, Hsin-Shu Chen","doi":"10.1109/ASSCC.2006.357919","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357919","url":null,"abstract":"A 6-bit 1.6 GS/s CMOS flash ADC using reversed-reference dummy method is demonstrated in a standard 0.18-μm CMOS process. The proposed method improves linearity error at the boundary of offset averaging networks. The prototype circuit exhibits an INL of +0.32/-0.28 LSB and a DNL of +0.28/-0.28 LSB. The SNDR and SFDR achieve 32 and 44 dB at 1.6 GS/s for Nyquist input frequency. The ADC consumes 350 mW at 1.8 V supply and occupies an active chip area of 0.46 mm2.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130514871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357837
Soo-Young Oh
Korea has developed the world best IT infra structures and is leading the Internet and mobile phone industry. Last two years, it has set up the IT development strategy, IT839 and leading the world IT industry by the simultaneous development of the IT services, IT infra structures, and IT systems. As a result, Korea has developed and commercialized Terrestrial DMB technology for the mobile TV services. It has also developed the WiBro technology which can provide the 2~10 Mbps mobile Internet service at the moving speed of 60~120 km/h and the cost of $20~30 per month. Both technologies have been selected as ETSI standard and IEEE standard respectively. This year, Korea is trying to commercialize the developed technologies and develop the components and softwares needed by these IT services and systems in order to lead the future ubiquitous IT society. This presentation covers the Korea IT development strategy, its results, and the components technologies needed by the ubiquitous IT society.
{"title":"IT SoC: Enabler of the Ubiquitous Society","authors":"Soo-Young Oh","doi":"10.1109/ASSCC.2006.357837","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357837","url":null,"abstract":"Korea has developed the world best IT infra structures and is leading the Internet and mobile phone industry. Last two years, it has set up the IT development strategy, IT839 and leading the world IT industry by the simultaneous development of the IT services, IT infra structures, and IT systems. As a result, Korea has developed and commercialized Terrestrial DMB technology for the mobile TV services. It has also developed the WiBro technology which can provide the 2~10 Mbps mobile Internet service at the moving speed of 60~120 km/h and the cost of $20~30 per month. Both technologies have been selected as ETSI standard and IEEE standard respectively. This year, Korea is trying to commercialize the developed technologies and develop the components and softwares needed by these IT services and systems in order to lead the future ubiquitous IT society. This presentation covers the Korea IT development strategy, its results, and the components technologies needed by the ubiquitous IT society.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132875049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357909
You-Gang Chen, I-Chyn Wey, An-Yeu Wu
As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.
{"title":"A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment","authors":"You-Gang Chen, I-Chyn Wey, An-Yeu Wu","doi":"10.1109/ASSCC.2006.357909","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357909","url":null,"abstract":"As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131644557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357890
H. Nakano, T. Iwao, T. Hishida, H. Shimomura, T. Izumi, T. Fujino, Y. Okuno, K. Arimoto
In this paper, we propose embedded programmable logic matrix (ePLX) which is suitable for flexible system on chip (SoC). The ePLX architecture is based on the dense two input look-up-table(LUT) array and the hierarchical wiring resources, which are global/local wiring resources and with simple mapping tools. The compile flow of ePLX is also the simple one with the standard design environments, basically. We have verified the advantage of this architecture by programming the function module and mapping the circuits with high usage efficiency and doubling operation speed. The physical architecture of ePLX uses the divided power supply LUT and wiring resources that consists of SRAM with CMOS transfer gate switch elements. These techniques enable to handle the 0.6V level FV controllable programmable devices for the power management SoC. The ePLX can provide the unique additional merits for many applications under the platform design environments.
{"title":"An Embedded Programmable Logic Matrix (ePLX) for flexible functions on SoC","authors":"H. Nakano, T. Iwao, T. Hishida, H. Shimomura, T. Izumi, T. Fujino, Y. Okuno, K. Arimoto","doi":"10.1109/ASSCC.2006.357890","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357890","url":null,"abstract":"In this paper, we propose embedded programmable logic matrix (ePLX) which is suitable for flexible system on chip (SoC). The ePLX architecture is based on the dense two input look-up-table(LUT) array and the hierarchical wiring resources, which are global/local wiring resources and with simple mapping tools. The compile flow of ePLX is also the simple one with the standard design environments, basically. We have verified the advantage of this architecture by programming the function module and mapping the circuits with high usage efficiency and doubling operation speed. The physical architecture of ePLX uses the divided power supply LUT and wiring resources that consists of SRAM with CMOS transfer gate switch elements. These techniques enable to handle the 0.6V level FV controllable programmable devices for the power management SoC. The ePLX can provide the unique additional merits for many applications under the platform design environments.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"26 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133087432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357839
M. Tsai
This presentation starts with evolution of the optical-storage chipsets for PC multimedia towards full-blown, next-generation SOC for digital consumer applications. Design challenges are reviewed and explored from submicron to nanometer eras in multiple levels of technology developments such as market-driven software/applications, advanced system architecture and engineering to address computation and connectivity requirements, performance-demanding but power-efficient circuit and functional blocks and the growing complexity being faced by increasingly large-scale chip integration. SOC companies will need to effectively cope with all incurred engineering issues to successfully achieve their competitive and leading positions.
{"title":"From PC Multimedia Chipsets to Digital Consumer SOC: Evolution and Challenges","authors":"M. Tsai","doi":"10.1109/ASSCC.2006.357839","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357839","url":null,"abstract":"This presentation starts with evolution of the optical-storage chipsets for PC multimedia towards full-blown, next-generation SOC for digital consumer applications. Design challenges are reviewed and explored from submicron to nanometer eras in multiple levels of technology developments such as market-driven software/applications, advanced system architecture and engineering to address computation and connectivity requirements, performance-demanding but power-efficient circuit and functional blocks and the growing complexity being faced by increasingly large-scale chip integration. SOC companies will need to effectively cope with all incurred engineering issues to successfully achieve their competitive and leading positions.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115753928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357945
Sangyoon Lee, Jaeha Kim, Bong-Joon Lee, Hwi-Cheol Kim, Hyung-ho Ko, D. Dong-il Cho, D. Jeong
A bandpass ΔΣ interface IC for sacrificial bulk micromachined inertial sensors is presented. To achieve high resolution without precision analog circuits, the proposed architecture replaces the analog mixer of a chopper-stabilized readout amplifier with a 1-bit, 4th-order bandpass ΔΣ modulator and a digital decimator/demodulator. Leveraging the high over-sampling ratio of 8192 and the supporting circuit techniques, the interface IC provides a 128-Hz, 20-bit digital output with 113 dB peak SNR and 115 dB dynamic range (DR). Fabricated in 0.18 μm CMOS, the IC dissipates 56.1 mW.
{"title":"A Bandpass ΔΣ Interface IC for Sacrificial Bulk Micromachined Inertial Sensors","authors":"Sangyoon Lee, Jaeha Kim, Bong-Joon Lee, Hwi-Cheol Kim, Hyung-ho Ko, D. Dong-il Cho, D. Jeong","doi":"10.1109/ASSCC.2006.357945","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357945","url":null,"abstract":"A bandpass ΔΣ interface IC for sacrificial bulk micromachined inertial sensors is presented. To achieve high resolution without precision analog circuits, the proposed architecture replaces the analog mixer of a chopper-stabilized readout amplifier with a 1-bit, 4th-order bandpass ΔΣ modulator and a digital decimator/demodulator. Leveraging the high over-sampling ratio of 8192 and the supporting circuit techniques, the interface IC provides a 128-Hz, 20-bit digital output with 113 dB peak SNR and 115 dB dynamic range (DR). Fabricated in 0.18 μm CMOS, the IC dissipates 56.1 mW.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127206526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357845
C. Ching-Hsiang Hsu, Yen-Tai Lin, Shih-Jye Shen
We have proposed a programmable non-volatile devices Neobitreg which can be built on any process platform, such as logic, analog, mixed-mode, high voltage, RF, SiGe, BCD, etc., without adding the complications to the existing process platforms. Due to the simplicity of Neobitreg , it has facilitated many applications for better cost/performance. The programmable logic non-volatile devices have been widely used for (1) code storage, (2) high voltage device trimming, (3) analog circuit trimming, (4) power management circuit trimming, (5) security ID, (6) RFID, and (7) memory repair. In this paper, the technology and applications of the new single poly programmable logic non-volatile devices will be presented. We believed that the programmable logic non-volatile devices are very promising for many future applications due to its simplicity, non-volatility and particularly programmability.
{"title":"Future Prospective of Programmable Logic Non-Volatile Device","authors":"C. Ching-Hsiang Hsu, Yen-Tai Lin, Shih-Jye Shen","doi":"10.1109/ASSCC.2006.357845","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357845","url":null,"abstract":"We have proposed a programmable non-volatile devices Neobitreg which can be built on any process platform, such as logic, analog, mixed-mode, high voltage, RF, SiGe, BCD, etc., without adding the complications to the existing process platforms. Due to the simplicity of Neobitreg , it has facilitated many applications for better cost/performance. The programmable logic non-volatile devices have been widely used for (1) code storage, (2) high voltage device trimming, (3) analog circuit trimming, (4) power management circuit trimming, (5) security ID, (6) RFID, and (7) memory repair. In this paper, the technology and applications of the new single poly programmable logic non-volatile devices will be presented. We believed that the programmable logic non-volatile devices are very promising for many future applications due to its simplicity, non-volatility and particularly programmability.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127214877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357913
Chao-Ching Wang, Jinn-Shyan Wang
A high-performance TCAM macro with the folded architecture for IPv6 routing address lookup is designed and presented. The implemented 0.18 mum TCAM macro uses a newly proposed folded architecture on top of the tree-style AND-type match-line and the segmented search-line techniques we proposed previously to achieve a 27% increase in area utilization efficiency and a 10% reduction in energy consumption, while maintaining the world-record search speed.
{"title":"A High-Performance TCAM Macro with the Folded Architecture for IP Routing Address Lookup","authors":"Chao-Ching Wang, Jinn-Shyan Wang","doi":"10.1109/ASSCC.2006.357913","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357913","url":null,"abstract":"A high-performance TCAM macro with the folded architecture for IPv6 routing address lookup is designed and presented. The implemented 0.18 mum TCAM macro uses a newly proposed folded architecture on top of the tree-style AND-type match-line and the segmented search-line techniques we proposed previously to achieve a 27% increase in area utilization efficiency and a 10% reduction in energy consumption, while maintaining the world-record search speed.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127541253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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