Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357857
Sungho Beck, Jeong-Cheol Lee, S. Yoo, Kyoohyun Lim, H. Jung, Jaekyung Han, Munkyung Ahn, Tschang-Hi Lee, Kyung-Lok Kim, Myung-woon Hwang, Sangwoo Han
This paper presents a fully integrated low-power direct-conversion transmitter for cellular/PCS/WCDMA applications. Low-power consumption is achieved with the architecture of a simplified local-oscillator network, though the harmonics of large output signal could cause interference to the VCO. This inherent problem is effectively alleviated with a wide bandwidth fractional-N frequency synthesizer and an enhanced harmonic rejection technique. The transmitter, which consists of signal-processing blocks and a Sigma-Delta fractional-N frequency synthesizer with an integrated VCO, is fabricated using a 0.35 mum SiGe BiCMOS process. The total current consumption at minimum power is only 23 mA for the cellular and 27 mA for the PCS/WCDMA; the error vector magnitude is 3.91%, 6.98% and 8.56%, respectively.
本文介绍了一种用于蜂窝/PCS/WCDMA应用的全集成低功耗直接转换发射机。采用简化的本振网络结构实现了低功耗，但大输出信号的谐波可能会对压控振荡器造成干扰。宽频带分数n频率合成器和增强的谐波抑制技术有效地缓解了这一固有问题。该发射机由信号处理模块和带集成VCO的Sigma-Delta分数n频率合成器组成，采用0.35 μ g SiGe BiCMOS工艺制造。在最小功率下，蜂窝的总电流消耗仅为23ma, PCS/WCDMA为27ma;误差向量大小分别为3.91%、6.98%和8.56%。
{"title":"A Low-Power Cellular/PCS/WCDMA Direct-Conversion Transmitter with Enhanced VCO Remodulation Rejection","authors":"Sungho Beck, Jeong-Cheol Lee, S. Yoo, Kyoohyun Lim, H. Jung, Jaekyung Han, Munkyung Ahn, Tschang-Hi Lee, Kyung-Lok Kim, Myung-woon Hwang, Sangwoo Han","doi":"10.1109/ASSCC.2006.357857","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357857","url":null,"abstract":"This paper presents a fully integrated low-power direct-conversion transmitter for cellular/PCS/WCDMA applications. Low-power consumption is achieved with the architecture of a simplified local-oscillator network, though the harmonics of large output signal could cause interference to the VCO. This inherent problem is effectively alleviated with a wide bandwidth fractional-N frequency synthesizer and an enhanced harmonic rejection technique. The transmitter, which consists of signal-processing blocks and a Sigma-Delta fractional-N frequency synthesizer with an integrated VCO, is fabricated using a 0.35 mum SiGe BiCMOS process. The total current consumption at minimum power is only 23 mA for the cellular and 27 mA for the PCS/WCDMA; the error vector magnitude is 3.91%, 6.98% and 8.56%, respectively.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124763096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357918
Yun-Sang Lee, Jung-Bae Lee, Changhyun Kim, S. Cha, H. Yoon
An efficient self post package repair algorithm using on-chip-ECC is proposed and the circuit implementation details are presented. The proposed algorithm identifies and stores the addresses of hard fault detected by on-chip-ECC during post package test phase and performs subsequent repairs with changing supply voltage level controlled by tester. A yield improvement by 1~1.5% is expected and the efficiency of test and repair steps is enhanced by about 58~67%. The chip size overhead for its implementation is estimated to be under 0.4% for an 80 nm 1 Gb memory.
{"title":"An Efficient Self Post Package Repair Algorithm and Implementation in Memory System with on-chip-EGG","authors":"Yun-Sang Lee, Jung-Bae Lee, Changhyun Kim, S. Cha, H. Yoon","doi":"10.1109/ASSCC.2006.357918","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357918","url":null,"abstract":"An efficient self post package repair algorithm using on-chip-ECC is proposed and the circuit implementation details are presented. The proposed algorithm identifies and stores the addresses of hard fault detected by on-chip-ECC during post package test phase and performs subsequent repairs with changing supply voltage level controlled by tester. A yield improvement by 1~1.5% is expected and the efficiency of test and repair steps is enhanced by about 58~67%. The chip size overhead for its implementation is estimated to be under 0.4% for an 80 nm 1 Gb memory.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125583014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357858
Ying Wang, Kangmin Hu, Guojing Ye, Xiaofeng Yi, Jirou He, Xiaoping Gao, Jingguang Wang, Juan Li, Ye Zhou, Jiayi Liang, Yumei Huang, Zhiliang Hong
A 2.4 G single-chip radio-frequency (RF) transceiver front-end for IEEE 802.11b is integrated in 0.18 mum CMOS technology. The direct conversion architecture is adopted for both transmitter & receiver to minimize the on-chip and off-chip components required, which ensures low cost and low power consumption. The VCO oscillates at two times the carrier frequency to minimize PA pulling effect, which also facilitates the generation of quadrature LOs by using a divide-by-two circuit. It is also promising that further integration of multi-mode transceiver can be facilitated because this architecture maximizes reuse of building blocks in transmitter, receiver and PLL. Primary test results show that the transmit peak error vector magnitude (peak EVM) is less than 16% (rms value about 8.6%) with the spectrum mask requirements met and show that at 4.4 GHz, PLL phase noise is about -119 dBc/Hz at 3 MHz offset.
采用0.18 μ m CMOS技术集成了用于IEEE 802.11b的2.4 G单芯片射频(RF)收发器前端。发射器和接收器均采用直接转换架构，最大限度地减少所需的片内和片外组件，确保低成本和低功耗。压控振荡器以两倍载波频率振荡，以最大限度地减少PA牵引效应，这也有助于通过使用除以二电路产生正交LOs。由于这种架构可以最大限度地重用发射器、接收器和锁相环中的构建块，因此可以促进多模收发器的进一步集成。初步测试结果表明，在满足频谱掩模要求的情况下，发射峰值误差矢量幅度(峰值EVM)小于16%(有效值约为8.6%)，在4.4 GHz时，锁相环在3mhz偏移时的相位噪声约为-119 dBc/Hz。
{"title":"A Single-Chip CMOS Transceiver for IEEE 802.11b Wireless LAN","authors":"Ying Wang, Kangmin Hu, Guojing Ye, Xiaofeng Yi, Jirou He, Xiaoping Gao, Jingguang Wang, Juan Li, Ye Zhou, Jiayi Liang, Yumei Huang, Zhiliang Hong","doi":"10.1109/ASSCC.2006.357858","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357858","url":null,"abstract":"A 2.4 G single-chip radio-frequency (RF) transceiver front-end for IEEE 802.11b is integrated in 0.18 mum CMOS technology. The direct conversion architecture is adopted for both transmitter & receiver to minimize the on-chip and off-chip components required, which ensures low cost and low power consumption. The VCO oscillates at two times the carrier frequency to minimize PA pulling effect, which also facilitates the generation of quadrature LOs by using a divide-by-two circuit. It is also promising that further integration of multi-mode transceiver can be facilitated because this architecture maximizes reuse of building blocks in transmitter, receiver and PLL. Primary test results show that the transmit peak error vector magnitude (peak EVM) is less than 16% (rms value about 8.6%) with the spectrum mask requirements met and show that at 4.4 GHz, PLL phase noise is about -119 dBc/Hz at 3 MHz offset.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127723142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357934
C. Kromer, G. Sialm, D. Erni, H. Jackel, T. Morf, M. Kossel
An optical receiver for short-range optical data communication up to 40 Gb/s is presented. The optimum number of limiting amplifier (LA) stages is calculated to achieve a large gain-bandwidth product. The receiver features an electrical transimpedance gain of 91.4 dBOmega and a bandwidth of 19.2 GHz. For the free-space optical measurements (lambda=1550nm) an InGaAs/lnP photo diode (PD) and the CMOS receiver chip were placed and bonded on a test substrate. At 40 Gb/s an open eye at the output of the receiver is shown at an optical input power of -4.6 dBni. Including the transmitter non-idealities, sensitivities at 20 Gb/s and 30 Gb/s of-8.2 dBni and -7.5 dBm, respectively, at a BER = 10-12 were measured. The complete receiver consumes 56 mW from a 1.1-V supply and occupies a chip area of 230 mum x 220 mum only.
{"title":"A 40 Gb/s Optical Receiver in 80-nm CMOS for Short-Distance High-Density Interconnects","authors":"C. Kromer, G. Sialm, D. Erni, H. Jackel, T. Morf, M. Kossel","doi":"10.1109/ASSCC.2006.357934","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357934","url":null,"abstract":"An optical receiver for short-range optical data communication up to 40 Gb/s is presented. The optimum number of limiting amplifier (LA) stages is calculated to achieve a large gain-bandwidth product. The receiver features an electrical transimpedance gain of 91.4 dBOmega and a bandwidth of 19.2 GHz. For the free-space optical measurements (lambda=1550nm) an InGaAs/lnP photo diode (PD) and the CMOS receiver chip were placed and bonded on a test substrate. At 40 Gb/s an open eye at the output of the receiver is shown at an optical input power of -4.6 dBni. Including the transmitter non-idealities, sensitivities at 20 Gb/s and 30 Gb/s of-8.2 dBni and -7.5 dBm, respectively, at a BER = 10-12 were measured. The complete receiver consumes 56 mW from a 1.1-V supply and occupies a chip area of 230 mum x 220 mum only.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120968346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357900
Youchun Liao, Zhangwen Tang, Hao Min
In this paper, a wide-band CMOS low-noise amplifier (LNA) is presented, in which the thermal noise of the input MOSFET is canceled exploiting a noise-canceling technique. The LNA is designed under input/output impedance matching condition. And its noise figure (NF) and linearity analysis are investigated particularly. The LNA chip is implemented in a 0.25-mum 1P5M RF CMOS process. Measurement results show that in 50-860 MHz, the gain is about 13.4 dB, the NF is from 2.4 dB to 3.5 dB, and the input-referred third-order intercept point (IIP3) is 3.3 dBm. The chip consumes 30 mW at 2.5-V power supply and the core size is only 0.15 mm times 0.18 mm.
本文设计了一种宽带CMOS低噪声放大器(LNA)，该放大器利用消噪技术消除了输入MOSFET的热噪声。在输入/输出阻抗匹配条件下设计LNA。并对其噪声系数(NF)和线性度分析进行了详细的研究。LNA芯片采用0.25 μ m 1P5M RF CMOS工艺实现。测量结果表明，在50 ~ 860mhz频段，增益约为13.4 dB, NF范围为2.4 ~ 3.5 dB，输入参考三阶截距(IIP3)为3.3 dBm。该芯片在2.5 v电源下功耗为30mw，核心尺寸仅为0.15 mm × 0.18 mm。
{"title":"A Wide-band CMOS Low-Noise Amplifier for TV Tuner Applications","authors":"Youchun Liao, Zhangwen Tang, Hao Min","doi":"10.1109/ASSCC.2006.357900","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357900","url":null,"abstract":"In this paper, a wide-band CMOS low-noise amplifier (LNA) is presented, in which the thermal noise of the input MOSFET is canceled exploiting a noise-canceling technique. The LNA is designed under input/output impedance matching condition. And its noise figure (NF) and linearity analysis are investigated particularly. The LNA chip is implemented in a 0.25-mum 1P5M RF CMOS process. Measurement results show that in 50-860 MHz, the gain is about 13.4 dB, the NF is from 2.4 dB to 3.5 dB, and the input-referred third-order intercept point (IIP3) is 3.3 dBm. The chip consumes 30 mW at 2.5-V power supply and the core size is only 0.15 mm times 0.18 mm.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"622 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122694422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357840
S. Tam, S. Rusu, J. Chang, S. Vora, B. Cherkauer, D. Ayers
This paper describes a 95 W dual-core 64-bit Xeonreg MP processor implemented in a 65 nm 8 metal layer process. Each processor core has a unified 1MB L2 cache and supports the Intelreg Extended Memory 64 Technology and the Hyper-Threading Technology. The shared L3 cache has extensive RAS features including the Intelreg Cache Safe Technology and Error Correction Codes (ECC). The processor is designed and optimized to operate at a 95W thermal design power envelope at the target product frequency. The front-side bus operates at 667 MT/s or 800 MT/s in a 3 load topology that is compatible with existing platforms.
{"title":"A 65nm 95W Dual-Core Multi-Threaded Xeon® Processor with L3 Cache","authors":"S. Tam, S. Rusu, J. Chang, S. Vora, B. Cherkauer, D. Ayers","doi":"10.1109/ASSCC.2006.357840","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357840","url":null,"abstract":"This paper describes a 95 W dual-core 64-bit Xeonreg MP processor implemented in a 65 nm 8 metal layer process. Each processor core has a unified 1MB L2 cache and supports the Intelreg Extended Memory 64 Technology and the Hyper-Threading Technology. The shared L3 cache has extensive RAS features including the Intelreg Cache Safe Technology and Error Correction Codes (ECC). The processor is designed and optimized to operate at a 95W thermal design power envelope at the target product frequency. The front-side bus operates at 667 MT/s or 800 MT/s in a 3 load topology that is compatible with existing platforms.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115551012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357928
L. Joet, A. Dezzani, F. Montaudon, F. Badets, Florent Sibille, Christian Corre, L. Chabert, R. Mina, F. Bailleuil, D. Saias, F. Paillardet, E. Perea
A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm2 core area, achieves -108-dBm sensitivity, and -16-dBm IIP3. It is based on a discrete-time approach centering the baseband signal at half the sampling frequency. The receiver integrates Low-Noise Amplifier, filters and two 40-MHz sigma delta Analog to Digital Converters achieving a 12-bit resolution in 100 kHz.
{"title":"Advanced `Fs/2' Discrete-Time GSM Receiver in 90-nm CMOS","authors":"L. Joet, A. Dezzani, F. Montaudon, F. Badets, Florent Sibille, Christian Corre, L. Chabert, R. Mina, F. Bailleuil, D. Saias, F. Paillardet, E. Perea","doi":"10.1109/ASSCC.2006.357928","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357928","url":null,"abstract":"A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm2 core area, achieves -108-dBm sensitivity, and -16-dBm IIP3. It is based on a discrete-time approach centering the baseband signal at half the sampling frequency. The receiver integrates Low-Noise Amplifier, filters and two 40-MHz sigma delta Analog to Digital Converters achieving a 12-bit resolution in 100 kHz.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115773239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357911
H. Tanizaki, T. Tsuji, J. Otani, Y. Yamaguchi, Y. Murai, H. Furuta, S. Ueno, T. Oishi, M. Hayashikoshi, H. Hidaka
A high-density and high-speed memory cell named 1-transistor 4-magnetic tunnel junction (1T-4MTJ) has been proposed for magnetic random access memory (MRAM). The new 1T-4MTJ cell has been successfully demonstrated by a 1 Mb MRAM test device, using a 130 nm CMOS process. The sensing scheme of a self-reference sense amplifier with Voltage offset (SRSV) enables high-speed memory operation (access time) of tAC=56 nsec and 50 MHz@4cycle.
{"title":"A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme","authors":"H. Tanizaki, T. Tsuji, J. Otani, Y. Yamaguchi, Y. Murai, H. Furuta, S. Ueno, T. Oishi, M. Hayashikoshi, H. Hidaka","doi":"10.1109/ASSCC.2006.357911","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357911","url":null,"abstract":"A high-density and high-speed memory cell named 1-transistor 4-magnetic tunnel junction (1T-4MTJ) has been proposed for magnetic random access memory (MRAM). The new 1T-4MTJ cell has been successfully demonstrated by a 1 Mb MRAM test device, using a 130 nm CMOS process. The sensing scheme of a self-reference sense amplifier with Voltage offset (SRSV) enables high-speed memory operation (access time) of tAC=56 nsec and 50 MHz@4cycle.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115985384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357891
Jia Zhao, Xiaoyang Zeng, Jun Han, Jun Chen
This paper proposes a very low-cost VLSI implementation of AES algorithm. This design splits the 128 bit computation in every round into four 32 bit calculations and exploits 2-level pipeline to finish the process. Moreover, such improvements as module reuse and calculation order optimization, especially low-cost key expansion structure, are used to achieve high performance with very low hardware cost. Using the HHNEC 0.25 mum CMOS process, the scale of the design is about 12 K equivalent gates and its system frequency is up to 100 MHz. The throughputs of the 128 bit data encryption and decryption are as high as 256 Mbit/s.
本文提出了一种低成本的AES算法的VLSI实现方案。本设计将每轮128位的计算拆分为4个32位的计算，利用2级流水线来完成整个过程。此外，采用模块重用和计算顺序优化等改进，特别是采用低成本的键扩展结构，以极低的硬件成本实现高性能。采用HHNEC 0.25 μ m CMOS工艺，设计规模约为12k等效门，系统频率高达100mhz。128位数据加解密吞吐量高达256mbit /s。
{"title":"Very Low-cost VLSI Implementation of AES Algorithm","authors":"Jia Zhao, Xiaoyang Zeng, Jun Han, Jun Chen","doi":"10.1109/ASSCC.2006.357891","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357891","url":null,"abstract":"This paper proposes a very low-cost VLSI implementation of AES algorithm. This design splits the 128 bit computation in every round into four 32 bit calculations and exploits 2-level pipeline to finish the process. Moreover, such improvements as module reuse and calculation order optimization, especially low-cost key expansion structure, are used to achieve high performance with very low hardware cost. Using the HHNEC 0.25 mum CMOS process, the scale of the design is about 12 K equivalent gates and its system frequency is up to 100 MHz. The throughputs of the 128 bit data encryption and decryption are as high as 256 Mbit/s.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116847833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357842
D. Kwai
This paper presents a compilable SRAM augmented with a sleep mode to achieve low standby power. Sleep transistor and source line self bias are added to the array, and their layouts fit to the repetitive cell placement. The area overhead is minimized in such a way that the footprint remains the same. A 0.18 mum 512 Kb test chip manufactured by two different foundries is used to demonstrate its effectiveness. The standby current measurements show substantial savings of 69% and 77%, respectively, at 1.8 V. The savings can be greater if the supply voltage is lowered. This encourages sleeping at low voltage. Design choices to vary the virtual ground voltage to attain further reduction are investigated. The tradeoff is with the data retention voltage which is measured at least 0.1 V higher. The fact that the cell stability is undermined in the sleep mode is the main concern to operate the SRAM at low voltage.
本文提出了一种可编译的SRAM，增强了休眠模式，以实现低待机功耗。休眠晶体管和源线自偏置被添加到阵列中，它们的布局适合重复单元放置。面积开销被最小化，从而使占用空间保持不变。由两家不同的代工厂生产的0.18 μ m 512 Kb测试芯片验证了其有效性。待机电流测量结果显示，在1.8 V时可分别节省69%和77%的电流。如果电源电压降低，节省的电能会更大。这有助于在低电压下睡觉。研究了改变虚地电压以达到进一步降低的设计选择。权衡的是数据保持电压，其测量值至少高出0.1 V。电池稳定性在睡眠模式下被破坏的事实是在低电压下操作SRAM的主要问题。
{"title":"Standby Current Reduction of Compilable SRAM Using Sleep Transistor and Source Line Self Bias","authors":"D. Kwai","doi":"10.1109/ASSCC.2006.357842","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357842","url":null,"abstract":"This paper presents a compilable SRAM augmented with a sleep mode to achieve low standby power. Sleep transistor and source line self bias are added to the array, and their layouts fit to the repetitive cell placement. The area overhead is minimized in such a way that the footprint remains the same. A 0.18 mum 512 Kb test chip manufactured by two different foundries is used to demonstrate its effectiveness. The standby current measurements show substantial savings of 69% and 77%, respectively, at 1.8 V. The savings can be greater if the supply voltage is lowered. This encourages sleeping at low voltage. Design choices to vary the virtual ground voltage to attain further reduction are investigated. The tradeoff is with the data retention voltage which is measured at least 0.1 V higher. The fact that the cell stability is undermined in the sleep mode is the main concern to operate the SRAM at low voltage.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129457745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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