Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357944
Chen-Ming Hsu, Chien-Ming Lee, Tzong-Chee Yo, C. Luo
The exclusive biotelemetry system for implantable measurement utilizing a low-power BPSK transmitter, RF terminal chip for signal up-conversion and receiver is presented. The frequency band used in the human body is the un-licensed band at 402-405 MHz allocated to medical implant communication systems (MICS) by FCC and the ISM band at 2.4GHz is used for transmission in the air. This system has following characteristics: 40 channels with 75k bandwidth, low output power in transmitter and easily be full-integrated that are suitable for implantable applications. The low noise amplifier (LNA) with current reuse technique and cascode structure for high gain and low noise figure is implemented in this paper. The chip is designed and fabricated in TSMC 0.18 mum 1P6M CMOS technology.
介绍了一种独特的植入式测量生物遥测系统，该系统利用低功耗BPSK发射机、用于信号上转换的射频终端芯片和接收器。人体使用的频段是FCC分配给医疗植入通信系统(MICS)的未经许可的402-405 MHz频段，2.4GHz的ISM频段用于空中传输。该系统具有40个通道，带宽75k，发射机输出功率低，易于集成，适合植入式应用。采用电流复用技术和级联码结构实现了高增益、低噪声系数的低噪声放大器。该芯片采用台积电0.18 μ m 1P6M CMOS工艺设计制造。
{"title":"The low power MICS band biotelemetry architecture and its LNA design for implantable applications","authors":"Chen-Ming Hsu, Chien-Ming Lee, Tzong-Chee Yo, C. Luo","doi":"10.1109/ASSCC.2006.357944","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357944","url":null,"abstract":"The exclusive biotelemetry system for implantable measurement utilizing a low-power BPSK transmitter, RF terminal chip for signal up-conversion and receiver is presented. The frequency band used in the human body is the un-licensed band at 402-405 MHz allocated to medical implant communication systems (MICS) by FCC and the ISM band at 2.4GHz is used for transmission in the air. This system has following characteristics: 40 channels with 75k bandwidth, low output power in transmitter and easily be full-integrated that are suitable for implantable applications. The low noise amplifier (LNA) with current reuse technique and cascode structure for high gain and low noise figure is implemented in this paper. The chip is designed and fabricated in TSMC 0.18 mum 1P6M CMOS technology.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127011070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To explore the possibility of soft IP implementation, a fully digital smart temperature sensor without any full-custom device is proposed for painless VLSI or SOC on-chip integrations. The signal is processed thoroughly in time domain instead of conventional voltage or current domain. A cyclic delay line is used to generate the thermally sensitive pulse with a width proportional to the measured temperature. The timing reference is just the input clock, and a counter instead of voltage or current analog-to-digital converter is utilized for digital output coding. The circuit is realized by FPGA chips for functionality verification and performance evaluation. Implemented with as few as 140 Logic Elements, the proposed smart sensor was measured to have an error of -0.7degC~0.9degC over a wide temperature range of -40degC~130degC. The effective resolution is better than 0.1degC, and the power consumption is 8.42 muW at a sample rate of 2 samples/s. The performance is as good as those of most full-custom predecessors. The longest conversion time is around 260 mus, and a conversion rate of 3 kHz at least is promised.
{"title":"A Fully Digital Low Cost Time Domain Smart Temperature Sensor with Extremely Tiny Size","authors":"Poki Chen, Mon-Chau Shie, Zi-Fan Zheng, C. Chu, Mao-Hsing Chiang, Zhi-Yuan Zheng","doi":"10.1109/ASSCC.2006.357873","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357873","url":null,"abstract":"To explore the possibility of soft IP implementation, a fully digital smart temperature sensor without any full-custom device is proposed for painless VLSI or SOC on-chip integrations. The signal is processed thoroughly in time domain instead of conventional voltage or current domain. A cyclic delay line is used to generate the thermally sensitive pulse with a width proportional to the measured temperature. The timing reference is just the input clock, and a counter instead of voltage or current analog-to-digital converter is utilized for digital output coding. The circuit is realized by FPGA chips for functionality verification and performance evaluation. Implemented with as few as 140 Logic Elements, the proposed smart sensor was measured to have an error of -0.7degC~0.9degC over a wide temperature range of -40degC~130degC. The effective resolution is better than 0.1degC, and the power consumption is 8.42 muW at a sample rate of 2 samples/s. The performance is as good as those of most full-custom predecessors. The longest conversion time is around 260 mus, and a conversion rate of 3 kHz at least is promised.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121551167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357901
B. Perumana, J. Zhan, S. S. Taylor, J. Laskar
This paper presents a resistive feedback broadband LNA in 90 nm CMOS which occupies 50 mum times 270 mum of active area. The LNA has 7 GHz 3 dB bandwidth and >24 dB voltage gain. Across 0.5-6 GHz, its input matching is better than -10 dB, noise figure below 2.5 dB, and iIP3 better than -8 dBm. Techniques to improve linearity in resistive feedback LNAs are discussed in detail. The LNA also provides an additional low power mode operation.
{"title":"A 0.5-6 GHz Improved Linearity, Resistive Feedback 90-nm CMOS LNA","authors":"B. Perumana, J. Zhan, S. S. Taylor, J. Laskar","doi":"10.1109/ASSCC.2006.357901","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357901","url":null,"abstract":"This paper presents a resistive feedback broadband LNA in 90 nm CMOS which occupies 50 mum times 270 mum of active area. The LNA has 7 GHz 3 dB bandwidth and >24 dB voltage gain. Across 0.5-6 GHz, its input matching is better than -10 dB, noise figure below 2.5 dB, and iIP3 better than -8 dBm. Techniques to improve linearity in resistive feedback LNAs are discussed in detail. The LNA also provides an additional low power mode operation.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130507305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357926
T. Ito, D. Kawazoe, K. Okada, K. Masu
This paper proposes a novel small-area distributed amplifler (DA), which utilizes two 5-port inductors to replace eight inductors. The DA is fabricated using a standard 180 nm CMOS process with 6 metal layers. The layout area of DA is 0.33 mm2. It is about 50 % as large as conventional DAs, and it has power gain of 6.3 dB and noise figure of 6 dB at DC-7 GHz.
{"title":"A DC-7 GHz Small-Area Distributed Amplifier Using 5-port Inductors in a 180nm Si CMOS Technology","authors":"T. Ito, D. Kawazoe, K. Okada, K. Masu","doi":"10.1109/ASSCC.2006.357926","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357926","url":null,"abstract":"This paper proposes a novel small-area distributed amplifler (DA), which utilizes two 5-port inductors to replace eight inductors. The DA is fabricated using a standard 180 nm CMOS process with 6 metal layers. The layout area of DA is 0.33 mm2. It is about 50 % as large as conventional DAs, and it has power gain of 6.3 dB and noise figure of 6 dB at DC-7 GHz.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124683454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357897
B. Moon, D. Jung, J. Chung, C. Joung, J. Hong, S. Lee, Y. Shin, C. Yoo
A full-digital 12-channel, 100-step capacitive sensor is described. The capacitance to be sensed forms an RC-delay line whose delay is compared with that of a reference RC-delay line. The difference of the RC delays is sensed by a simple full-digital time-to-digital converter (TDC). By compensating the parasitic capacitance at power up, the capacitive sensor implemented in a 0.35 mum standard digital CMOS technology shows 30fF sensing resolution. The capacitive sensor consumes 5 muA per channel under 3.3V supply voltage.
{"title":"A Full-Digital Multi-Channel CMOS Capacitive Sensor","authors":"B. Moon, D. Jung, J. Chung, C. Joung, J. Hong, S. Lee, Y. Shin, C. Yoo","doi":"10.1109/ASSCC.2006.357897","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357897","url":null,"abstract":"A full-digital 12-channel, 100-step capacitive sensor is described. The capacitance to be sensed forms an RC-delay line whose delay is compared with that of a reference RC-delay line. The difference of the RC delays is sensed by a simple full-digital time-to-digital converter (TDC). By compensating the parasitic capacitance at power up, the capacitive sensor implemented in a 0.35 mum standard digital CMOS technology shows 30fF sensing resolution. The capacitive sensor consumes 5 muA per channel under 3.3V supply voltage.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121136590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357904
M.A. Khan, N. Miyamoto, R. Pantonial, K. Kotani, S. Sugawa, T. Ohmi
To implement a user circuit on a Dynamically Reconflgurable FPGA (DRFPGA) the circuit needs to be temporally partitioned into several sub-circuits such that their sequential execution on the DRFPGA yields the same result as that of the user circuit. In devices where interconnect delay is far dominating than logic delay, such implementation has the prospect of executing user circuits faster than traditional FPGA implementation, since temporal partitioning divides a long spatial wire of a circuit into several short temporal wires, thus converting interconnect delay into logic delay. To realize such prospect, reconfiguration delay and temporal communication delay of a DRFPGA must be kept as low as possible. This paper studies these issues and reports the architecture and performance of Flexible Processor III (FP3), a newly proposed DRFPGA. FP3 employs a new shift register type temporal interconnect and Nearest Neighbor (NN) type spatial interconnect to reduce the delay mentioned above. Correct behavior of FP3, designed and fabricated in 0.35 um CMOS technology, has been confirmed and our experimental results show that there exist cases where the best user circuit speed is achieved when two or more contexts are in use.
为了在动态可重构FPGA (DRFPGA)上实现用户电路，需要将电路暂时划分为几个子电路，以便它们在DRFPGA上的顺序执行产生与用户电路相同的结果。在互连延迟远比逻辑延迟占主导地位的设备中，这种实现有望比传统的FPGA实现更快地执行用户电路，因为时间划分将电路的长空间线划分为几个短时间线，从而将互连延迟转换为逻辑延迟。为了实现这一前景，DRFPGA的重构延迟和瞬时通信延迟必须尽可能低。本文对这些问题进行了研究，并报道了柔性处理器III (FP3)的结构和性能。FP3采用一种新的移位寄存器型时间互连和最近邻(NN)型空间互连来减少上述延迟。采用0.35 um CMOS技术设计和制造的FP3的正确行为已经得到证实，我们的实验结果表明，当使用两种或多种环境时，存在最佳用户电路速度的情况。
{"title":"Improving Multi-Context Execution Speed on DRFPGAs","authors":"M.A. Khan, N. Miyamoto, R. Pantonial, K. Kotani, S. Sugawa, T. Ohmi","doi":"10.1109/ASSCC.2006.357904","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357904","url":null,"abstract":"To implement a user circuit on a Dynamically Reconflgurable FPGA (DRFPGA) the circuit needs to be temporally partitioned into several sub-circuits such that their sequential execution on the DRFPGA yields the same result as that of the user circuit. In devices where interconnect delay is far dominating than logic delay, such implementation has the prospect of executing user circuits faster than traditional FPGA implementation, since temporal partitioning divides a long spatial wire of a circuit into several short temporal wires, thus converting interconnect delay into logic delay. To realize such prospect, reconfiguration delay and temporal communication delay of a DRFPGA must be kept as low as possible. This paper studies these issues and reports the architecture and performance of Flexible Processor III (FP3), a newly proposed DRFPGA. FP3 employs a new shift register type temporal interconnect and Nearest Neighbor (NN) type spatial interconnect to reduce the delay mentioned above. Correct behavior of FP3, designed and fabricated in 0.35 um CMOS technology, has been confirmed and our experimental results show that there exist cases where the best user circuit speed is achieved when two or more contexts are in use.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128289278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357905
H. Nakaya, Y. Sasaki, N. Kato, F. Arakawa, T. Shimizu
We describe an alternative cyclic synchronous mirror delay (ACSMD) for highly integrated SoCs of mobile application processors. ACSMD provides the following advantages: wide operational frequency range from 0.5 to 400 MHz, 0.08 mm2 chip area, and 6.13 mW power consumption @ 400 MHz operation. The chip area and power consumption are reduced by 95% of those of a conventional hierarchical SMD with the same operational frequency and resolution. Key circuit technologies are cyclic delay line, alternating use of three delay lines, and a new loop counter.
{"title":"An Alternative Cyclic Synchronous Mirror Delay for Versatility in Highly Integrated SoC","authors":"H. Nakaya, Y. Sasaki, N. Kato, F. Arakawa, T. Shimizu","doi":"10.1109/ASSCC.2006.357905","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357905","url":null,"abstract":"We describe an alternative cyclic synchronous mirror delay (ACSMD) for highly integrated SoCs of mobile application processors. ACSMD provides the following advantages: wide operational frequency range from 0.5 to 400 MHz, 0.08 mm2 chip area, and 6.13 mW power consumption @ 400 MHz operation. The chip area and power consumption are reduced by 95% of those of a conventional hierarchical SMD with the same operational frequency and resolution. Key circuit technologies are cyclic delay line, alternating use of three delay lines, and a new loop counter.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"37 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132737682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357853
H. Fujisawa, M. Saito, S. Nishijima, N. Odate, Y. Sakai, K. Yoda, I. Sugiyama, T. Ishihara, Y. Hirose, H. Yoshizawa
Software defined radio (SDR) is expected to be a progressive technology for wireless communications under multi-communication systems. SDR requires high performance, low power consumption, and short latency hardware. We have developed a single-chip baseband processing LSI for SDR based on a hybrid architecture of coarse-grain reconfigurable logic cores and flexible accelerator modules to achieve the required features. The maximum performance is 103 GOPS. Moreover, we implemented IEEE 802.11a and IEEE 802.11b, and show the effectiveness in latency.
{"title":"Flexible Signal Processing Platform Chip for Software Defined Radio with 103 GOPS Dynamic Reconf1gurable Logic Cores","authors":"H. Fujisawa, M. Saito, S. Nishijima, N. Odate, Y. Sakai, K. Yoda, I. Sugiyama, T. Ishihara, Y. Hirose, H. Yoshizawa","doi":"10.1109/ASSCC.2006.357853","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357853","url":null,"abstract":"Software defined radio (SDR) is expected to be a progressive technology for wireless communications under multi-communication systems. SDR requires high performance, low power consumption, and short latency hardware. We have developed a single-chip baseband processing LSI for SDR based on a hybrid architecture of coarse-grain reconfigurable logic cores and flexible accelerator modules to achieve the required features. The maximum performance is 103 GOPS. Moreover, we implemented IEEE 802.11a and IEEE 802.11b, and show the effectiveness in latency.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134254716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357908
I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen, A. Wu
As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the injected noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. In this paper, we design and implement an 8-bit Markov random field carry lookahead adder (MRFCLA) probabilistic-based noise-tolerant circuit in 0.18μm CMOS process technology. This is the first working silicon design to prove the design concept of the noise-tolerant MRF circuits. The measurement results show that the proposed of the MRF adder can provide 28.7dB of noise-immunity as compared with its conventional CMOS design, when both circuits are facing the same server SNR environment. The MRF adder circuit can also achieve 10-6 BER when the supply voltage is only 0.45 V and SNR is only 10 dB.
{"title":"A 0.18=μm Probabilistic-Based Noise-Tolerate Circuit Design and Implementation with 28.7dB Noise-Immunity Improvement","authors":"I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen, A. Wu","doi":"10.1109/ASSCC.2006.357908","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357908","url":null,"abstract":"As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the injected noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. In this paper, we design and implement an 8-bit Markov random field carry lookahead adder (MRFCLA) probabilistic-based noise-tolerant circuit in 0.18μm CMOS process technology. This is the first working silicon design to prove the design concept of the noise-tolerant MRF circuits. The measurement results show that the proposed of the MRF adder can provide 28.7dB of noise-immunity as compared with its conventional CMOS design, when both circuits are facing the same server SNR environment. The MRF adder circuit can also achieve 10-6 BER when the supply voltage is only 0.45 V and SNR is only 10 dB.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"19 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113955298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357895
T. Kazama, T. Nakura, M. Ikeda, K. Asada
This paper demonstrates optimization of a feedforward active substrate noise canceling technique using a power supply di/dt detector. Our past study realized substrate noise canceling using a di/dt detector. For further substrate noise reduction, this study analyzes the parameters which constitute a di/dt canceller and develops the effective di/dt noise canceling scheme. As a result, we realized 62% substrate noise reduction. Compared with effect of guard ring, our multiple di/dt canceller suppressed about five times as much substrate noise as that of guard ring.
{"title":"Optimization of Active Substrate Noise Cancelling Technique using Power Line di/dt Detector","authors":"T. Kazama, T. Nakura, M. Ikeda, K. Asada","doi":"10.1109/ASSCC.2006.357895","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357895","url":null,"abstract":"This paper demonstrates optimization of a feedforward active substrate noise canceling technique using a power supply di/dt detector. Our past study realized substrate noise canceling using a di/dt detector. For further substrate noise reduction, this study analyzes the parameters which constitute a di/dt canceller and develops the effective di/dt noise canceling scheme. As a result, we realized 62% substrate noise reduction. Compared with effect of guard ring, our multiple di/dt canceller suppressed about five times as much substrate noise as that of guard ring.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"32 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114133846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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