Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357863
Jin Soo Kim, C. Hyun, M. Sunwoo
This paper presents efficient memory reuse and sub-pixel interpolation algorithms for ME (motion estimation)/MC (motion compensation) of H.264/AVC. ME is a computationally intensive task and its number of memory accesses is quite high. Moreover, sub-pixel interpolation requires many additions and multiplications. The proposed memory reuse algorithm utilizes the position similarity of the MVp (motion vector prediction) among neighboring Sub-MBs (macro blocks). It can reduce a large number of memory accesses and can save power consumption by sharing SR (search range) of the current block In addition, simplifying weights of sub-pixel interpolation can eliminate multiplications. Therefore, the proposed memory reuse and sub-pixel interpolation algorithms can be employed for low power video compression. In addition, the proposed ME accelerator uses the proposed algorithms. Performance comparisons show a significant improvement compared with existing ME accelerators.
{"title":"Efficient Motion Estimation Accelerator for H.264/AVC","authors":"Jin Soo Kim, C. Hyun, M. Sunwoo","doi":"10.1109/ASSCC.2006.357863","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357863","url":null,"abstract":"This paper presents efficient memory reuse and sub-pixel interpolation algorithms for ME (motion estimation)/MC (motion compensation) of H.264/AVC. ME is a computationally intensive task and its number of memory accesses is quite high. Moreover, sub-pixel interpolation requires many additions and multiplications. The proposed memory reuse algorithm utilizes the position similarity of the MVp (motion vector prediction) among neighboring Sub-MBs (macro blocks). It can reduce a large number of memory accesses and can save power consumption by sharing SR (search range) of the current block In addition, simplifying weights of sub-pixel interpolation can eliminate multiplications. Therefore, the proposed memory reuse and sub-pixel interpolation algorithms can be employed for low power video compression. In addition, the proposed ME accelerator uses the proposed algorithms. Performance comparisons show a significant improvement compared with existing ME accelerators.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"379 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121766511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Novel piezoresistive microsensors for automotive tire pressure monitoring system (TPMS) are designed, fabricated and tested. 30 mum thick silicon diaphragms (from 370 mum times 370 mum to 970 mum times 970 mum) are adopted, thicker than that of the conventional piezoresistive pressure sensor, which extends the high stress distribution in the bulk silicon. Novel meander shape piezoresistors are designed, parts of which are fabricated on the high stress bulk silicon to obtain high linearity and sensitivity. Different diaphragm areas, piezoresistive shapes and placing methods on the microsensor performances are simulated, measured and analyzed. The whole fabrication is low-cost and compatible with standard IC process, which tolerates large process variations. Good microsensor precision (0.23%/FS) is obtained. The whole work indicates a novel solution of small size, high performance and low cost piezoresistive microsensor for TPMS and many other applications.
{"title":"Design, Fabrication and Characterization of Novel Piezoresistive Pressure Microsensor for TPMS","authors":"Yanhong Zhang, Bingwu Liu, Litian Liu, Zhimin Tan, Zhaohua Zhang, Huiwang Lin, T. Ren","doi":"10.1109/ASSCC.2006.357946","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357946","url":null,"abstract":"Novel piezoresistive microsensors for automotive tire pressure monitoring system (TPMS) are designed, fabricated and tested. 30 mum thick silicon diaphragms (from 370 mum times 370 mum to 970 mum times 970 mum) are adopted, thicker than that of the conventional piezoresistive pressure sensor, which extends the high stress distribution in the bulk silicon. Novel meander shape piezoresistors are designed, parts of which are fabricated on the high stress bulk silicon to obtain high linearity and sensitivity. Different diaphragm areas, piezoresistive shapes and placing methods on the microsensor performances are simulated, measured and analyzed. The whole fabrication is low-cost and compatible with standard IC process, which tolerates large process variations. Good microsensor precision (0.23%/FS) is obtained. The whole work indicates a novel solution of small size, high performance and low cost piezoresistive microsensor for TPMS and many other applications.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125161758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357849
K. Leung, K. Leung, D. Holberg
A 0.35 mum double-poly CMOS 16 b SAR A/D converter uses self-calibration techniques to obtain frac12 LSB INL. The differential and single-ended THD at 1Msample/s are 101dB and 96 dB, respectively. Each ADC consumes 20 mW at 3 V and occupies 2.9 mm2 active area, resulting in a 0.9 pJ/b FOM. The chip includes 3 ADCs, 2 DACs, 8051-microcontroller, CAN controller, DMA controller, 64 K flash memory and 4 K RAM occupying 26 mm2.
一种0.35 μ m双聚CMOS 16b SAR A/D转换器采用自校准技术获得frac12lsb INL。差分THD和单端THD在1Msample/s下分别为101dB和96db。每个ADC在3v时消耗20 mW，占用2.9 mm2的有效面积，产生0.9 pJ/b的FOM。该芯片包括3个adc、2个dac、8051微控制器、CAN控制器、DMA控制器、64k闪存和4k内存，占用26mm2。
{"title":"A Dual Low Power 1/2 LSB NL 16b/1Msample/s SAR A/D Converter with on-chip Microcontroller","authors":"K. Leung, K. Leung, D. Holberg","doi":"10.1109/ASSCC.2006.357849","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357849","url":null,"abstract":"A 0.35 mum double-poly CMOS 16 b SAR A/D converter uses self-calibration techniques to obtain frac12 LSB INL. The differential and single-ended THD at 1Msample/s are 101dB and 96 dB, respectively. Each ADC consumes 20 mW at 3 V and occupies 2.9 mm2 active area, resulting in a 0.9 pJ/b FOM. The chip includes 3 ADCs, 2 DACs, 8051-microcontroller, CAN controller, DMA controller, 64 K flash memory and 4 K RAM occupying 26 mm2.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128208408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357929
Li Yin, Ting-Hua Yun, Jian-hui Wu, L. Shi
In this paper, a CMOS low-distortion variable gain amplifier with exponential gain control is developed by utilizing a transconductance linearization scheme. The VGA is composed of a VGA core based on current-steering structure, an exponential voltage generator based on transfer characteristics of differential pair, and a stage of fixed gain amplifier. The proposed VGA circuit was verified in 0.25 mum CMOS technology, the measurement results show a total gain control range of 40 dB, the 3-dB bandwidth is 100 MHz, and a -58.5dBc third-order inter-modulation distortion at differential output of 2 Vpp are obtained, the noise figure at maximum gain is 8.6 dB.
本文采用跨导线性化方法，设计了一种指数增益控制的CMOS低失真变增益放大器。该VGA由基于电流转向结构的VGA核、基于差分对传输特性的指数电压发生器和定增益放大器级组成。在0.25 μ m CMOS技术上对所提出的VGA电路进行了验证，测量结果表明，总增益控制范围为40 dB, 3-dB带宽为100 MHz，差分输出2 Vpp时三阶互调失真为-58.5dBc，最大增益时噪声系数为8.6 dB。
{"title":"A CMOS Low-Distortion Variable Gain Amplifier with Exponential Gain Control","authors":"Li Yin, Ting-Hua Yun, Jian-hui Wu, L. Shi","doi":"10.1109/ASSCC.2006.357929","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357929","url":null,"abstract":"In this paper, a CMOS low-distortion variable gain amplifier with exponential gain control is developed by utilizing a transconductance linearization scheme. The VGA is composed of a VGA core based on current-steering structure, an exponential voltage generator based on transfer characteristics of differential pair, and a stage of fixed gain amplifier. The proposed VGA circuit was verified in 0.25 mum CMOS technology, the measurement results show a total gain control range of 40 dB, the 3-dB bandwidth is 100 MHz, and a -58.5dBc third-order inter-modulation distortion at differential output of 2 Vpp are obtained, the noise figure at maximum gain is 8.6 dB.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131729788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357916
Won-Joo Yun, Hyun-Woo Lee, Young-Ju Kim, Won-Jun Choi, Sang-Hoon Shin, Hyang-Hwa Choi, Hyeng-Ouk Lee, Shin-Deok Kang, Hyong-Uk Moon, S. Kwack, Dong-Uk Lee, Jung-Woo Lee, Young-Kyoung Choi, N. Park, KiChang Kwean, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, J. Kih, Ye-Seok Yang
A new low power, low cost and high performance register-controlled digital delay locked loop with wide locking range is presented. The DLL has dual loops with single replica block, duty cycle correction enhance controller (DCCEC), smart power down controller (SPDC) for reducing the standby current during power down, and locking range doubler for wide locking range. The digital DLL used for 3 Gbps 512 Mb GDDR3 SDRAM is fabricated using an 80 nm DRAM Process. Experimental results show less than plusmn1% duty correction from external duty error of plusmn5%, less than 400 cycle locking time, 1.5 GHz operation frequency at 1.9 V, and a wide locking range from 50 MHz to 1.5 GHz.
{"title":"A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM","authors":"Won-Joo Yun, Hyun-Woo Lee, Young-Ju Kim, Won-Jun Choi, Sang-Hoon Shin, Hyang-Hwa Choi, Hyeng-Ouk Lee, Shin-Deok Kang, Hyong-Uk Moon, S. Kwack, Dong-Uk Lee, Jung-Woo Lee, Young-Kyoung Choi, N. Park, KiChang Kwean, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, J. Kih, Ye-Seok Yang","doi":"10.1109/ASSCC.2006.357916","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357916","url":null,"abstract":"A new low power, low cost and high performance register-controlled digital delay locked loop with wide locking range is presented. The DLL has dual loops with single replica block, duty cycle correction enhance controller (DCCEC), smart power down controller (SPDC) for reducing the standby current during power down, and locking range doubler for wide locking range. The digital DLL used for 3 Gbps 512 Mb GDDR3 SDRAM is fabricated using an 80 nm DRAM Process. Experimental results show less than plusmn1% duty correction from external duty error of plusmn5%, less than 400 cycle locking time, 1.5 GHz operation frequency at 1.9 V, and a wide locking range from 50 MHz to 1.5 GHz.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115649190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357882
Shon-Hang Wen, Juin-Wei Huang, Chao-Shiun Wang, Chomg-Kuang Wang
A 60GHz injection-locked frequency divider with power-matching technique is designed in 0.13-mum CMOS technology for wide locking range. Compared with shunt-peaking version, the power-matching technique utilized in injection-locked frequency divider improves locking range by 15% based on simulation results. The measurement results show the divider free-running frequency is 30.4 GHz and the total locking range is 6 GHz (10%) at the input power of 3 dBm while consuming 8.8mW from a 1.2 V power supply.
设计了一种采用功率匹配技术的60GHz注入锁定分频器，采用0.13 μ m CMOS技术实现了宽锁定范围。仿真结果表明，与并联调峰型分频器相比，采用功率匹配技术的注入锁定分频器的锁定范围提高了15%。测量结果表明，在输入功率为3 dBm时，分压器的自由工作频率为30.4 GHz，总锁定范围为6 GHz(10%)，功耗为8.8mW，电源为1.2 V。
{"title":"A 60GHz Wide Locking Range CMOS Frequency Divider using Power-Matching Technique","authors":"Shon-Hang Wen, Juin-Wei Huang, Chao-Shiun Wang, Chomg-Kuang Wang","doi":"10.1109/ASSCC.2006.357882","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357882","url":null,"abstract":"A 60GHz injection-locked frequency divider with power-matching technique is designed in 0.13-mum CMOS technology for wide locking range. Compared with shunt-peaking version, the power-matching technique utilized in injection-locked frequency divider improves locking range by 15% based on simulation results. The measurement results show the divider free-running frequency is 30.4 GHz and the total locking range is 6 GHz (10%) at the input power of 3 dBm while consuming 8.8mW from a 1.2 V power supply.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123340338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357933
Lidong Chen, F. Spagna, P. Marzolf, J.K. Wu
This paper describes the design of a receiver that supports the operation from 1 to 4.25-Gb/s, enabling a single macro to satisfy different protocols. The receiver performs equalization to compensate for interconnect ISI, achieves 10 mV sensitivity at 4.25-Gb/s by using offset corrected amplification, and performs clock-data-recovery with a digital algorithm that controls a recovered clock out of a phase interpolator. The receiver has been validated in 90 nm CMOS with 45 mW at 1.1 V supply voltage and demonstrated to achieve link over 30-meter AGW24 cable at 3.125 Gb/s with BER<10-5.
{"title":"A 90nm 1-4.25-Gb/s Multi Data Rate Receiver for High Speed Serial Links","authors":"Lidong Chen, F. Spagna, P. Marzolf, J.K. Wu","doi":"10.1109/ASSCC.2006.357933","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357933","url":null,"abstract":"This paper describes the design of a receiver that supports the operation from 1 to 4.25-Gb/s, enabling a single macro to satisfy different protocols. The receiver performs equalization to compensate for interconnect ISI, achieves 10 mV sensitivity at 4.25-Gb/s by using offset corrected amplification, and performs clock-data-recovery with a digital algorithm that controls a recovered clock out of a phase interpolator. The receiver has been validated in 90 nm CMOS with 45 mW at 1.1 V supply voltage and demonstrated to achieve link over 30-meter AGW24 cable at 3.125 Gb/s with BER<10-5.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122729016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357871
Qingyu Lin, Wei Miao, N. Wu
The paper proposes a high-speed target tracking CMOS image sensor. The target tracking CMOS image sensor consists of an image sensor array, row-parallel processors, a controller and a SRAM. It implements two novel concise algorithms that composed of efficient operations: such as collision detection, separation detection and position extraction. A 64 times 64 pixel array high-speed target tracking CMOS image sensor chip was implemented in using 0.35 mum 2P4M CMOS process. An N-well/P-sub SAB diode without salicide is used as photodiode in the image sensor. The chip size is 4.5 mm times 2.5 mm. The measured results demonstrated that the chip can perform target tracking at the rate of 1000 fps with more functionality and less area than the reported digital chips. The chip power consumption is 30 mW at the main clock of 20 MHz.
提出了一种高速目标跟踪CMOS图像传感器。目标跟踪CMOS图像传感器由图像传感器阵列、行并行处理器、控制器和SRAM组成。它实现了碰撞检测、分离检测和位置提取两种新颖简洁的算法。采用0.35 μ m 2P4M CMOS工艺，实现了64 × 64像素阵列高速目标跟踪CMOS图像传感器芯片。在图像传感器中，采用不含水杨酸的n阱/ p阱SAB二极管作为光电二极管。芯片尺寸为4.5 mm × 2.5 mm。测量结果表明，该芯片可以以1000 fps的速度进行目标跟踪，并且比现有的数字芯片具有更大的功能和更小的面积。芯片功耗为30mw，主频为20mhz。
{"title":"A High-Speed Target Tracking CMOS Image Sensor","authors":"Qingyu Lin, Wei Miao, N. Wu","doi":"10.1109/ASSCC.2006.357871","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357871","url":null,"abstract":"The paper proposes a high-speed target tracking CMOS image sensor. The target tracking CMOS image sensor consists of an image sensor array, row-parallel processors, a controller and a SRAM. It implements two novel concise algorithms that composed of efficient operations: such as collision detection, separation detection and position extraction. A 64 times 64 pixel array high-speed target tracking CMOS image sensor chip was implemented in using 0.35 mum 2P4M CMOS process. An N-well/P-sub SAB diode without salicide is used as photodiode in the image sensor. The chip size is 4.5 mm times 2.5 mm. The measured results demonstrated that the chip can perform target tracking at the rate of 1000 fps with more functionality and less area than the reported digital chips. The chip power consumption is 30 mW at the main clock of 20 MHz.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127244660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357870
Y. Egawa, H. Koike, R. Okamoto, H. Yamashita, N. Tanaka, J. Hosokawa, K. Arakawa, H. Ishida, H. Harakawa, T. Sakai, H. Goto
A 1/2.5 inch, 5.2 Mpeixel CMOS image sensor with wide dynamic range operation mode is developed and its effectiveness for high contrast scene pictures is verified. The adopted algorithm for this operation is inherently free from fixed pattern noise generation which often resists the realization of mass production level wide dynamic range image sensors. The attained dynamic range is 96 dB with 12 bit output scheme.
{"title":"A 1/2.5 inch 5.2Mpixel, 96dB Dynamic Range CMOS Image Sensor with Fixed Pattern Noise Free, Double Exposure Time Read-Out Operation","authors":"Y. Egawa, H. Koike, R. Okamoto, H. Yamashita, N. Tanaka, J. Hosokawa, K. Arakawa, H. Ishida, H. Harakawa, T. Sakai, H. Goto","doi":"10.1109/ASSCC.2006.357870","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357870","url":null,"abstract":"A 1/2.5 inch, 5.2 Mpeixel CMOS image sensor with wide dynamic range operation mode is developed and its effectiveness for high contrast scene pictures is verified. The adopted algorithm for this operation is inherently free from fixed pattern noise generation which often resists the realization of mass production level wide dynamic range image sensors. The attained dynamic range is 96 dB with 12 bit output scheme.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"23 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125842802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357864
Kuan-Hung Chen, Yu-Min Chen, Y. Chu, Jiun-In Guo
This paper presents a versatile multimedia functional unit (VMFU) which can compute six arithmetic operations, i.e. addition, subtraction, multiplication, MAC, interpolation, and SAD with different configurations. The VMFU is constructed on the basis of a row-based modified Booth encoding multiplier which consumes the lowest power among others according to our transistor-level simulations. Besides, we apply the spurious power suppression technique (SPST) to the proposed VMFU to decrease the wasted dynamic power dissipation. From the transistor-level simulations, the proposed VMFU dissipates 0.0142 mW/MHz under a 0.18 mum/1.8V CMOS technology. Adopting the SPST can reduce 24% power consumption with only a 15% area overhead.
{"title":"A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique","authors":"Kuan-Hung Chen, Yu-Min Chen, Y. Chu, Jiun-In Guo","doi":"10.1109/ASSCC.2006.357864","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357864","url":null,"abstract":"This paper presents a versatile multimedia functional unit (VMFU) which can compute six arithmetic operations, i.e. addition, subtraction, multiplication, MAC, interpolation, and SAD with different configurations. The VMFU is constructed on the basis of a row-based modified Booth encoding multiplier which consumes the lowest power among others according to our transistor-level simulations. Besides, we apply the spurious power suppression technique (SPST) to the proposed VMFU to decrease the wasted dynamic power dissipation. From the transistor-level simulations, the proposed VMFU dissipates 0.0142 mW/MHz under a 0.18 mum/1.8V CMOS technology. Adopting the SPST can reduce 24% power consumption with only a 15% area overhead.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"2 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116927268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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