Pub Date : 2006-11-01DOI: 10.1093/ietele/e90-c.10.1927
H. Shimano, F. Morishita, K. Dosaka, K. Arimoto
The advanced-DFM RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability(@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 cell/bit with the complementary dynamic memory operation and has the 1 cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (sense synchronized write) peripheral circuit technologies are also adopted for the low voltage and FV controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.
{"title":"A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform","authors":"H. Shimano, F. Morishita, K. Dosaka, K. Arimoto","doi":"10.1093/ietele/e90-c.10.1927","DOIUrl":"https://doi.org/10.1093/ietele/e90-c.10.1927","url":null,"abstract":"The advanced-DFM RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability(@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 cell/bit with the complementary dynamic memory operation and has the 1 cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (sense synchronized write) peripheral circuit technologies are also adopted for the low voltage and FV controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126429950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357880
J. Koh, Jungeun Lee, Chun-Deok Suh, Hoon-Tae Kim
We present new circuit architecture for the 1/f noise reduction in a CMOS Miller operational amplifier. Compared to a reference circuit, the 1/f noise reduction of 7 dB is achieved for a CMOS Miller operational amplifier implemented in a 0.13 μm 1.5 V standard CMOS technology. This architecture successfully reduces the 1/f noise and is applicable to a continuous signal processing analog IC's.
{"title":"A 1/f-Noise Reduction Architecture for an Operational Amplifier in a 0.13 μm Standard digital CMOS technology","authors":"J. Koh, Jungeun Lee, Chun-Deok Suh, Hoon-Tae Kim","doi":"10.1109/ASSCC.2006.357880","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357880","url":null,"abstract":"We present new circuit architecture for the 1/f noise reduction in a CMOS Miller operational amplifier. Compared to a reference circuit, the 1/f noise reduction of 7 dB is achieved for a CMOS Miller operational amplifier implemented in a 0.13 μm 1.5 V standard CMOS technology. This architecture successfully reduces the 1/f noise and is applicable to a continuous signal processing analog IC's.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"26 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357893
S. Kousai, M. Hamada, R. Ito, T. Itakura
A fifth order LPF with a quality factor(Q) tuning circuit has been implemented for IEEE802.11 n in a 0.13 mum CMOS technology. The proposed Q tuning technique enables a 19.7 MHz, active-RC Chebyshev LPF. The filter has 2 dB gain, 30 nV/Hz1/2 input referred noise, 113 dB muV input PIdB, draws 7.5 mA current from 1.5 V supply and occupies an area of 0.2 mm2.
在0.13 μ m CMOS技术下，实现了IEEE802.11 n的带质量因子(Q)调谐电路的五阶LPF。提出的Q调谐技术可实现19.7 MHz有源rc切比雪夫LPF。该滤波器具有2 dB增益，30 nV/Hz1/2输入参考噪声，113 dB muV输入PIdB，从1.5 V电源吸收7.5 mA电流，占地面积为0.2 mm2。
{"title":"A 19.7 MHz, 5th Order Active-RC Chebyshev LPF for IEEE802.11n with Automatic Quality Factor Tuning Scheme","authors":"S. Kousai, M. Hamada, R. Ito, T. Itakura","doi":"10.1109/ASSCC.2006.357893","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357893","url":null,"abstract":"A fifth order LPF with a quality factor(Q) tuning circuit has been implemented for IEEE802.11 n in a 0.13 mum CMOS technology. The proposed Q tuning technique enables a 19.7 MHz, active-RC Chebyshev LPF. The filter has 2 dB gain, 30 nV/Hz1/2 input referred noise, 113 dB muV input PIdB, draws 7.5 mA current from 1.5 V supply and occupies an area of 0.2 mm2.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132207447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357865
Kunjie Liu, Xing Qin, Xiaolang Yan, Li Quan
A single instruction multiple data (SIMD) video signal processor (VSP) is presented in this paper. To provide flexible and efficient data organization, a separate control/data-preparing pipeline and global switch register file with write-transposer and read-permuter is designed. Since data preparation is offloaded from computing core, this VSP promises sustained performance close to its peak computational rates of 64-bit SIMD ALU/MAC datapath. The benchmarking shows that the proposed VSP forms a highly efficient solution to emerging H.264/AVC video decoder.
{"title":"A SIMD Video Signal Processor with Efficient Data Organization","authors":"Kunjie Liu, Xing Qin, Xiaolang Yan, Li Quan","doi":"10.1109/ASSCC.2006.357865","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357865","url":null,"abstract":"A single instruction multiple data (SIMD) video signal processor (VSP) is presented in this paper. To provide flexible and efficient data organization, a separate control/data-preparing pipeline and global switch register file with write-transposer and read-permuter is designed. Since data preparation is offloaded from computing core, this VSP promises sustained performance close to its peak computational rates of 64-bit SIMD ALU/MAC datapath. The benchmarking shows that the proposed VSP forms a highly efficient solution to emerging H.264/AVC video decoder.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128716490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357874
M. Hariyama, W. H. Muthumala, M. Kameyama
Dynamically programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One important issue on DPGAs is the large amount of configuration memory, which leads to area-inefficient implementation and large static power dissipation. This paper presents novel architecture of a switch block to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18 mum CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310 MHz and 272 MHz, respectively. The area of the proposed MC-FPGA is reduced to 45% of a typical MC-FPGA under a constraint of 8 contexts.
动态可编程门阵列(DPGAs)比传统的fpga实现成本更低，因为它们可以有效地及时重用有限的硬件资源。DPGAs的一个重要问题是大量的配置内存，这会导致面积低效的实现和大的静态功耗。本文提出了一种新颖的开关块结构，以克服对组态存储器容量的要求。我们的主要思想是通过使用细粒度的switch元素来利用不同上下文之间的冗余。所提出的MC-FPGA采用0.18 μ m CMOS技术设计。其最大时钟频率为310 MHz，上下文切换频率为272 MHz。在8个上下文的约束下，所提出的MC-FPGA的面积减少到典型MC-FPGA的45%。
{"title":"Dynamically Reconfigurable Gate Array Based on Fine-Grained Switch Elements and Its CAD Environment","authors":"M. Hariyama, W. H. Muthumala, M. Kameyama","doi":"10.1109/ASSCC.2006.357874","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357874","url":null,"abstract":"Dynamically programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One important issue on DPGAs is the large amount of configuration memory, which leads to area-inefficient implementation and large static power dissipation. This paper presents novel architecture of a switch block to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18 mum CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310 MHz and 272 MHz, respectively. The area of the proposed MC-FPGA is reduced to 45% of a typical MC-FPGA under a constraint of 8 contexts.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122436904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357892
Xiangyu Li, Sun Yi-he
THDFAES04 is a data flow random execution Rijndael encryption ASIC, which can resist against side-channel attacks and is low power. It is based on dynamic data-flow architecture. It performs token matching and random service jointly by the token Hold-Match-Fetch components. In experiments, it could resist 15000 less samples correlation power analysis attack. The fabricated chip's average energy of one 128 bits key AES encryption is 0.053 muJ. Its die size is 2.21 mm2. Its throughput distributes between 59 Mbps and 63 Mbps.
{"title":"A Low Power Side Channel Attack Resistant Data Flow Rindael Encryption ASIC","authors":"Xiangyu Li, Sun Yi-he","doi":"10.1109/ASSCC.2006.357892","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357892","url":null,"abstract":"THDFAES04 is a data flow random execution Rijndael encryption ASIC, which can resist against side-channel attacks and is low power. It is based on dynamic data-flow architecture. It performs token matching and random service jointly by the token Hold-Match-Fetch components. In experiments, it could resist 15000 less samples correlation power analysis attack. The fabricated chip's average energy of one 128 bits key AES encryption is 0.053 muJ. Its die size is 2.21 mm2. Its throughput distributes between 59 Mbps and 63 Mbps.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122658483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357903
Rong-Jyi Yang, Shen-Iuan Liu
A. 2.5GHz, 30mW, 0.03mm2, all-digital DLL in 0.13mum CMOS technology is presented. The lattice delay unit provides both a small delay step and a fixed intrinsic delay of two NAND gates. A modified binary search controller reduces the locking time and allows the DLL to track the PVT variations. This DLL locks in 24 cycles and has the closed-loop characteristic with pk-pk jitter of 14ps.
A.提出了一种基于0.13 μ m CMOS技术的2.5GHz、30mW、0.03mm2全数字DLL。晶格延迟单元提供了两个NAND门的小延迟步长和固定的固有延迟。修改后的二进制搜索控制器减少了锁定时间，并允许DLL跟踪PVT的变化。该DLL锁定24个周期，具有14ps的pk-pk抖动的闭环特性。
{"title":"A 2.5GHz, 30mW, 0.03mm2, All-Digital Delay-Locked Loop","authors":"Rong-Jyi Yang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2006.357903","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357903","url":null,"abstract":"A. 2.5GHz, 30mW, 0.03mm2, all-digital DLL in 0.13mum CMOS technology is presented. The lattice delay unit provides both a small delay step and a fixed intrinsic delay of two NAND gates. A modified binary search controller reduces the locking time and allows the DLL to track the PVT variations. This DLL locks in 24 cycles and has the closed-loop characteristic with pk-pk jitter of 14ps.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132250403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357937
H. Muljono, S. Rusu, K. Tian, M. Atria, M. Chan, Charlie Lin
A 65 nm 1.2 V GTL bus interface achieves 800 MT/s 6.4 GB/S data rate in a 3-load multi-processor (MP) environment. To enable a 20% increase in data rate compared to previous design, it utilizes a staged driver, DLL controlled predriver, Tco compensation, data/strobe time shifter, high gain differential amplifier as well as advanced process, voltage and temperature (PVT) compensation design.
65 nm 1.2 V GTL总线接口在3负载多处理器(MP)环境下实现了800 MT/s 6.4 GB/ s的数据速率。为了使数据速率比以前的设计提高20%，它采用了分级驱动、DLL控制的预驱动、Tco补偿、数据/频门时移器、高增益差分放大器以及先进的工艺、电压和温度(PVT)补偿设计。
{"title":"A 800MT/s Multiprocessor Bus Interface With Strobe Centering Architecture","authors":"H. Muljono, S. Rusu, K. Tian, M. Atria, M. Chan, Charlie Lin","doi":"10.1109/ASSCC.2006.357937","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357937","url":null,"abstract":"A 65 nm 1.2 V GTL bus interface achieves 800 MT/s 6.4 GB/S data rate in a 3-load multi-processor (MP) environment. To enable a 20% increase in data rate compared to previous design, it utilizes a staged driver, DLL controlled predriver, Tco compensation, data/strobe time shifter, high gain differential amplifier as well as advanced process, voltage and temperature (PVT) compensation design.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132521116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357850
H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, J. Kudoh, K. Yahagi, T. Matsuura, H. Nakane, H. Kobayashi, M. Hotta, T. Tsukada, K. Mashiko, A. Wada
A second-order multi-bit switched-capacitor complex bandpass DeltaSigmaAD modulator has been designed and fabricated for application to low-IF receivers in wireless communication systems such as Bluetooth and WLAN. We propose a new structure of a complex bandpass filter in forward path with I, Q dynamic matching which is equivalent to the conventional one but it can be divided into two separate parts. As a result, the DeltaSigma modulator which constituted with our proposed complex filter can be completely divided into two separate parts too, and there are not any signal line crossing between the upper and lower paths by a complex filter and feedback from DACs. Therefore, the layout design of the modulator can be greatly simplified. Nine-level two quantizers and four DACs are used in the modulator for lower power implementation and higher SNDR, but the nonlinearities of DACs are not noise-shaped and the SNDR of the DeltaSigma ADC degrades. We have employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized just by adding simple digital circuitry. Implemented in a 0.18-mum CMOS process and at 2.8 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion (SNDR) of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm2.
{"title":"A Multibit Complex Bandpass AZAD Modulator with I, Q Dynamic Matching and DWA Algorithm","authors":"H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, J. Kudoh, K. Yahagi, T. Matsuura, H. Nakane, H. Kobayashi, M. Hotta, T. Tsukada, K. Mashiko, A. Wada","doi":"10.1109/ASSCC.2006.357850","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357850","url":null,"abstract":"A second-order multi-bit switched-capacitor complex bandpass DeltaSigmaAD modulator has been designed and fabricated for application to low-IF receivers in wireless communication systems such as Bluetooth and WLAN. We propose a new structure of a complex bandpass filter in forward path with I, Q dynamic matching which is equivalent to the conventional one but it can be divided into two separate parts. As a result, the DeltaSigma modulator which constituted with our proposed complex filter can be completely divided into two separate parts too, and there are not any signal line crossing between the upper and lower paths by a complex filter and feedback from DACs. Therefore, the layout design of the modulator can be greatly simplified. Nine-level two quantizers and four DACs are used in the modulator for lower power implementation and higher SNDR, but the nonlinearities of DACs are not noise-shaped and the SNDR of the DeltaSigma ADC degrades. We have employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized just by adding simple digital circuitry. Implemented in a 0.18-mum CMOS process and at 2.8 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion (SNDR) of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm2.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121414678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357925
Yusaku Ito, H. Sugawara, Kenichi Okada, K. Masu
This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed VCO has a core VCO and a tuning-range extension circuit, which consists of switches, a mixer, dividers, and variable gain combiners with a spurious rejection technique. The experimental results exhibit 0.98-to-6.6 GHz continuous frequency tuning with -206dBc/Hz of FoMT, which is fabricated by using a 0.18 mum CMOS process. The frequency tuning range (FTR) is 149 %, and the chip area is 800 mum x 540 mum.
提出了一种适用于多波段收发器的新型宽带压控振荡器(VCO)。所提出的压控振荡器具有一个核心压控振荡器和一个调谐范围扩展电路，该电路由开关、混频器、分频器和具有抑制杂散技术的可变增益合成器组成。实验结果表明，采用0.18 μ m CMOS工艺制备的fmt具有-206dBc/Hz的0.98 ~ 6.6 GHz连续调谐频率。频率调谐范围(FTR)为149%，芯片面积为800 μ m × 540 μ m。
{"title":"A 0.98 to 6.6 Hz Tunable Wideband VCO in a 180nm CMOS Technology for Reconfigurable Radio Transceiver","authors":"Yusaku Ito, H. Sugawara, Kenichi Okada, K. Masu","doi":"10.1109/ASSCC.2006.357925","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357925","url":null,"abstract":"This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed VCO has a core VCO and a tuning-range extension circuit, which consists of switches, a mixer, dividers, and variable gain combiners with a spurious rejection technique. The experimental results exhibit 0.98-to-6.6 GHz continuous frequency tuning with -206dBc/Hz of FoMT, which is fabricated by using a 0.18 mum CMOS process. The frequency tuning range (FTR) is 149 %, and the chip area is 800 mum x 540 mum.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125652288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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