Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357885
A. Valdes-Garcia, S. Reynolds, U. Pfeiffer
A millimeter-wave Class-E tuned power amplifier is realized in 0.13 mum SiGe BiCMOS technology. To accomplish switching-mode operation at 60GHz, the transmission line input impedance transformation network provides a low real source impedance rather than optimum power match. The prototype IC is a single-ended single stage design that operates from a 1.2V supply and employs an area of 0.98mm2. Measurement results show a saturated output power >11.1dBm with peak PAE>15% from 55-60GHz. At 58GHz it achieves a peak PAE of 20.9%, peak power gain of 4.2dB and saturated output power of 11.7dBm.
{"title":"A 60GHz Class-E Power Amplifier in SiGe","authors":"A. Valdes-Garcia, S. Reynolds, U. Pfeiffer","doi":"10.1109/ASSCC.2006.357885","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357885","url":null,"abstract":"A millimeter-wave Class-E tuned power amplifier is realized in 0.13 mum SiGe BiCMOS technology. To accomplish switching-mode operation at 60GHz, the transmission line input impedance transformation network provides a low real source impedance rather than optimum power match. The prototype IC is a single-ended single stage design that operates from a 1.2V supply and employs an area of 0.98mm2. Measurement results show a saturated output power >11.1dBm with peak PAE>15% from 55-60GHz. At 58GHz it achieves a peak PAE of 20.9%, peak power gain of 4.2dB and saturated output power of 11.7dBm.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129081889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357932
J. Koon-Lun Wong, Ehung Chen, K. Chih-Kong Yang
Discrete-time edge equalizers can enhance symbol-rate equalizers by compensating for inter-symbol interference at data transitions (timing ISI). The reduced timing ISI improves the timing margin and provides the CDR with clean timing information. This paper shows that adapting tap weights with standard blind LMS algorithm results in a reduced eye and may not converge. A modified algorithm is introduced to maximize the data eye.
{"title":"Modified LMS Adaptation Algorithm for a Discrete-Time Edge Equalizer of Serial I/O","authors":"J. Koon-Lun Wong, Ehung Chen, K. Chih-Kong Yang","doi":"10.1109/ASSCC.2006.357932","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357932","url":null,"abstract":"Discrete-time edge equalizers can enhance symbol-rate equalizers by compensating for inter-symbol interference at data transitions (timing ISI). The reduced timing ISI improves the timing margin and provides the CDR with clean timing information. This paper shows that adapting tap weights with standard blind LMS algorithm results in a reduced eye and may not converge. A modified algorithm is introduced to maximize the data eye.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126269284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357847
V. Yeh, C. Huang, Chia-Huang Fu, Chieh‐Hung Chen, Tsong-Lin Lee, Hsiang-Hui Chang, Tsung-Yao Lin, Yung-Chun Lei
Modern FM radio receiver on portable devices requires low power consumption, small size and good audio performance. This paper reports a highly integrated FM radio single-chip receiver optimized for low power consumption and minimum external components. The operating frequency is 76 MHz ~ 108 MHz which covers EURO/US/Japan FM bands. The chip integrates all essential RF front-end circuits including LNA and mixer with automatic gain control (AGC), and mixed-signal functional blocks such as channel filter, limiting amplifier, integrated FM demodulator, stereo decoder, and integrated frequency locked loop (FLL). The total current consumption is only 10 mA off 2.8 V while maintaining sensitivity as low as 1.1 μV. The audio signal-to-noise ratio (SNR) is 58 dB. Total harmonic distortion (THD) is less than 0.4 % and the stereo audio separation (SEP) is more than 30 dB. This chip is fabricated in 0.35 μm BiCMOS process and packaged in 28-pin 4×4 mm2 LGA.
{"title":"A 10-mA Current and 1.1-μV Sensitivity Single-Chip FM Radio Receiver","authors":"V. Yeh, C. Huang, Chia-Huang Fu, Chieh‐Hung Chen, Tsong-Lin Lee, Hsiang-Hui Chang, Tsung-Yao Lin, Yung-Chun Lei","doi":"10.1109/ASSCC.2006.357847","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357847","url":null,"abstract":"Modern FM radio receiver on portable devices requires low power consumption, small size and good audio performance. This paper reports a highly integrated FM radio single-chip receiver optimized for low power consumption and minimum external components. The operating frequency is 76 MHz ~ 108 MHz which covers EURO/US/Japan FM bands. The chip integrates all essential RF front-end circuits including LNA and mixer with automatic gain control (AGC), and mixed-signal functional blocks such as channel filter, limiting amplifier, integrated FM demodulator, stereo decoder, and integrated frequency locked loop (FLL). The total current consumption is only 10 mA off 2.8 V while maintaining sensitivity as low as 1.1 μV. The audio signal-to-noise ratio (SNR) is 58 dB. Total harmonic distortion (THD) is less than 0.4 % and the stereo audio separation (SEP) is more than 30 dB. This chip is fabricated in 0.35 μm BiCMOS process and packaged in 28-pin 4×4 mm2 LGA.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122080341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357930
Hua-Chin Lee, Chien-Chih Lin, Chorng-Kuang Wang
This paper presents a CMOS programmable gain amplifier (PGA) with 3dB bandwidth greater than 290MHz. The PGA can provide 50dB gain with 20dB gain control range, and the gain step is ldB with -0.4 to +0.4dB gain error. The minimal acceptable input signal is -52dBm and the 1dB compression point is -6dBm. It consumes 4 mA in core stage from IV supply voltage. This PGA is fabricated in 90nm CMOS one-poly nine-metal digital process and the core area is 0.2x0.15 mm2.
{"title":"A 290MHz 50dB Programmable Gain Amplifier for Wideband Communications","authors":"Hua-Chin Lee, Chien-Chih Lin, Chorng-Kuang Wang","doi":"10.1109/ASSCC.2006.357930","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357930","url":null,"abstract":"This paper presents a CMOS programmable gain amplifier (PGA) with 3dB bandwidth greater than 290MHz. The PGA can provide 50dB gain with 20dB gain control range, and the gain step is ldB with -0.4 to +0.4dB gain error. The minimal acceptable input signal is -52dBm and the 1dB compression point is -6dBm. It consumes 4 mA in core stage from IV supply voltage. This PGA is fabricated in 90nm CMOS one-poly nine-metal digital process and the core area is 0.2x0.15 mm2.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127419133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357939
A. Keshavarzi, A. Raychowdhury, J. Kurtin, K. Roy, V. De
In this paper, we studied the scalability of CNT-based devices and circuits. We focused mainly on SB CNFETs and determined 1-1,5 nm to be an optimum tube diameter to achieve the best performance-power trade-off We established that CNTs have a potential in logic applications. We introduced FOA metric and showed improvement over Si-based MOSFETs and we extended our discussion toward scalability of CNFETs. CNTs are potentially a promising novel material to be integrated into future technology generations if research communities can collectively address some of the barriers and fabrication challenges this material system is facing.
{"title":"Scalability of Carbon Nanotube FET-based Circuits","authors":"A. Keshavarzi, A. Raychowdhury, J. Kurtin, K. Roy, V. De","doi":"10.1109/ASSCC.2006.357939","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357939","url":null,"abstract":"In this paper, we studied the scalability of CNT-based devices and circuits. We focused mainly on SB CNFETs and determined 1-1,5 nm to be an optimum tube diameter to achieve the best performance-power trade-off We established that CNTs have a potential in logic applications. We introduced FOA metric and showed improvement over Si-based MOSFETs and we extended our discussion toward scalability of CNFETs. CNTs are potentially a promising novel material to be integrated into future technology generations if research communities can collectively address some of the barriers and fabrication challenges this material system is facing.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130809782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357920
Ja-Hyun Koo, Yun-Jeong Kim, Bong-Hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim
In this paper, a 4-bit 1.356GS/S analog to digital (A/D) converter targeted for the direct spectrum code division multiple access ultra wide band (DS-CDMA UWB) is presented. The A/D converter uses a fully differential flash architecture. To achieve low power consumption and high conversion rate, the proposed converter is designed with current mode amplifier (CMA) and each preamplifier includes a dual sense amplifier (DSA). The A/D converter can sample input frequencies above 650 MHz with this current mode processing technique. The A/D converter achieves 3.7 effective number of bits (ENOBs) for a 30MHz sinusoidal input and 3.35 ENOBs for a 650 MHz input at a 1.356 GHz sampling rate. At 1.356 GS/s, the current consumption is 38 mA including digital logic with a power supply of 1.8V. The proposed A/D converter is fabricated using a 0.18-mum 6Metal lPoly CMOS process and the active area is 0.35 mm2.
{"title":"A 4-bit 1.356 Gsps ADC for DS-CDMA UWB System","authors":"Ja-Hyun Koo, Yun-Jeong Kim, Bong-Hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim","doi":"10.1109/ASSCC.2006.357920","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357920","url":null,"abstract":"In this paper, a 4-bit 1.356GS/S analog to digital (A/D) converter targeted for the direct spectrum code division multiple access ultra wide band (DS-CDMA UWB) is presented. The A/D converter uses a fully differential flash architecture. To achieve low power consumption and high conversion rate, the proposed converter is designed with current mode amplifier (CMA) and each preamplifier includes a dual sense amplifier (DSA). The A/D converter can sample input frequencies above 650 MHz with this current mode processing technique. The A/D converter achieves 3.7 effective number of bits (ENOBs) for a 30MHz sinusoidal input and 3.35 ENOBs for a 650 MHz input at a 1.356 GHz sampling rate. At 1.356 GS/s, the current consumption is 38 mA including digital logic with a power supply of 1.8V. The proposed A/D converter is fabricated using a 0.18-mum 6Metal lPoly CMOS process and the active area is 0.35 mm2.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122236242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357902
Qiang Li, Y.P. Zhang, J.S. Chang
An inductorless low-noise amplifier (LNA) design for ultra-wideband (UWB) receiver front-end is presented. Without on-chip inductors, the ultra-wide bandwidth is achieved by a syncretic adoption of thermal noise canceling, capacitor peaking, and current reuse. Fabricated in a 0.13-mum CMOS technology, the LNA exhibits a small signal gain of 11-dB and a -3-d 15 bandwidth of 2-9.6-GHz. The input return loss is less than -9.5-dB, and the noise figure is 3.6-4.8-dB. The LNA consumes 19-mW from a low supply voltage of 1.5-V. The LNA circuit with pad occupies only 0.17 mm2 die area, which is among the smallest reported designs.
{"title":"An Inductorless Low-Noise Amplifier with Noise Cancellation for UWB Receiver Front-End","authors":"Qiang Li, Y.P. Zhang, J.S. Chang","doi":"10.1109/ASSCC.2006.357902","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357902","url":null,"abstract":"An inductorless low-noise amplifier (LNA) design for ultra-wideband (UWB) receiver front-end is presented. Without on-chip inductors, the ultra-wide bandwidth is achieved by a syncretic adoption of thermal noise canceling, capacitor peaking, and current reuse. Fabricated in a 0.13-mum CMOS technology, the LNA exhibits a small signal gain of 11-dB and a -3-d 15 bandwidth of 2-9.6-GHz. The input return loss is less than -9.5-dB, and the noise figure is 3.6-4.8-dB. The LNA consumes 19-mW from a low supply voltage of 1.5-V. The LNA circuit with pad occupies only 0.17 mm2 die area, which is among the smallest reported designs.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"80 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116067952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357872
Y. Xu, R. Yu, W. Hsu, A.R. Brown
This paper describes a bandpass SigmaDelta modulator employing a silicon micromechanical resonator as the loop filter. The micromechanical resonator is chosen primarily for its high quality factor and low power consumption. A 2nd-order prototype bandpass SigmaDelta modulator is realized in a 0.35-mum CMOS process and tested with a 19.6-MHz silicon micromechanical resonator. The measured results show a peak SNDR of 51 dB and a dynamic range of 52.5 dB in a 200-kHz signal bandwidth.
本文介绍了一种采用硅微机械谐振器作为环路滤波器的带通SigmaDelta调制器。选择微机械谐振器主要是因为其高质量因数和低功耗。在0.35 μ m CMOS工艺中实现了二阶带通SigmaDelta调制器原型，并在19.6 mhz硅微机械谐振器上进行了测试。测量结果表明，在200 khz信号带宽下，峰值SNDR为51 dB，动态范围为52.5 dB。
{"title":"A Silicon Micromechanical Resonator Based CMOS Bandpass Sigma-Delta Modulator","authors":"Y. Xu, R. Yu, W. Hsu, A.R. Brown","doi":"10.1109/ASSCC.2006.357872","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357872","url":null,"abstract":"This paper describes a bandpass SigmaDelta modulator employing a silicon micromechanical resonator as the loop filter. The micromechanical resonator is chosen primarily for its high quality factor and low power consumption. A 2nd-order prototype bandpass SigmaDelta modulator is realized in a 0.35-mum CMOS process and tested with a 19.6-MHz silicon micromechanical resonator. The measured results show a peak SNDR of 51 dB and a dynamic range of 52.5 dB in a 200-kHz signal bandwidth.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133811827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357889
Yanjun Zhang, Hu He, Zhixiong Zhou, Xu Yang, Yihe Sun
This paper describes a scaleable DSP architecture for ASIP design and a retargetable compiler based on ORC. By configuring this architecture, designers can easily get the ASIP for one set of applications. A DSP named THUASDSP2004 is developed manually based on this architecture and the compiler can give a satisfied result.
{"title":"A Scaleable DSP System for ASIP Design","authors":"Yanjun Zhang, Hu He, Zhixiong Zhou, Xu Yang, Yihe Sun","doi":"10.1109/ASSCC.2006.357889","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357889","url":null,"abstract":"This paper describes a scaleable DSP architecture for ASIP design and a retargetable compiler based on ORC. By configuring this architecture, designers can easily get the ASIP for one set of applications. A DSP named THUASDSP2004 is developed manually based on this architecture and the compiler can give a satisfied result.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122885443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357848
S. Gambini, J. Rabaey
A moderate resolution analog-to-digital converter targeting wireless sensor networks applications is presented. Employing a successive approximation architecture, the device achieves 6 bits of resolution at 1.5 MS/s output rate, while drawing 28muA from a low 0.5 V supply, corresponding to a Figure of Merit (FOM) of .25pJ/conversion step. Low-density metal5-metal6 capacitors guarantee feedback DAC linearity while minimizing input capacitance, while the use of a passive sample and hold, combined with a class-AB comparator reduce analog power dissipation to 4muW (30% of the total). The analog core is operational for supply values as low as .3V, even though sampling rate is reduced to 175kS/s.
{"title":"A 1.5MS/s 6-bit ADC with 0.5V supply","authors":"S. Gambini, J. Rabaey","doi":"10.1109/ASSCC.2006.357848","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357848","url":null,"abstract":"A moderate resolution analog-to-digital converter targeting wireless sensor networks applications is presented. Employing a successive approximation architecture, the device achieves 6 bits of resolution at 1.5 MS/s output rate, while drawing 28muA from a low 0.5 V supply, corresponding to a Figure of Merit (FOM) of .25pJ/conversion step. Low-density metal5-metal6 capacitors guarantee feedback DAC linearity while minimizing input capacitance, while the use of a passive sample and hold, combined with a class-AB comparator reduce analog power dissipation to 4muW (30% of the total). The analog core is operational for supply values as low as .3V, even though sampling rate is reduced to 175kS/s.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128576229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：