Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345759
L. Economikos, X. Wang, X. Sakamoto, P. Ong, M. Naujok, R. Knarr, L. Chen, Y. Moon, S. Neo, J. Salfelder, A. Duboust, A. Manens, W. Lu, S. Shrauti, F. Liu, S. Tsai, W. Swart
A novel copper (Cu) planarization process, Ecmp, integrating electro-chemical mechanical polishing capability on a 300mm CMP platform with low down force conventional polishing processes is being developed and evaluated on low-k CVD devices. In the integrated Ecmp process, the bulk Cu is removed by electro-chemical mechanical polishing at a high rate which is controlled by applied charge and is independent of down force (0.3psi bulk Cu removal step). The Ecmp process removes topography efficiently and produces a thin planarized Cu film across the wafer to match that of the conventional Cu planarization step. The Cu thickness profile produced by electro-chemical planarization allows the conventional planarization process to clear remaining Cu with low dishing across the wafer. Therefore, an excessive dielectric removal for dishing correction is not required, making the process extendible to ultra-low k dielectrics that require a protective capping layer to be retained after polishing. Experiments are conducted to evaluate the planarization efficiency, film profile, and endpoint control, cost of consumables, pattern density sensitivity and defect density. The mechanical and electrical results indicate that Ecmp enables the planarization of dual damascene structures with minimal dielectric erosion and defect density.
{"title":"Integrated electro-chemical mechanical planarization (Ecmp) for future generation device technology","authors":"L. Economikos, X. Wang, X. Sakamoto, P. Ong, M. Naujok, R. Knarr, L. Chen, Y. Moon, S. Neo, J. Salfelder, A. Duboust, A. Manens, W. Lu, S. Shrauti, F. Liu, S. Tsai, W. Swart","doi":"10.1109/IITC.2004.1345759","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345759","url":null,"abstract":"A novel copper (Cu) planarization process, Ecmp, integrating electro-chemical mechanical polishing capability on a 300mm CMP platform with low down force conventional polishing processes is being developed and evaluated on low-k CVD devices. In the integrated Ecmp process, the bulk Cu is removed by electro-chemical mechanical polishing at a high rate which is controlled by applied charge and is independent of down force (0.3psi bulk Cu removal step). The Ecmp process removes topography efficiently and produces a thin planarized Cu film across the wafer to match that of the conventional Cu planarization step. The Cu thickness profile produced by electro-chemical planarization allows the conventional planarization process to clear remaining Cu with low dishing across the wafer. Therefore, an excessive dielectric removal for dishing correction is not required, making the process extendible to ultra-low k dielectrics that require a protective capping layer to be retained after polishing. Experiments are conducted to evaluate the planarization efficiency, film profile, and endpoint control, cost of consumables, pattern density sensitivity and defect density. The mechanical and electrical results indicate that Ecmp enables the planarization of dual damascene structures with minimal dielectric erosion and defect density.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133826208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345680
S. Brongersma, K. Vanstreels, W. Wu, W. Zhang, D. Ernur, J. D’Haen, V. Terzieva, M. Van Hove, T. Clarysse, L. Carbonell, W. Vandervorst, W. De Ceuninck, K. Maex
The size effect observed for copper in reduced dimensions is studied by several different routes in order to further understand the relative influence of various scattering mechanisms and determine where to focus our efforts in order to reduce line resistance.
{"title":"Copper grain growth in reduced dimensions","authors":"S. Brongersma, K. Vanstreels, W. Wu, W. Zhang, D. Ernur, J. D’Haen, V. Terzieva, M. Van Hove, T. Clarysse, L. Carbonell, W. Vandervorst, W. De Ceuninck, K. Maex","doi":"10.1109/IITC.2004.1345680","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345680","url":null,"abstract":"The size effect observed for copper in reduced dimensions is studied by several different routes in order to further understand the relative influence of various scattering mechanisms and determine where to focus our efforts in order to reduce line resistance.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126497832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345689
C. Thompson, C. Gan, S. Alam, D. Troxel
Accurate circuit-level reliability analyses can be based in experimental results for simple interconnect segments if interconnect trees, linked interconnect segments within one level of metallization, are used as fundamental reliability units. The reliability behaviour of both segments and trees is different for Al and Cu. A revised method is proposed for tree-based circuit-level reliability analyses for Cu. The types of additional experimental data that would allow assessments with improves accuracy are outlined.
{"title":"Experiments and models for circuit-level assessment of the reliability of Cu metallization","authors":"C. Thompson, C. Gan, S. Alam, D. Troxel","doi":"10.1109/IITC.2004.1345689","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345689","url":null,"abstract":"Accurate circuit-level reliability analyses can be based in experimental results for simple interconnect segments if interconnect trees, linked interconnect segments within one level of metallization, are used as fundamental reliability units. The reliability behaviour of both segments and trees is different for Al and Cu. A revised method is proposed for tree-based circuit-level reliability analyses for Cu. The types of additional experimental data that would allow assessments with improves accuracy are outlined.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122404857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345704
S. Pozder, J. Lu, Y. Kwon, S. Zollner, J. Yu, J. McMahon, T. Cale, K. Yu, R. Gutmann
A previously proposed wafer-level 3D IC technology platform has been extensively evaluated for compatibility with conventional IC packaging. Results demonstrate that the dielectric glue bonding using benzocyclobutene (BCB) is compatible with conventional wafer sawing techniques, and that the bond adhesion strength is unaffected by die-level autoclave and thermal shock testing. High-resolution X-ray diffraction (HRXRD) results show that the stress levels in 70 nm or 140 nm thick silicon SOI layers had no appreciable change after BCB bonding and wafer-thinning.
{"title":"Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform","authors":"S. Pozder, J. Lu, Y. Kwon, S. Zollner, J. Yu, J. McMahon, T. Cale, K. Yu, R. Gutmann","doi":"10.1109/IITC.2004.1345704","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345704","url":null,"abstract":"A previously proposed wafer-level 3D IC technology platform has been extensively evaluated for compatibility with conventional IC packaging. Results demonstrate that the dielectric glue bonding using benzocyclobutene (BCB) is compatible with conventional wafer sawing techniques, and that the bond adhesion strength is unaffected by die-level autoclave and thermal shock testing. High-resolution X-ray diffraction (HRXRD) results show that the stress levels in 70 nm or 140 nm thick silicon SOI layers had no appreciable change after BCB bonding and wafer-thinning.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121331633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345728
Y. Tretiakov, K. Vaed, D. Ahlgren, J. Rascoe, S. Venkatadri, Wayne H. Woods
This paper compares different de-embedding techniques for on-wafer transmission line interconnect characterization. The main goal is to contrast and correlate de-embedded S-parameters and extracted electrical characteristics versus industry standard electromagnetic solver results. For the first time the simplified "thru" technique and new "short-open" method are employed for de-embedding on-chip coplanar waveguides over the 0.1-70 GHz frequency bandwidth.
{"title":"On wafer de-embedding for SiGe/BiCMOS/RFCMOS transmission line interconnect characterization","authors":"Y. Tretiakov, K. Vaed, D. Ahlgren, J. Rascoe, S. Venkatadri, Wayne H. Woods","doi":"10.1109/IITC.2004.1345728","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345728","url":null,"abstract":"This paper compares different de-embedding techniques for on-wafer transmission line interconnect characterization. The main goal is to contrast and correlate de-embedded S-parameters and extracted electrical characteristics versus industry standard electromagnetic solver results. For the first time the simplified \"thru\" technique and new \"short-open\" method are employed for de-embedding on-chip coplanar waveguides over the 0.1-70 GHz frequency bandwidth.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126370456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345722
C. Guedj, L. Arnaud, M. Fayolle, V. Jousseaume, J. Guillaumond, J. Cluzel, A. Toffoli, G. Reimbold, D. Bouchu
The combination of porous ultra low k dielectric and copper metallization is an attractive alternative to meet the requirements of ITRS roadmap concerning the 65 nm interconnection technology, but very little is known about the reliability of such an approach. Porous materials are usually unstable and sensitive to moisture, but pore sealing is a possible strategy to overcome these detrimental effects. In this paper, we have studied the effect of pore sealing on the electrical performance and long-term reliability of ULK/Cu interconnects. The best pore sealing efficiency is obtained for a nominal thickness of 10 nm of a SiC:H sealing layer. With these conditions, the dielectric constant of the ULK is kept at 2.2 even after integration and an electromigration activation energy of 1.2 eV is obtained. The failures mechanisms have been correlated to SEM and FIB analysis.
{"title":"Effect of pore sealing on the reliability of ULK/Cu interconnects","authors":"C. Guedj, L. Arnaud, M. Fayolle, V. Jousseaume, J. Guillaumond, J. Cluzel, A. Toffoli, G. Reimbold, D. Bouchu","doi":"10.1109/IITC.2004.1345722","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345722","url":null,"abstract":"The combination of porous ultra low k dielectric and copper metallization is an attractive alternative to meet the requirements of ITRS roadmap concerning the 65 nm interconnection technology, but very little is known about the reliability of such an approach. Porous materials are usually unstable and sensitive to moisture, but pore sealing is a possible strategy to overcome these detrimental effects. In this paper, we have studied the effect of pore sealing on the electrical performance and long-term reliability of ULK/Cu interconnects. The best pore sealing efficiency is obtained for a nominal thickness of 10 nm of a SiC:H sealing layer. With these conditions, the dielectric constant of the ULK is kept at 2.2 even after integration and an electromigration activation energy of 1.2 eV is obtained. The failures mechanisms have been correlated to SEM and FIB analysis.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127942391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345667
L. Gosset, S. Chhun, A. Farcy, N. Casanova, V. Arnal, W. Besling, J. Torres
Simulated signal propagation performances including crosstalk and delay time were investigated for self-aligned barriers on copper, highlighting the benefits of introducing these barriers for the 65 and 45 nm technology nodes. As an alternative to electrolessly deposited alloys, a self-aligned barrier technique based on controlled Si enrichment of Cu and named CuSiN was introduced. Promising performances in terms of copper barrier efficiency, interconnect compatibility, integration (line and via resistances, leakage currents, coupling capacitances), and reliability were shown.
{"title":"Integration and performances of an alternative approach using copper silicide as a self-aligned barrier for 45 nm technology node Cu interconnects","authors":"L. Gosset, S. Chhun, A. Farcy, N. Casanova, V. Arnal, W. Besling, J. Torres","doi":"10.1109/IITC.2004.1345667","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345667","url":null,"abstract":"Simulated signal propagation performances including crosstalk and delay time were investigated for self-aligned barriers on copper, highlighting the benefits of introducing these barriers for the 65 and 45 nm technology nodes. As an alternative to electrolessly deposited alloys, a self-aligned barrier technique based on controlled Si enrichment of Cu and named CuSiN was introduced. Promising performances in terms of copper barrier efficiency, interconnect compatibility, integration (line and via resistances, leakage currents, coupling capacitances), and reliability were shown.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114567496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345706
W. Landers, D. Edelstein, L. Clevenger, C. Das, C. Yang, T. Aoki, F. Beaulieu, J. Casey, A. Cowley, M. Cullinan, T. Daubenspeck, C. Davis, J. Demarest, É. Duchesne, L. Guerin, D. Hawken, T. Ivers, M. Lane, X. Liu, T. Lombardi, C. McCarthy, C. Muzzy, J. Nadeau-Filteau, D. Questad, W. Sauter, T. Shaw, J. Wright
A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBM's internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.
{"title":"Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology","authors":"W. Landers, D. Edelstein, L. Clevenger, C. Das, C. Yang, T. Aoki, F. Beaulieu, J. Casey, A. Cowley, M. Cullinan, T. Daubenspeck, C. Davis, J. Demarest, É. Duchesne, L. Guerin, D. Hawken, T. Ivers, M. Lane, X. Liu, T. Lombardi, C. McCarthy, C. Muzzy, J. Nadeau-Filteau, D. Questad, W. Sauter, T. Shaw, J. Wright","doi":"10.1109/IITC.2004.1345706","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345706","url":null,"abstract":"A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBM's internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114237988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345760
E. Guyer, R. Dauskardt
Considerable efforts have been directed at integrating nanoporous low dielectric constant (LKD) materials into the interconnect structures of high-density integrated circuits. The reliable fabrication of devices containing these fragile materials is, however, a significant technological challenge due to their high propensity for mechanical failure during all levels of processing and subsequent packaging operations in which they are subjected to mechanical loads in the presence of aggressive aqueous environments, such as chemical mechanical planarization (CMP). Here we demonstrate the significant effect of CMP solution chemistry on interfacial adhesion and crack growth rates in nanoporous LKD thin-films as well as lithographically patterned structures containing copper and LKDs. A new mechanism of accelerated cracking in H/sub 2/O/sub 2/ environments is revealed.
{"title":"Accelerated crack growth of nanoporous low-k glasses in CMP slurry environments","authors":"E. Guyer, R. Dauskardt","doi":"10.1109/IITC.2004.1345760","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345760","url":null,"abstract":"Considerable efforts have been directed at integrating nanoporous low dielectric constant (LKD) materials into the interconnect structures of high-density integrated circuits. The reliable fabrication of devices containing these fragile materials is, however, a significant technological challenge due to their high propensity for mechanical failure during all levels of processing and subsequent packaging operations in which they are subjected to mechanical loads in the presence of aggressive aqueous environments, such as chemical mechanical planarization (CMP). Here we demonstrate the significant effect of CMP solution chemistry on interfacial adhesion and crack growth rates in nanoporous LKD thin-films as well as lithographically patterned structures containing copper and LKDs. A new mechanism of accelerated cracking in H/sub 2/O/sub 2/ environments is revealed.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114880599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345671
H. Oh, J. Chung, Jungwoo Lee, K. Kang, D. Park, S. Hah, I. Cho, K. Park
The effect of FSG film properties as inter-metal dielectrics on stress-induced voiding (SIV) phenomena in Cu dual-damascene interconnects has been investigated with various FSG-films. HDPFSG and PEFSG2 showed less SIV failure than those of PEFSGI and 3. These behaviors of SIV according to FSG films agree well with desorbed amount of hydrogen, oxygen and fluorine ions from FSG films at high temperature over 400/spl deg/C. The result of SIMS analysis suggests that SIV phenomena are improved by application of stable FSG film without desorption at high temperature such as HDPFSG and PEFSG2 used in this work.
{"title":"The effect of FSG stability at high temperature on stress-induced voiding in Cu dual-damascene interconnects","authors":"H. Oh, J. Chung, Jungwoo Lee, K. Kang, D. Park, S. Hah, I. Cho, K. Park","doi":"10.1109/IITC.2004.1345671","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345671","url":null,"abstract":"The effect of FSG film properties as inter-metal dielectrics on stress-induced voiding (SIV) phenomena in Cu dual-damascene interconnects has been investigated with various FSG-films. HDPFSG and PEFSG2 showed less SIV failure than those of PEFSGI and 3. These behaviors of SIV according to FSG films agree well with desorbed amount of hydrogen, oxygen and fluorine ions from FSG films at high temperature over 400/spl deg/C. The result of SIMS analysis suggests that SIV phenomena are improved by application of stable FSG film without desorption at high temperature such as HDPFSG and PEFSG2 used in this work.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123465520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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