Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345749
M. Okazaki, M. Hatano, K. Yoshida, S. Shibasaki, H. Kaneko, T. Yoda, N. Hayasaka
A very unique multiple pattern arrangement for low-k/Cu interconnect characterization method is introduced. Several hundreds of different shape 4-point probe Kelvin/via/interconnect test patterns are created. With these "Sea of Kelvin" multiple-pattern test structures, 65nm node generation feature size (0.10/spl mu/m /spl phi/ via). Low-k/Cu dual damascene interconnect is evaluated. Various aspects of pattern design dependent interconnect characteristics including the influence from the surrounding neighbour patterns are examined. This paper reports this new characterization method and its findings.
{"title":"\"Sea of Kelvin\" multiple-pattern arrangement interconnect characterization for low-k/Cu dual damascene and its findings","authors":"M. Okazaki, M. Hatano, K. Yoshida, S. Shibasaki, H. Kaneko, T. Yoda, N. Hayasaka","doi":"10.1109/IITC.2004.1345749","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345749","url":null,"abstract":"A very unique multiple pattern arrangement for low-k/Cu interconnect characterization method is introduced. Several hundreds of different shape 4-point probe Kelvin/via/interconnect test patterns are created. With these \"Sea of Kelvin\" multiple-pattern test structures, 65nm node generation feature size (0.10/spl mu/m /spl phi/ via). Low-k/Cu dual damascene interconnect is evaluated. Various aspects of pattern design dependent interconnect characteristics including the influence from the surrounding neighbour patterns are examined. This paper reports this new characterization method and its findings.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126531155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345716
S. Tokitoh, S. Kondo, B. Yoon, A. Namiki, K. Inukai, K. Misawa, S. Sone, H.J. Shin, Y. Matsubara, N. Ohashi, N. Kobayashi
The effects of CMP pressure on the via resistance yield of dual- and single-damascene interconnects consisting of porous low-k films have been investigated. Porous low-k films with different mechanical strengths (Young's modulus and hardness) were used. The via resistance yield was found to strongly depend on both the CMP pressure of the via-layer and mechanical strength of the via low-k film. Analysis of the results considering the mechanical and chemical aspects of the CMP process showed that using low-pressure CMP (1.5 psi) resulted in excellent electrical properties for Cu interconnects composed of the porous low-k (k=2.3) film with high mechanical strength (E=9.8GPa, H=1.2GPa).
{"title":"Enhancement in electrical via-yield of porous low-k/Cu integration by reducing CMP pressure","authors":"S. Tokitoh, S. Kondo, B. Yoon, A. Namiki, K. Inukai, K. Misawa, S. Sone, H.J. Shin, Y. Matsubara, N. Ohashi, N. Kobayashi","doi":"10.1109/IITC.2004.1345716","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345716","url":null,"abstract":"The effects of CMP pressure on the via resistance yield of dual- and single-damascene interconnects consisting of porous low-k films have been investigated. Porous low-k films with different mechanical strengths (Young's modulus and hardness) were used. The via resistance yield was found to strongly depend on both the CMP pressure of the via-layer and mechanical strength of the via low-k film. Analysis of the results considering the mechanical and chemical aspects of the CMP process showed that using low-pressure CMP (1.5 psi) resulted in excellent electrical properties for Cu interconnects composed of the porous low-k (k=2.3) film with high mechanical strength (E=9.8GPa, H=1.2GPa).","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127638303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345677
A. Furuya, E. Soda, K. Yoneda, T. Yoshie, H. Okamura, M. Shimada, N. Ohtsuka, S. Ogawa
Increase of process steps by pore-sealing and low via yield by low adhesion between Cu and barrier metal are cost issues when atomic layer deposited (ALD) barrier metal process is integrated into Cu/porous low-k interconnects. In order to solve these issues, etch-byproduct in-situ deposited on the sidewall and ALD-Ta is proposed. The etch-byproduct successfully prevented Ta penetration into the porous low-k film without increase process steps. ALD-Ta film of 0.8 nm, deposited by exposures of pentakisdimethylaminotantalium (PDMAT) and He/H/sub 2/ plasma to the substrate in turn, demonstrated strong adhesion layer as same as the conventional PVD barrier. Via yield of single-damascene Cu/porous low-k interconnects with the etch-byproduct was improved by substituting ALD-Ta for ALD-TaN.
{"title":"Pore-sealing by etch-byproduct followed by ALD-Ta adhesion layer for Cu/porous low-k interconnects","authors":"A. Furuya, E. Soda, K. Yoneda, T. Yoshie, H. Okamura, M. Shimada, N. Ohtsuka, S. Ogawa","doi":"10.1109/IITC.2004.1345677","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345677","url":null,"abstract":"Increase of process steps by pore-sealing and low via yield by low adhesion between Cu and barrier metal are cost issues when atomic layer deposited (ALD) barrier metal process is integrated into Cu/porous low-k interconnects. In order to solve these issues, etch-byproduct in-situ deposited on the sidewall and ALD-Ta is proposed. The etch-byproduct successfully prevented Ta penetration into the porous low-k film without increase process steps. ALD-Ta film of 0.8 nm, deposited by exposures of pentakisdimethylaminotantalium (PDMAT) and He/H/sub 2/ plasma to the substrate in turn, demonstrated strong adhesion layer as same as the conventional PVD barrier. Via yield of single-damascene Cu/porous low-k interconnects with the etch-byproduct was improved by substituting ALD-Ta for ALD-TaN.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115408766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345725
A. Naeemi, J. Meindl
For the first time, the average energy dissipation per input/output bits is estimated, which is very useful in determining an upper bound for chip aggregate I/O bandwidth for a given dynamic power budget. Some empirical parameters such as Rent's parameters and activity factor are used to capture the impact of chip architecture. For a projected multiprocessor implemented at the 45 nm technology node it is shown that 30 Tb/s is the maximum aggregate I/O bandwidth for 100W dynamic power dissipation.
{"title":"An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by power dissipation","authors":"A. Naeemi, J. Meindl","doi":"10.1109/IITC.2004.1345725","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345725","url":null,"abstract":"For the first time, the average energy dissipation per input/output bits is estimated, which is very useful in determining an upper bound for chip aggregate I/O bandwidth for a given dynamic power budget. Some empirical parameters such as Rent's parameters and activity factor are used to capture the impact of chip architecture. For a projected multiprocessor implemented at the 45 nm technology node it is shown that 30 Tb/s is the maximum aggregate I/O bandwidth for 100W dynamic power dissipation.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114871466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345741
B. White, G. Book, J. Hautala, M. Tabat
Integration of porous low-k materials for interconnect technology at the 45nm node presents many challenges to etch, ash and cleans processes. Dry processing with a gas cluster ion beam (GCIB) employs a highly energetic beam of loosely bound atomic or molecular clusters. We will show the ability of GCIB to pore seal, etch and ash p-MSQ features, while minimizing low-k film damage as compared to traditional plasma processes.
{"title":"Ultra low-k integration solutions using GCIB processing","authors":"B. White, G. Book, J. Hautala, M. Tabat","doi":"10.1109/IITC.2004.1345741","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345741","url":null,"abstract":"Integration of porous low-k materials for interconnect technology at the 45nm node presents many challenges to etch, ash and cleans processes. Dry processing with a gas cluster ion beam (GCIB) employs a highly energetic beam of loosely bound atomic or molecular clusters. We will show the ability of GCIB to pore seal, etch and ash p-MSQ features, while minimizing low-k film damage as compared to traditional plasma processes.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123419324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345717
Y. Xiang, T. Tsui, J. Vlassak, A. Mckerrow
The mechanical properties of organosilicate glass (OSG) thin films were measured for the first time using bulge testing of OSG / silicon nitride (SiN/sub x/) freestanding membranes. Evaluation of two different OSG films revealed significant differences in Young's modulus and residual stress between the two dielectric films. Young's modulus of both types of OSGs was independently measured using nanoindentation and found to be at least 8.5-17% greater than that measured using the bulge test. It is well known, and demonstrated herein, that modulus data obtained from nanoindentation is influenced by mechanical properties of the substrate. Operating without this constraint, it is believed that data obtained using the bulge test more accurately represents the intrinsic mechanical properties of OSG thin films.
{"title":"Measuring the elastic modulus and ultimate strength of low-k dielectric materials by means of the bulge test","authors":"Y. Xiang, T. Tsui, J. Vlassak, A. Mckerrow","doi":"10.1109/IITC.2004.1345717","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345717","url":null,"abstract":"The mechanical properties of organosilicate glass (OSG) thin films were measured for the first time using bulge testing of OSG / silicon nitride (SiN/sub x/) freestanding membranes. Evaluation of two different OSG films revealed significant differences in Young's modulus and residual stress between the two dielectric films. Young's modulus of both types of OSGs was independently measured using nanoindentation and found to be at least 8.5-17% greater than that measured using the bulge test. It is well known, and demonstrated herein, that modulus data obtained from nanoindentation is influenced by mechanical properties of the substrate. Operating without this constraint, it is believed that data obtained using the bulge test more accurately represents the intrinsic mechanical properties of OSG thin films.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126003285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345675
E. Kondoh, M. Hishikawa, M. Yanagihara, K. Shigama
Metallization in supercritical CO/sub 2/ (scCO/sub 2/) is a method to form nano-interconnects for future generation LSIs. It has been recognized that metal layers, Cu for instance, grow only on conductive layers thus requires an underlayer or 'activation' treatment to promote nucleation. Such a layer is formed by a conventional way, which may limit the potential of scCO/sub 2/ deposition. The keys to solve this issues are: 1) to develop a way to deposit a conductive barrier layer, and 2) to develop a proper chemistry to deposit the barrier layer directly on dielectric/nonconductive layers from scCO/sub 2/. The focus of this work is to form Cu/barrier stacks on dielectric layers using only scCO/sub 2/.
{"title":"Direct deposition of Cu/barrier stacks on dielectric/nonconductive layers using supercritical CO/sub 2/","authors":"E. Kondoh, M. Hishikawa, M. Yanagihara, K. Shigama","doi":"10.1109/IITC.2004.1345675","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345675","url":null,"abstract":"Metallization in supercritical CO/sub 2/ (scCO/sub 2/) is a method to form nano-interconnects for future generation LSIs. It has been recognized that metal layers, Cu for instance, grow only on conductive layers thus requires an underlayer or 'activation' treatment to promote nucleation. Such a layer is formed by a conventional way, which may limit the potential of scCO/sub 2/ deposition. The keys to solve this issues are: 1) to develop a way to deposit a conductive barrier layer, and 2) to develop a proper chemistry to deposit the barrier layer directly on dielectric/nonconductive layers from scCO/sub 2/. The focus of this work is to form Cu/barrier stacks on dielectric layers using only scCO/sub 2/.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126426441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345699
X. Liu, T. Shaw, M. Lane, R. Rosenberg, S. Lane, J. Doyle, D. Restaino, S. Vogt, D.C. Edelstaeing
This paper considers cracking of a low-k tensile film fabricated on top of a patterned multilayer. A finite element model has been established to study all the geometry effects of the top film and underlying layers. It is found that the driving force for film cracking, as calculated from the energy release rate, is greatly enhanced by the underlying layers of copper and low-k materials. The geometry dependence has been verified by a test structure. The results indicate that a low-k film that is intact when deposited on silicon may crack when integrated in a multilayer BEOL. IBM has successfully engineered a CVD SiCOH low-k film with reduced film stress and increased modulus without degrading the cohesive strength (or the dielectric constant). Accordingly, cracking of the film has been prevented even for the worst case interconnect structures.
{"title":"Channel cracking in low-k films on patterned multi-layers","authors":"X. Liu, T. Shaw, M. Lane, R. Rosenberg, S. Lane, J. Doyle, D. Restaino, S. Vogt, D.C. Edelstaeing","doi":"10.1109/IITC.2004.1345699","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345699","url":null,"abstract":"This paper considers cracking of a low-k tensile film fabricated on top of a patterned multilayer. A finite element model has been established to study all the geometry effects of the top film and underlying layers. It is found that the driving force for film cracking, as calculated from the energy release rate, is greatly enhanced by the underlying layers of copper and low-k materials. The geometry dependence has been verified by a test structure. The results indicate that a low-k film that is intact when deposited on silicon may crack when integrated in a multilayer BEOL. IBM has successfully engineered a CVD SiCOH low-k film with reduced film stress and increased modulus without degrading the cohesive strength (or the dielectric constant). Accordingly, cracking of the film has been prevented even for the worst case interconnect structures.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127004745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345748
M. Fayolle, V. Jousseaume, M. Assous, E. Tabouret, C. Le Cornec, P. Haumesser, P. Leduc, H. Feldis, O. Louveau, G. Passemard, F. Fusalba
This paper is focused on a new integration scheme to perform Cu/porous ULK interconnects. The dielectric (composite material made of porogen nano-particles dispersed in a MSQ matrix) is integrated in its non-porous state, preventing integration issues inherent in porous material. The porosity is only created after integration by a final thermal degradation of the porogen phase. Material, curing and processes compatibilities have been studied in order to perform single damascene interconnects. Electrical results prove the feasibility of this approach, showing that the porogen can be preserved during the integration and removed after the integration.
{"title":"Cu/ULK integration using a post integration porogen removal approach","authors":"M. Fayolle, V. Jousseaume, M. Assous, E. Tabouret, C. Le Cornec, P. Haumesser, P. Leduc, H. Feldis, O. Louveau, G. Passemard, F. Fusalba","doi":"10.1109/IITC.2004.1345748","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345748","url":null,"abstract":"This paper is focused on a new integration scheme to perform Cu/porous ULK interconnects. The dielectric (composite material made of porogen nano-particles dispersed in a MSQ matrix) is integrated in its non-porous state, preventing integration issues inherent in porous material. The porosity is only created after integration by a final thermal degradation of the porogen phase. Material, curing and processes compatibilities have been studied in order to perform single damascene interconnects. Electrical results prove the feasibility of this approach, showing that the porogen can be preserved during the integration and removed after the integration.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132587760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345672
C. Yao, T.C. Huang, K. Chi, W. K. Wan, H.H. Lin, C. Hsia, M. Liang
Modelling methodologies including a dynamic stress evolution are proposed in this work to characterize the relative stress-induced voiding (SIV) probability inside via of various Cu/low k interconnects. Seven patterns being representative of versatile IC design units are selected. It is demonstrated that our modelling approach can serve as a good method identifying the most troublesome layout units to inside-via SIV, and the results aligned well with the experimental data. From our studies, two kinds of layout styles when designed together are found detrimental: (1) the layout units with via(s) subjected to significant upper-metal edge confinement and (2) the one with via close to big vacancy sources.
{"title":"Numerical characterization of the stress induced voiding inside via of various Cu/low k interconnects","authors":"C. Yao, T.C. Huang, K. Chi, W. K. Wan, H.H. Lin, C. Hsia, M. Liang","doi":"10.1109/IITC.2004.1345672","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345672","url":null,"abstract":"Modelling methodologies including a dynamic stress evolution are proposed in this work to characterize the relative stress-induced voiding (SIV) probability inside via of various Cu/low k interconnects. Seven patterns being representative of versatile IC design units are selected. It is demonstrated that our modelling approach can serve as a good method identifying the most troublesome layout units to inside-via SIV, and the results aligned well with the experimental data. From our studies, two kinds of layout styles when designed together are found detrimental: (1) the layout units with via(s) subjected to significant upper-metal edge confinement and (2) the one with via close to big vacancy sources.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134304651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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