Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345676
T. Saito, H. Ashihara, K. Ishikawa, Y. Miyauchi, Y. Yamada, S. Uno, M. Kubo, J. Noguchi, T. Oshima, H. Aoki
A high reliable copper interconnects with metallic cap is studied. W-CVD process combined with pre-cleaning succeeded in self-aligned metal deposition on Cu interconnects surface. Degradation of leakage current between adjacent Cu wires is suppressed by process optimization. Reliability characteristics such as electromigration and stress-migration of metal capped Cu interconnect structure are investigated and are superior to those of conventional one. These results reveal that Cu and vacancy diffusion at the Cu wire surface is successfully suppressed by eliminating Cu/dielectric interface.
{"title":"A robust, deep-submicron copper interconnect structure using self-aligned metal capping method","authors":"T. Saito, H. Ashihara, K. Ishikawa, Y. Miyauchi, Y. Yamada, S. Uno, M. Kubo, J. Noguchi, T. Oshima, H. Aoki","doi":"10.1109/IITC.2004.1345676","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345676","url":null,"abstract":"A high reliable copper interconnects with metallic cap is studied. W-CVD process combined with pre-cleaning succeeded in self-aligned metal deposition on Cu interconnects surface. Degradation of leakage current between adjacent Cu wires is suppressed by process optimization. Reliability characteristics such as electromigration and stress-migration of metal capped Cu interconnect structure are investigated and are superior to those of conventional one. These results reveal that Cu and vacancy diffusion at the Cu wire surface is successfully suppressed by eliminating Cu/dielectric interface.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116210385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345697
T. Suzuki, Akira Uedono, Tomoji Nakamura, Y. Mizushima, H. Kitada, Y. Koura
Vacant defects in electroplated Cu films are investigated by positron annihilation and high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM). The evolution of vacancies was divided into two regions with respect to the annealing temperature. For temperature below 300/spl deg/C, the behavior of vacancies was closely related to grain growth. When the annealing temperature was over 300/spl deg/C, the vacancy concentration was estimated to be of the order of 10/sup 19/ /spl sim/10/sup 20//cm/sup 3/, which is similar to void volume estimates in stress induced voiding (SIV) failure.
{"title":"Direct observation of vacancy defects in electroplated Cu films","authors":"T. Suzuki, Akira Uedono, Tomoji Nakamura, Y. Mizushima, H. Kitada, Y. Koura","doi":"10.1109/IITC.2004.1345697","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345697","url":null,"abstract":"Vacant defects in electroplated Cu films are investigated by positron annihilation and high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM). The evolution of vacancies was divided into two regions with respect to the annealing temperature. For temperature below 300/spl deg/C, the behavior of vacancies was closely related to grain growth. When the annealing temperature was over 300/spl deg/C, the vacancy concentration was estimated to be of the order of 10/sup 19/ /spl sim/10/sup 20//cm/sup 3/, which is similar to void volume estimates in stress induced voiding (SIV) failure.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127338801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345750
D. Edelstein, C. Davis, L. Clevenger, M. Yoon, A. Cowley, T. Nogami, H. Rathore, B. Agarwala, S. Arai, A. Carbone, K. Chanda, S. Cohen, W. Cote, M. Cullinan, T. Dalton, S. Das, P. Davis, J. Demarest, D. Dunn, C. Dziobkowski, R. Filippi, J. Fitzsimmons, P. Flaitz, S. Gates, J. Gill, A. Grill, D. Hawken, K. Ida, D. Klaus, N. Klymko, M. Lane, S. Lane, J. Lee, W. Landers, W.-K. Li, Y. Lin, E. Liniger, X. Liu, A. Madan, S. Malhotra, J. Martin, S. Molis, C. Muzzy, D. Nguyen, S. Nguyen, M. Ono, C. Parks, D. Questad, D. Restaino, A. Sakamoto, T. Shaw, Y. Shimooka, A. Simon, E. Simonyi, S. Tempest, T. Van Kleeck, S. Vogt, Y. Wang, W. Wille, J. Wright, C. Yang, T. Ivers
We report a comprehensive characterization of a 90 nm CMOS technology with Cu/SiCOH low-k interconnect BEOL. Significant material and integration engineering have led to the highest reliability, without degrading the performance expected from low-k. Results are presented on every aspect of BEOL and chip-package reliability, yields, low-k film parameters, BEOL capacitances and circuit delays on functional chips. All results meet or exceed our concurrent 90 nm Cu/FTEOS technology, and support extendibility to 65 nm.
{"title":"Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology","authors":"D. Edelstein, C. Davis, L. Clevenger, M. Yoon, A. Cowley, T. Nogami, H. Rathore, B. Agarwala, S. Arai, A. Carbone, K. Chanda, S. Cohen, W. Cote, M. Cullinan, T. Dalton, S. Das, P. Davis, J. Demarest, D. Dunn, C. Dziobkowski, R. Filippi, J. Fitzsimmons, P. Flaitz, S. Gates, J. Gill, A. Grill, D. Hawken, K. Ida, D. Klaus, N. Klymko, M. Lane, S. Lane, J. Lee, W. Landers, W.-K. Li, Y. Lin, E. Liniger, X. Liu, A. Madan, S. Malhotra, J. Martin, S. Molis, C. Muzzy, D. Nguyen, S. Nguyen, M. Ono, C. Parks, D. Questad, D. Restaino, A. Sakamoto, T. Shaw, Y. Shimooka, A. Simon, E. Simonyi, S. Tempest, T. Van Kleeck, S. Vogt, Y. Wang, W. Wille, J. Wright, C. Yang, T. Ivers","doi":"10.1109/IITC.2004.1345750","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345750","url":null,"abstract":"We report a comprehensive characterization of a 90 nm CMOS technology with Cu/SiCOH low-k interconnect BEOL. Significant material and integration engineering have led to the highest reliability, without degrading the performance expected from low-k. Results are presented on every aspect of BEOL and chip-package reliability, yields, low-k film parameters, BEOL capacitances and circuit delays on functional chips. All results meet or exceed our concurrent 90 nm Cu/FTEOS technology, and support extendibility to 65 nm.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"41 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123474825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345684
S. Parikh, M. Naik, R. Hung, H. Dai, D. Padhi, L. Zhang, T. Pan, Kuo-Wei Liu, G. Dixit, M. Armacost
The paper addresses critical issues associated with 90 and 65 nm copper low k interconnects. A stable baseline with >98% yield on 1E7via and 5m long serpent was established. Electromigration (EM) and IV breakdown performance was improved by optimizing the post CMP Cu pre-treatment and the dielectric barrier obtaining EM T/sub 0.1/ lifetime of greater than 10 yrs at 1.5 MA/cm/sup 2/ and >6MV/cm IV breakdown field. Detailed characterization of the impact of the barrier process on stress migration (SM) is presented. Extendibility of the process flow to sub-90nm interconnects and advanced dielectric (k<2.7) is shown.
{"title":"300mm copper low-k integration and reliability for 90 and 65 nm nodes","authors":"S. Parikh, M. Naik, R. Hung, H. Dai, D. Padhi, L. Zhang, T. Pan, Kuo-Wei Liu, G. Dixit, M. Armacost","doi":"10.1109/IITC.2004.1345684","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345684","url":null,"abstract":"The paper addresses critical issues associated with 90 and 65 nm copper low k interconnects. A stable baseline with >98% yield on 1E7via and 5m long serpent was established. Electromigration (EM) and IV breakdown performance was improved by optimizing the post CMP Cu pre-treatment and the dielectric barrier obtaining EM T/sub 0.1/ lifetime of greater than 10 yrs at 1.5 MA/cm/sup 2/ and >6MV/cm IV breakdown field. Detailed characterization of the impact of the barrier process on stress migration (SM) is presented. Extendibility of the process flow to sub-90nm interconnects and advanced dielectric (k<2.7) is shown.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127815595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345756
N. Nakamura, T. Yoshizawa, T. Watanabe, H. Miyajima, S. Nakao, N. Yamada, K. Fujita, N. Matsunaga, H. Shibata
A plasma damage resistant hybrid (polyarylene ether (PAR)/SiOC) dielectric structure using the ultra low-k (ULK) films with k value of 2.2 was demonstrated for Cu dual-damascene (DD) interconnects. The reliability issues attributed to plasma process induced damage to ULK films were clarified and resolved. As well as ULK film selection with plasma damage resistance, insertion of a low-k buffer layer with k value of 3.0 between SiOC and PAE and damage restoration process using hydrophobic treatment were found to be most important factors for robust ULK process integration.
{"title":"A plasma damage resistant ultra low-k hybrid dielectric structure for 45nm node copper dual-damascene interconnects","authors":"N. Nakamura, T. Yoshizawa, T. Watanabe, H. Miyajima, S. Nakao, N. Yamada, K. Fujita, N. Matsunaga, H. Shibata","doi":"10.1109/IITC.2004.1345756","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345756","url":null,"abstract":"A plasma damage resistant hybrid (polyarylene ether (PAR)/SiOC) dielectric structure using the ultra low-k (ULK) films with k value of 2.2 was demonstrated for Cu dual-damascene (DD) interconnects. The reliability issues attributed to plasma process induced damage to ULK films were clarified and resolved. As well as ULK film selection with plasma damage resistance, insertion of a low-k buffer layer with k value of 3.0 between SiOC and PAE and damage restoration process using hydrophobic treatment were found to be most important factors for robust ULK process integration.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125779301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345753
K. Char, B. Cha, Suhan Kim
Using the molecularly designed porogen (pore generating agent) approach, novel nanoporous low-k materials with improved mechanical properties have been achieved based on poly(methylsilsesquioxane), PMSSQ, structure. Two different methods, microphase separation system and grafted porogen system, were adopted to realize nonporous ultra low-k dielectrics with superior mechanical properties. We found that the behavior of dielectric constant as well as thin film modulus depends on the molecular structure of a porogen. Within the decomposition temperature windows of grafted porogens, a low-k material with k < 2.2 and Young's modulus > 6 Gpa was achieved. These results indicate that it is possible to design and fabricate nanoporous thin films with balanced low dielectric constant and robust mechanical properties, which are highly desired for microelectronic industry.
{"title":"Material issues for nanoporous ultra low-k dielectrics","authors":"K. Char, B. Cha, Suhan Kim","doi":"10.1109/IITC.2004.1345753","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345753","url":null,"abstract":"Using the molecularly designed porogen (pore generating agent) approach, novel nanoporous low-k materials with improved mechanical properties have been achieved based on poly(methylsilsesquioxane), PMSSQ, structure. Two different methods, microphase separation system and grafted porogen system, were adopted to realize nonporous ultra low-k dielectrics with superior mechanical properties. We found that the behavior of dielectric constant as well as thin film modulus depends on the molecular structure of a porogen. Within the decomposition temperature windows of grafted porogens, a low-k material with k < 2.2 and Young's modulus > 6 Gpa was achieved. These results indicate that it is possible to design and fabricate nanoporous thin films with balanced low dielectric constant and robust mechanical properties, which are highly desired for microelectronic industry.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"2 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113954747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have found that Cu-line walls located along the peripheral of the test chips improve lifetime in chip-level electromigration (EM) test and time-dependent dielectric breakdown (TDDB) test for Cu/porous-methyl-silsesquioxane (MSQ) structure. After EM test at elevated temperatures, Cu loss and extrusion are greatly suppressed in the samples with the walls. They seem to be promoted by any reactants such as moisture or oxidant penetrated from the surface on the chip side and to cause short EM lifetime. Therefore, the above layout is effective and essential in future Cu/low-k integrity.
{"title":"Suppression of Cu extrusion into porous-MSQ film during chip-reliability test","authors":"Hiroshi, Satoshi Kageyama, Shigeydu Katayama, Naofumi Ohashi, Yoshihisa Matsubara, Nobuyoshi Kobayashi","doi":"10.1109/IITC.2004.1345673","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345673","url":null,"abstract":"We have found that Cu-line walls located along the peripheral of the test chips improve lifetime in chip-level electromigration (EM) test and time-dependent dielectric breakdown (TDDB) test for Cu/porous-methyl-silsesquioxane (MSQ) structure. After EM test at elevated temperatures, Cu loss and extrusion are greatly suppressed in the samples with the walls. They seem to be promoted by any reactants such as moisture or oxidant penetrated from the surface on the chip side and to cause short EM lifetime. Therefore, the above layout is effective and essential in future Cu/low-k integrity.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130461826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345685
S. Lee, T. Yoshie, Y. Sudo, E. Soda, K. Yoneda, B. Yoon, H. Kabayashi, S. Kageyama, K. Misawa, S. Kondo, T. Nasuno, Y. Matsubara, N. Ohashi, N. Kobayashi
This work proposes a use of PECVD low-k carbon-doped SiO2 (SiOC) as a cap layer for 200nm pitch Cu interconnects using high-modulus porous MSQ (k=2.3) to reduce the low-k void formation and the effective dielectric constant (keff). The mechanism of void suppression is due to the high permeability of SiOC film for fluorine (F), which is incorporated I p-MSQ during damascene etching. The elimination of voids by application of SiOC cap layer is confirmed by FIB analysis as well as the electrical characteristics. The keff value of 200nm pitch Cu/p-MSQ interconnects is reduced using SiOC cap layer, which is in good agreement with the calculation. Thus, this process is promising for the reliable porous ultra low-k for the 65nm node and beyond.
{"title":"PECVD low-k SiOC (k=2.8) as a cap layer for 200nm pitch Cu interconnect using porous low-k dielectrics (k=2.3)","authors":"S. Lee, T. Yoshie, Y. Sudo, E. Soda, K. Yoneda, B. Yoon, H. Kabayashi, S. Kageyama, K. Misawa, S. Kondo, T. Nasuno, Y. Matsubara, N. Ohashi, N. Kobayashi","doi":"10.1109/IITC.2004.1345685","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345685","url":null,"abstract":"This work proposes a use of PECVD low-k carbon-doped SiO2 (SiOC) as a cap layer for 200nm pitch Cu interconnects using high-modulus porous MSQ (k=2.3) to reduce the low-k void formation and the effective dielectric constant (keff). The mechanism of void suppression is due to the high permeability of SiOC film for fluorine (F), which is incorporated I p-MSQ during damascene etching. The elimination of voids by application of SiOC cap layer is confirmed by FIB analysis as well as the electrical characteristics. The keff value of 200nm pitch Cu/p-MSQ interconnects is reduced using SiOC cap layer, which is in good agreement with the calculation. Thus, this process is promising for the reliable porous ultra low-k for the 65nm node and beyond.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127075020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345705
J. Balachandran, S. Brebels, G. Carchon, T. Webers, W. De Raedt, B. Nauwelaers, E. Beyne
Wafer level package (WLP) redistribution layer interconnects can be effectively used for countering on-die global wiring challenges. To demonstrate this, we fabricated WLP test chips with two configurations namely IMPS and microstrip transmission lines in WLP layers. Experimental results indicate superior electrical performance. Near speed of light propagation is observed with insignificant signal distortion. We compare the WLP layers interconnect performance with a representative 70nm node upsized global interconnect. Details on the WLP technology are also provided.
{"title":"Extending on-die wiring hierarchy with wafer level packaging concepts","authors":"J. Balachandran, S. Brebels, G. Carchon, T. Webers, W. De Raedt, B. Nauwelaers, E. Beyne","doi":"10.1109/IITC.2004.1345705","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345705","url":null,"abstract":"Wafer level package (WLP) redistribution layer interconnects can be effectively used for countering on-die global wiring challenges. To demonstrate this, we fabricated WLP test chips with two configurations namely IMPS and microstrip transmission lines in WLP layers. Experimental results indicate superior electrical performance. Near speed of light propagation is observed with insignificant signal distortion. We compare the WLP layers interconnect performance with a representative 70nm node upsized global interconnect. Details on the WLP technology are also provided.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345679
S. Brongersma, K. Vanstreels, W. Wu, W. Zhang, D. Ernur, J. D’Haen, V. Terzieva, M. Van Hove, T. Clarysse, L. Carbonell, W. Vandervorst, W. De Ceuninck, K. Maex
Electromigration in copper damascene interconnects is usually associated with interfacial diffusion at the copper/ dielectric barrier interface. In this study, we demonstrate how impurity and microstructural properties of the bulk copper can influence failures at the copper/dielectric barrier interface. Impurity concentrations in the bulk copper were modulated by varying electroplating conditions and the resulting effects on the copper microstructure and electromigration performances were investigated. A higher impurity concentration in the copper was found to increase the formation of microvoids during anneal and reduced the anneal rate which retarded the formation of large grains in the plated films. Both of these effects result in reduced electromigration lifetime with higher impurity level.
{"title":"Influence of copper purity on microstructure and electromigration","authors":"S. Brongersma, K. Vanstreels, W. Wu, W. Zhang, D. Ernur, J. D’Haen, V. Terzieva, M. Van Hove, T. Clarysse, L. Carbonell, W. Vandervorst, W. De Ceuninck, K. Maex","doi":"10.1109/IITC.2004.1345679","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345679","url":null,"abstract":"Electromigration in copper damascene interconnects is usually associated with interfacial diffusion at the copper/ dielectric barrier interface. In this study, we demonstrate how impurity and microstructural properties of the bulk copper can influence failures at the copper/dielectric barrier interface. Impurity concentrations in the bulk copper were modulated by varying electroplating conditions and the resulting effects on the copper microstructure and electromigration performances were investigated. A higher impurity concentration in the copper was found to increase the formation of microvoids during anneal and reduced the anneal rate which retarded the formation of large grains in the plated films. Both of these effects result in reduced electromigration lifetime with higher impurity level.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134175382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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