Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345746
V. Arnal, R. Hoofman, M. Assous, P. Bancken, M. Brokaart, P. Brun, N. Casanova, L. Chapelon, T. Chevolleau, C. Cowache, R. Daamen, A. Farcy, M. Fayolle, H. Feldis, Y. Furukawa, C. Goldberg, L. Gosset, C. Guedj, K. Haxaire, O. Hinsinger, E. Josse, S. Jullian, O. Louveau, J. Michelon, N. Possémé, M. Rivoire, A. Roman, T. Vandeweyer, J. Verheijden, J. Torres
Dual damascene integration of porous CVD SiOC low-k material was performed for interconnects of the 65 and 45 nm technology nodes. Deposition processes with dielectric constant of 2.4 and 2.2 were developed and characterized. Low-k integration was performed with feature sizes down to 85 nm. Etch and strip processes compatible with this ultra low-k investigated and lead to the successful dual damascene integration, illustrated by physical and electrical results such as low leakage current, via chain and line resistances. The k-value after integration was preserved at its initial value.
{"title":"Process optimisation and dual damascene integration of porous CVD SiOC dielectric at 2.4 and 2.2 k-values for 45 nm CMOS technology","authors":"V. Arnal, R. Hoofman, M. Assous, P. Bancken, M. Brokaart, P. Brun, N. Casanova, L. Chapelon, T. Chevolleau, C. Cowache, R. Daamen, A. Farcy, M. Fayolle, H. Feldis, Y. Furukawa, C. Goldberg, L. Gosset, C. Guedj, K. Haxaire, O. Hinsinger, E. Josse, S. Jullian, O. Louveau, J. Michelon, N. Possémé, M. Rivoire, A. Roman, T. Vandeweyer, J. Verheijden, J. Torres","doi":"10.1109/IITC.2004.1345746","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345746","url":null,"abstract":"Dual damascene integration of porous CVD SiOC low-k material was performed for interconnects of the 65 and 45 nm technology nodes. Deposition processes with dielectric constant of 2.4 and 2.2 were developed and characterized. Low-k integration was performed with feature sizes down to 85 nm. Etch and strip processes compatible with this ultra low-k investigated and lead to the successful dual damascene integration, illustrated by physical and electrical results such as low leakage current, via chain and line resistances. The k-value after integration was preserved at its initial value.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123864257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345665
Jong Won Hong, K. Choi, You Kyoung Lee, Sung Gun Park, Sang woo Lee, Jong Myeong Lee, S. Kang, G. Choi, Sung Tae Kim, U. Chung, J. Moon
PAALD (plasma assisted atomic layer deposition)-TaN thin films derived from a precursor, tert-amylimidotrisdim-ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were developed and compared to the thermal ALD-TaN. The deposition rate of the PAALD-TaN process was around /spl sim/0.9 /spl Aring//cycle at 250 /spl deg/C. The resistivity of TaN film by the PAALD was /spl sim/ 366 /spl mu/ohm-cm, while the resistivity by the thermal ALD was not measurable. The PAALD-TaN and thermal ALD-TaN film appeared to have cubic and amorphous phase, respectively. In Cu metallization, as TaN thickness increased, via resistance with thermal ALD-TaN increased dramatically, but via resistance with PAALD-TaN was almost constant and much lower than that with thermal ALD-TaN. Using PAALD-TaN, the diffusion barrier characteristics was also improved in comparison to thermal ALD-TaN.
{"title":"Characteristics of PAALD-TaN thin films derived from TAIMATA precursor for copper metallization","authors":"Jong Won Hong, K. Choi, You Kyoung Lee, Sung Gun Park, Sang woo Lee, Jong Myeong Lee, S. Kang, G. Choi, Sung Tae Kim, U. Chung, J. Moon","doi":"10.1109/IITC.2004.1345665","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345665","url":null,"abstract":"PAALD (plasma assisted atomic layer deposition)-TaN thin films derived from a precursor, tert-amylimidotrisdim-ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were developed and compared to the thermal ALD-TaN. The deposition rate of the PAALD-TaN process was around /spl sim/0.9 /spl Aring//cycle at 250 /spl deg/C. The resistivity of TaN film by the PAALD was /spl sim/ 366 /spl mu/ohm-cm, while the resistivity by the thermal ALD was not measurable. The PAALD-TaN and thermal ALD-TaN film appeared to have cubic and amorphous phase, respectively. In Cu metallization, as TaN thickness increased, via resistance with thermal ALD-TaN increased dramatically, but via resistance with PAALD-TaN was almost constant and much lower than that with thermal ALD-TaN. Using PAALD-TaN, the diffusion barrier characteristics was also improved in comparison to thermal ALD-TaN.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121855369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345729
A. Mulé, R. Villalaz, T. Gaylord, J. Meindl
The fabrication and testing of two-material, air-clad, volume grating-in-the-waveguide optical interconnects are described. Avatrel 2190P photopolymer from Promerus, LLC, and Omnidex HRF600 photopolymer from Dupont are incorporated as the waveguide and grating materials, respectively. Waveguide/grating interconnects exhibiting waveguide propagation losses of a/sub wg/ = -(0.47-3) dB/cm and grating coupling coefficients a/sub g/ = 1.4-5.3 mm/sup -1/ are demonstrated.
{"title":"Two-material, air-clad, grating-in-the-waveguide optical interconnects","authors":"A. Mulé, R. Villalaz, T. Gaylord, J. Meindl","doi":"10.1109/IITC.2004.1345729","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345729","url":null,"abstract":"The fabrication and testing of two-material, air-clad, volume grating-in-the-waveguide optical interconnects are described. Avatrel 2190P photopolymer from Promerus, LLC, and Omnidex HRF600 photopolymer from Dupont are incorporated as the waveguide and grating materials, respectively. Waveguide/grating interconnects exhibiting waveguide propagation losses of a/sub wg/ = -(0.47-3) dB/cm and grating coupling coefficients a/sub g/ = 1.4-5.3 mm/sup -1/ are demonstrated.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122824602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345681
G. Steinlesberger, G. Schindler, M. Engelhardt, W. Steinhogl, M. Traving
The physical and technological limitations for aluminium interconnect technology in the deep sub-100 nm regime are investigated. Using a wet chemical process for hard mask trimming the fabrication of nano Al interconnects has been demonstrated. Based on first electrical measurements the electrical size effect of Al interconnects with critical dimensions far below 100 nm as well as the impact of side wall roughness are discussed.
{"title":"Aluminum nano interconnects","authors":"G. Steinlesberger, G. Schindler, M. Engelhardt, W. Steinhogl, M. Traving","doi":"10.1109/IITC.2004.1345681","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345681","url":null,"abstract":"The physical and technological limitations for aluminium interconnect technology in the deep sub-100 nm regime are investigated. Using a wet chemical process for hard mask trimming the fabrication of nano Al interconnects has been demonstrated. Based on first electrical measurements the electrical size effect of Al interconnects with critical dimensions far below 100 nm as well as the impact of side wall roughness are discussed.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130239518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345727
R. Sarvari, A. Naeemi, J. Meindl
Compact models are presented for the bit-rate limit of transmission lines using a general form of resistance that for the first time simultaneously considers dc resistance, skin effect, and surface scattering. A conventional approximation that is only valid for fast rising signals is also relaxed. In contrast to previous models, it is shown that the bit-rate limit of a transmission line is not independent of wire perimeter-to-length ratio or scale-invariant. It is also shown that the error of previous models is large (e.g. 80% for bit-rate limit equals reciprocal time of flight) if bit-rate limit is not considerably larger than the reciprocal time-of-flight.
{"title":"General compact model for bit-rate limit of electrical interconnects considering DC resistance, skin effect and surface scattering","authors":"R. Sarvari, A. Naeemi, J. Meindl","doi":"10.1109/IITC.2004.1345727","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345727","url":null,"abstract":"Compact models are presented for the bit-rate limit of transmission lines using a general form of resistance that for the first time simultaneously considers dc resistance, skin effect, and surface scattering. A conventional approximation that is only valid for fast rising signals is also relaxed. In contrast to previous models, it is shown that the bit-rate limit of a transmission line is not independent of wire perimeter-to-length ratio or scale-invariant. It is also shown that the error of previous models is large (e.g. 80% for bit-rate limit equals reciprocal time of flight) if bit-rate limit is not considerably larger than the reciprocal time-of-flight.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129746248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345735
H. Chang, Y.C. Lu, L.P. Li, B.T. Chen, K.C. Lin, S. Jeng, S. Jang, M. Liang
Cu/porous low-k (PLK) with k/spl les/2.5 is the current choice to 65nm and beyond BEOL interconnect technologies. However, critical concerns of the weak physical and chemical structures of PLK (k/spl les/2.5) films on their integration compatibilities, such as CMP defectivity and trench bottom/via smoothness, electrical performances, such as etching/ashing film damaging, and reliability performances, such as electromigration (EM), stress migration (SM) and time-dependent dielectric breakdown (TDDB), still challenge their application feasibility. A novel in-situ formed trench-porous (k=2.5) and via-dense (k=2.7) k=2.5/2.7 bilayer film design was proposed in this study to overcome these facing issues. Cu/PLK DD study results showed that CMP defectivity was /spl sim/4/spl times/ improved and trench bottom was smoothened with a k=2.5/2,7 bilayer PLK approach. Electrical performances using this approach also showed that film damaging from DD etching/ashing was reduced with the higher chemical resistance of the via in the bilayer. Reliability study results demonstrated that an /spl sim/ 2000/spl times/ better DD TDDB lifetime was achieved due to smooth trench bottoms. When changing from Cu/k=2.5 single layer to Cu/k=2.5/2.7 bilayer, SM and EM performances were not impacted. Moreover, with >405 improved hardness and film adhesion the bilayer PLK approach highlights a potential direction to improve Cu/k=2.5 PLK manufacturability in packaging. All these results indicate that this Cu/bilayer BEOL interconnection applicable for 65 nm and beyond generation CMOS technologies.
{"title":"Robust low-k film (k=2.1/spl sim/2.5) for 90/65 nm BEOL technology using bilayer film schemes","authors":"H. Chang, Y.C. Lu, L.P. Li, B.T. Chen, K.C. Lin, S. Jeng, S. Jang, M. Liang","doi":"10.1109/IITC.2004.1345735","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345735","url":null,"abstract":"Cu/porous low-k (PLK) with k/spl les/2.5 is the current choice to 65nm and beyond BEOL interconnect technologies. However, critical concerns of the weak physical and chemical structures of PLK (k/spl les/2.5) films on their integration compatibilities, such as CMP defectivity and trench bottom/via smoothness, electrical performances, such as etching/ashing film damaging, and reliability performances, such as electromigration (EM), stress migration (SM) and time-dependent dielectric breakdown (TDDB), still challenge their application feasibility. A novel in-situ formed trench-porous (k=2.5) and via-dense (k=2.7) k=2.5/2.7 bilayer film design was proposed in this study to overcome these facing issues. Cu/PLK DD study results showed that CMP defectivity was /spl sim/4/spl times/ improved and trench bottom was smoothened with a k=2.5/2,7 bilayer PLK approach. Electrical performances using this approach also showed that film damaging from DD etching/ashing was reduced with the higher chemical resistance of the via in the bilayer. Reliability study results demonstrated that an /spl sim/ 2000/spl times/ better DD TDDB lifetime was achieved due to smooth trench bottoms. When changing from Cu/k=2.5 single layer to Cu/k=2.5/2.7 bilayer, SM and EM performances were not impacted. Moreover, with >405 improved hardness and film adhesion the bilayer PLK approach highlights a potential direction to improve Cu/k=2.5 PLK manufacturability in packaging. All these results indicate that this Cu/bilayer BEOL interconnection applicable for 65 nm and beyond generation CMOS technologies.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116712241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345739
M. Baklanov, Q. Le, E. Kesters, F. Iacopi, J. van Aelst, H. Struyf, W. Boullart, Vanhaelemeersch, K. Maex
This presentation is an overview of clean/strip processing for low Cu/low-k technology. The paper starts with a brief analysis of dry etch processes that determine the issues in subsequent processes; in the case of porous low-k dielectrics, etch conditions must be carefully optimized to find an optimal balance between the polymer formation and plasma damage of low-k dielectrics. The presentation includes recent results related to dry and wet cleaning, plasma damage, and stability of low-k films. The wet cleaning of solutions using supercritical CO/sub 2/(SCCO/sub 2/)IPA/water mixtures and special surfactants will also be analyzed. Results obtained by different advanced techniques like FTIR, XPS, ellipsometric porosimetry (EP), energy filtered TEM (EFTEM), TOF SIMS etc have been used to characterize the residues, plasma damage and cleaning efficiency and they will be analyzed during the presentation.
{"title":"Challenges of clean/strip processing for Cu/low-k technology","authors":"M. Baklanov, Q. Le, E. Kesters, F. Iacopi, J. van Aelst, H. Struyf, W. Boullart, Vanhaelemeersch, K. Maex","doi":"10.1109/IITC.2004.1345739","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345739","url":null,"abstract":"This presentation is an overview of clean/strip processing for low Cu/low-k technology. The paper starts with a brief analysis of dry etch processes that determine the issues in subsequent processes; in the case of porous low-k dielectrics, etch conditions must be carefully optimized to find an optimal balance between the polymer formation and plasma damage of low-k dielectrics. The presentation includes recent results related to dry and wet cleaning, plasma damage, and stability of low-k films. The wet cleaning of solutions using supercritical CO/sub 2/(SCCO/sub 2/)IPA/water mixtures and special surfactants will also be analyzed. Results obtained by different advanced techniques like FTIR, XPS, ellipsometric porosimetry (EP), energy filtered TEM (EFTEM), TOF SIMS etc have been used to characterize the residues, plasma damage and cleaning efficiency and they will be analyzed during the presentation.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124113597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345755
Y. Hayashi, F. Itoh, Y. Harada, T. Takeuchi, M. Tada, M. Tagami, H. Ohtake, K. Hijioka, S. Saito, T. Onodera, D. Hara, K. Tokudome
A porous SiOCH film with k=2.3 is developed by a new concept PECVD, in which pore-involved molecules are piled up together to deposit a "molecular-pore stacked, SiOCH (MPS)" film. The pore size and the density of the film are controlled by designing the pore size and the steric-hindrance side-chains of the source molecules. A newly synthesized, 6-member ring-type, organo-siloxane with the side-chains of large steric-hindrance hydrocarbons realizes the MPS film with k=2.3. the basic feasibility of the MPS film is confirmed through the integration into Cu damascene interconnects. The MPS film is a strong candidate for the low-k, inter-metal-dielectrics in 45nm node, ASICs.
{"title":"Novel molecular-structure design for PECVD porous SiOCH films toward 45nm node, ASICs with k=2.3","authors":"Y. Hayashi, F. Itoh, Y. Harada, T. Takeuchi, M. Tada, M. Tagami, H. Ohtake, K. Hijioka, S. Saito, T. Onodera, D. Hara, K. Tokudome","doi":"10.1109/IITC.2004.1345755","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345755","url":null,"abstract":"A porous SiOCH film with k=2.3 is developed by a new concept PECVD, in which pore-involved molecules are piled up together to deposit a \"molecular-pore stacked, SiOCH (MPS)\" film. The pore size and the density of the film are controlled by designing the pore size and the steric-hindrance side-chains of the source molecules. A newly synthesized, 6-member ring-type, organo-siloxane with the side-chains of large steric-hindrance hydrocarbons realizes the MPS film with k=2.3. the basic feasibility of the MPS film is confirmed through the integration into Cu damascene interconnects. The MPS film is a strong candidate for the low-k, inter-metal-dielectrics in 45nm node, ASICs.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122272888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345664
K. Higashi, H. Yamaguchi, S. Omoto, A. Sakata, T. Katata, N. Matsunaga, H. Shibata
In this paper, we describe highly reliable barrier metal structure for 45nm-node (140nm pitch) high performance copper interconnects. Issues and solutions for utilizing TaN barrier metal by atomic-layer deposition (ALD) process, which is the key technology for scaling down the barrier metal thickness, on low-k ILD materials were investigated. PVD/ALD/PVD stacked barrier metal structure was proposed from the viewpoint of factors affecting reliability such as stress-induced voiding (SiV) and electromigration (EM) endurance, and realized lower wiring resistance than that is attainable with the conventional process. We distinguished the role of each PVD film, and suggest the optimal barrier metal structure to realize highly reliable Cu dual-damascene interconnects.
{"title":"Highly reliable PVD/ALD/PVD stacked barrier metal structure for 45-nm node copper dual-damascene interconnects","authors":"K. Higashi, H. Yamaguchi, S. Omoto, A. Sakata, T. Katata, N. Matsunaga, H. Shibata","doi":"10.1109/IITC.2004.1345664","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345664","url":null,"abstract":"In this paper, we describe highly reliable barrier metal structure for 45nm-node (140nm pitch) high performance copper interconnects. Issues and solutions for utilizing TaN barrier metal by atomic-layer deposition (ALD) process, which is the key technology for scaling down the barrier metal thickness, on low-k ILD materials were investigated. PVD/ALD/PVD stacked barrier metal structure was proposed from the viewpoint of factors affecting reliability such as stress-induced voiding (SiV) and electromigration (EM) endurance, and realized lower wiring resistance than that is attainable with the conventional process. We distinguished the role of each PVD film, and suggest the optimal barrier metal structure to realize highly reliable Cu dual-damascene interconnects.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129767006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345690
Hsien-Ming Lee, J.C. Lin, C.H. Peng, S. Pan, C.L. Huang, L.L. Su, C. Hsieh, W. Shue, M. Liang
Performance of Cu dual damascene interconnects with a full coverage ALD TaNx cap layer coating on the top surface of Cu line has been investigated. With deposition process that generates different ALD TaNx film properties on Cu and low-k dielectrics, 100% yield of line-to-line leakage can be achieved. ALD TaNx cap layer can improve electromigration lifetime by more than 3 times due to improvement of the interface between Cu and cap layer which actually suppress the Cu surface migration without degradation of stress migration performance. This work demonstrates that ALD TaNx cap layer can be successfully integrated with Cu/low-k (k/spl sim/2.5) metallization with potential5% reduction in RC delay as compared to conventional cap layer.
{"title":"High performance Cu interconnects capped with full-coverage ALD TaNx layer for Cu/low-k (k/spl sim/2.5) metallization","authors":"Hsien-Ming Lee, J.C. Lin, C.H. Peng, S. Pan, C.L. Huang, L.L. Su, C. Hsieh, W. Shue, M. Liang","doi":"10.1109/IITC.2004.1345690","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345690","url":null,"abstract":"Performance of Cu dual damascene interconnects with a full coverage ALD TaNx cap layer coating on the top surface of Cu line has been investigated. With deposition process that generates different ALD TaNx film properties on Cu and low-k dielectrics, 100% yield of line-to-line leakage can be achieved. ALD TaNx cap layer can improve electromigration lifetime by more than 3 times due to improvement of the interface between Cu and cap layer which actually suppress the Cu surface migration without degradation of stress migration performance. This work demonstrates that ALD TaNx cap layer can be successfully integrated with Cu/low-k (k/spl sim/2.5) metallization with potential5% reduction in RC delay as compared to conventional cap layer.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"140 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134162002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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