Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131219
Shuyan Zhao, Yao Wang, R. Kheirollahi, Yashraj Shanker, Jeremy Wartenberg, Dana Murphy, Hua Zhang, F. Lu
This paper presents a design methodology of modular medium-voltage direct current (MVDC) solid-state circuit breakers (SSCBs) based on scalable power electronics building block (PEBB) units. Regarding the PEBB, 1) isolated gate drive, 2) natural convection cooling and 3) voltage clamping circuit are introduced. There are three major contributions of this paper. First, the PEBB concept is proposed for MVDC SSCB design for the first time. Second, a novel hybrid MOV based voltage clamping circuit is proposed to increase PEBB voltage rating thence enhancing SSCB efficiency. Third, a PEBB parallel packaging method is proposed based on economic analysis of compromise between efficiency enhancement and cost. A symmetrical busbar layout is proposed to ensure parallel switches consistency. A 1.33kV/40A PEBB prototype is successfully implemented, which is experimentally validated by 40A/1hour continuous conduction test and 1.33kV/200A fault interruption test. A 1.33kV/400A power disk prototype is then implemented based on 10 paralleled PEBBs and symmetrical busbar connections. A 400A/1hour continuous dc conduction test is conducted to verify its state-of-the-art 99.98% steady state efficiency, which paves the way for the next generation of high efficiency ultrafast solid-state breakers for MVDC systems.
{"title":"Modular Scalable Power Electronics Building Block Based MVDC Solid State Circuit Breakers","authors":"Shuyan Zhao, Yao Wang, R. Kheirollahi, Yashraj Shanker, Jeremy Wartenberg, Dana Murphy, Hua Zhang, F. Lu","doi":"10.1109/APEC43580.2023.10131219","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131219","url":null,"abstract":"This paper presents a design methodology of modular medium-voltage direct current (MVDC) solid-state circuit breakers (SSCBs) based on scalable power electronics building block (PEBB) units. Regarding the PEBB, 1) isolated gate drive, 2) natural convection cooling and 3) voltage clamping circuit are introduced. There are three major contributions of this paper. First, the PEBB concept is proposed for MVDC SSCB design for the first time. Second, a novel hybrid MOV based voltage clamping circuit is proposed to increase PEBB voltage rating thence enhancing SSCB efficiency. Third, a PEBB parallel packaging method is proposed based on economic analysis of compromise between efficiency enhancement and cost. A symmetrical busbar layout is proposed to ensure parallel switches consistency. A 1.33kV/40A PEBB prototype is successfully implemented, which is experimentally validated by 40A/1hour continuous conduction test and 1.33kV/200A fault interruption test. A 1.33kV/400A power disk prototype is then implemented based on 10 paralleled PEBBs and symmetrical busbar connections. A 400A/1hour continuous dc conduction test is conducted to verify its state-of-the-art 99.98% steady state efficiency, which paves the way for the next generation of high efficiency ultrafast solid-state breakers for MVDC systems.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125697187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131497
Haoran Li, Diego Serrano, Shukai Wang, T. Guillod, Min Luo, Minjie Chen
This paper presents a transformer-based encoder-projector-decoder neural network architecture for modeling power magnetics B-H hysteresis loops. The transformer-based encoder-decoder network architecture maps a flux density excitation waveform (B) into the corresponding magnetic field strength (H) waveform. The predicted B-H loop can be used to estimate the core loss and support magnetics-in-circuit simulations. A projector is added between the transformer encoder and decoder to capture the impact of other inputs such as frequency, temperature, and dc bias. An example transformer neural network is designed, trained, and tested to prove the effectiveness of the proposed architecture.
{"title":"Predicting the B-H Loops of Power Magnetics with Transformer-based Encoder-Projector-Decoder Neural Network Architecture","authors":"Haoran Li, Diego Serrano, Shukai Wang, T. Guillod, Min Luo, Minjie Chen","doi":"10.1109/APEC43580.2023.10131497","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131497","url":null,"abstract":"This paper presents a transformer-based encoder-projector-decoder neural network architecture for modeling power magnetics B-H hysteresis loops. The transformer-based encoder-decoder network architecture maps a flux density excitation waveform (B) into the corresponding magnetic field strength (H) waveform. The predicted B-H loop can be used to estimate the core loss and support magnetics-in-circuit simulations. A projector is added between the transformer encoder and decoder to capture the impact of other inputs such as frequency, temperature, and dc bias. An example transformer neural network is designed, trained, and tested to prove the effectiveness of the proposed architecture.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126020130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131602
Zhehui Guo, Hui Li, P. Cheetham, Nagaraju Guvvala
In this paper, the partial discharge (PD) of a solid-dielectric-based coreless transformer applied in an isolated gate driver power supply for 10-kV SiC MOSFETs is experimentally evaluated under a high frequency, high dv/dt PWM voltage. A PD test platform is built with a 10-kV SiC power module to generate high frequency, high dv/dt PWM voltage. Different PD detection equipment, including the photomultiplier tube (PMT), ultra-high frequency (UHF) antenna and high frequency current transform-er (HFCT) are adopted to detect PD signals. Experimental results validated that the solid-dielectric-based coreless transformer achieves PD free at 100-kHz, up to 75-V/ns, 5-kV PWM voltage excitation. The PD results under high frequency, high dv/dt PWM voltage and 60- Hz ac voltage are also compared.
本文在高频、高dv/dt PWM电压下，实验评估了用于10 kv SiC mosfet隔离栅驱动电源的固体介质无铁芯变压器的局部放电(PD)。采用10kv SiC功率模块搭建PD测试平台，产生高频、高dv/dt PWM电压。采用光电倍增管(PMT)、超高频(UHF)天线和高频电流互感器(HFCT)等不同的PD检测设备检测PD信号。实验结果验证了基于固体介质的无铁芯变压器在100 khz、高达75 v /ns、5 kv PWM电压激励下实现了无局部放电。并比较了高频、高dv/dt PWM电压和60 Hz交流电压下的PD结果。
{"title":"Partial Discharge Characterization of Solid-Dielectric-Based Transformer Under High Frequency High dv/dt PWM Voltage for MV Applications","authors":"Zhehui Guo, Hui Li, P. Cheetham, Nagaraju Guvvala","doi":"10.1109/APEC43580.2023.10131602","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131602","url":null,"abstract":"In this paper, the partial discharge (PD) of a solid-dielectric-based coreless transformer applied in an isolated gate driver power supply for 10-kV SiC MOSFETs is experimentally evaluated under a high frequency, high dv/dt PWM voltage. A PD test platform is built with a 10-kV SiC power module to generate high frequency, high dv/dt PWM voltage. Different PD detection equipment, including the photomultiplier tube (PMT), ultra-high frequency (UHF) antenna and high frequency current transform-er (HFCT) are adopted to detect PD signals. Experimental results validated that the solid-dielectric-based coreless transformer achieves PD free at 100-kHz, up to 75-V/ns, 5-kV PWM voltage excitation. The PD results under high frequency, high dv/dt PWM voltage and 60- Hz ac voltage are also compared.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121963093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131624
Maida Farooq, K. Afridi
This paper presents a dynamic cancellation control strategy for the inversion stage of the recently proposed high-power-density common-neutral single-dc-bus (CN-SDB) single-phase online uninterruptible power supply (UPS). The inversion stage operates in buck or buck-boost mode depending on the polarity of the output voltage reference and produces a sinusoidal output voltage. Owing to the dual-mode nature of the inversion stage, output voltage regulation with standard feedback control results in a large dc-offset and poor total harmonic distortion (THD), which is unacceptable for practical applications. To substantially improve the output voltage dc-offset and THD, a dynamic cancellation control strategy is proposed for the buck-boost mode of the dual-mode inversion stage. An analytical model capturing the dynamics of the inversion stage with dynamic cancellation control strategy is also presented to facilitate the controller design. A 1-kVA GaN-based prototype of online UPS is designed, built, and tested, and the output voltage THD is experimentally measured across a wide output voltage range. Standard feedback control strategy results in a 10% output voltage THD whereas the dynamic cancellation control strategy offers a significant improvement of 68% and results in a 3.2% output voltage THD.
本文提出了一种针对大功率密度共中性单直流母线(CN-SDB)单相在线不间断电源(UPS)逆变级的动态对消控制策略。根据输出电压基准的极性，反转级以降压或降压升压模式工作，并产生正弦输出电压。由于逆变级的双模特性，采用标准反馈控制的输出电压调节会导致较大的直流偏置和较差的总谐波失真(THD)，这在实际应用中是不可接受的。为了大幅改善输出电压直流偏置和THD，针对双模反转级的降压升压模式，提出了一种动态对消控制策略。为了便于控制器的设计，还提出了一种利用动态抵消控制策略捕捉反转阶段动力学的解析模型。设计、构建并测试了基于1 kva gan的在线UPS样机，并在较宽的输出电压范围内实验测量了输出电压THD。标准反馈控制策略的输出电压THD为10%，而动态抵消控制策略的输出电压THD显著提高68%，输出电压THD为3.2%。
{"title":"Output Voltage Control via Dynamic Cancellation of a GaN-Based High-Power-Density Single-Phase Transformer-Less Online UPS","authors":"Maida Farooq, K. Afridi","doi":"10.1109/APEC43580.2023.10131624","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131624","url":null,"abstract":"This paper presents a dynamic cancellation control strategy for the inversion stage of the recently proposed high-power-density common-neutral single-dc-bus (CN-SDB) single-phase online uninterruptible power supply (UPS). The inversion stage operates in buck or buck-boost mode depending on the polarity of the output voltage reference and produces a sinusoidal output voltage. Owing to the dual-mode nature of the inversion stage, output voltage regulation with standard feedback control results in a large dc-offset and poor total harmonic distortion (THD), which is unacceptable for practical applications. To substantially improve the output voltage dc-offset and THD, a dynamic cancellation control strategy is proposed for the buck-boost mode of the dual-mode inversion stage. An analytical model capturing the dynamics of the inversion stage with dynamic cancellation control strategy is also presented to facilitate the controller design. A 1-kVA GaN-based prototype of online UPS is designed, built, and tested, and the output voltage THD is experimentally measured across a wide output voltage range. Standard feedback control strategy results in a 10% output voltage THD whereas the dynamic cancellation control strategy offers a significant improvement of 68% and results in a 3.2% output voltage THD.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127943493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131420
Bo Yao, Yichi Zhang, Pedro Correia, R. Wu, Sungyoung Song, I. Trintis, Haoran Wang, Huai Wang
This paper presents the degradation testing and failure mechanisms analysis of metalized film capacitors used for AC filtering in MW power converters. Based on more than 2,800 hours of accelerated testing under accelerated AC voltage, temperature, and AC current, various electro-thermal parameter data are recorded. The results reveal that capacitance values have negligible reduction until the testing samples catastrophically fail. The capacitor hot spot temperature and case temperature are measured along the testing, which are increasing. The observations provide a new perspective on the possible failure mechanisms and condition monitoring of film capacitors in AC filtering applications.
{"title":"Accelerated degradation testing and failure phenomenon of metalized film capacitors for AC filtering","authors":"Bo Yao, Yichi Zhang, Pedro Correia, R. Wu, Sungyoung Song, I. Trintis, Haoran Wang, Huai Wang","doi":"10.1109/APEC43580.2023.10131420","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131420","url":null,"abstract":"This paper presents the degradation testing and failure mechanisms analysis of metalized film capacitors used for AC filtering in MW power converters. Based on more than 2,800 hours of accelerated testing under accelerated AC voltage, temperature, and AC current, various electro-thermal parameter data are recorded. The results reveal that capacitance values have negligible reduction until the testing samples catastrophically fail. The capacitor hot spot temperature and case temperature are measured along the testing, which are increasing. The observations provide a new perspective on the possible failure mechanisms and condition monitoring of film capacitors in AC filtering applications.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121444481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131356
Yuchen He, Yuan Li, Bokang Zhou, Yuntao Zou, F. Peng
This paper proposes an ultra-fast inrush-current-free startup method for grid-tie inverters without voltage sensors and phase-locked loop (PLL). Traditionally, the grid-tie inverter needs the voltage measured from points of common couplings (PCC) to generate the phase angle via PLL for inverter pulse-width-modulation (PWM) signals. The startup procedure is slow and inrush current occurs if the initial PWM does not match the unknown grid voltage well. This paper proposes a startup method that only uses measured inverter ac currents to generate the initial PWM by controlling the current to zero. The generated PWM pattern can be used to reproduce the real grid voltage regardless of the grid impedance. The zero-crossing points of the grid voltage are detected and then used for grid synchronization. The proposed startup procedure only needs a few cycles (16.67 ms/cycle) to reliably synchronize the inverter to the grid without any inrush current. Simulation and experimental results are presented to verify the effectiveness of this control strategy.
{"title":"An Ultra-Fast Inrush-Current-Free Startup Method for Grid-tie Inverter without Voltage Sensors","authors":"Yuchen He, Yuan Li, Bokang Zhou, Yuntao Zou, F. Peng","doi":"10.1109/APEC43580.2023.10131356","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131356","url":null,"abstract":"This paper proposes an ultra-fast inrush-current-free startup method for grid-tie inverters without voltage sensors and phase-locked loop (PLL). Traditionally, the grid-tie inverter needs the voltage measured from points of common couplings (PCC) to generate the phase angle via PLL for inverter pulse-width-modulation (PWM) signals. The startup procedure is slow and inrush current occurs if the initial PWM does not match the unknown grid voltage well. This paper proposes a startup method that only uses measured inverter ac currents to generate the initial PWM by controlling the current to zero. The generated PWM pattern can be used to reproduce the real grid voltage regardless of the grid impedance. The zero-crossing points of the grid voltage are detected and then used for grid synchronization. The proposed startup procedure only needs a few cycles (16.67 ms/cycle) to reliably synchronize the inverter to the grid without any inrush current. Simulation and experimental results are presented to verify the effectiveness of this control strategy.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121727480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131640
Chuangchuang Lu, Weiyang Zhou, Ke-feng Jin
For most digital twin (DT) method, it is challenge to achieve high accuracy parameters identification due to the digital model is not a perfect replica of physical model. In this paper, a novel DT approach based on electrothermal model, which features more realistic than ideal model, is firstly proposed to obtain accurate parameters identification. By calculating the power loss of the proposed digital model, the temperature of self-heating devices in the digital model, such as MOSFETs, diodes and capacitors, can be obtained, so that the values of the temperature-dependent parameters in these devices can be updated, and hence more accurate results can be guaranteed. The proposed method is validated on a 500W buck converter and the experimental results show that the maximum estimated error of the on-state resistances of MOSFET is 0.6%, which is hundreds of times higher accuracy than conventional DT methods.
{"title":"Electrothermal Modeling Based Digital Twin Method for Degradation Parameters Identification of DC-DC Converter","authors":"Chuangchuang Lu, Weiyang Zhou, Ke-feng Jin","doi":"10.1109/APEC43580.2023.10131640","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131640","url":null,"abstract":"For most digital twin (DT) method, it is challenge to achieve high accuracy parameters identification due to the digital model is not a perfect replica of physical model. In this paper, a novel DT approach based on electrothermal model, which features more realistic than ideal model, is firstly proposed to obtain accurate parameters identification. By calculating the power loss of the proposed digital model, the temperature of self-heating devices in the digital model, such as MOSFETs, diodes and capacitors, can be obtained, so that the values of the temperature-dependent parameters in these devices can be updated, and hence more accurate results can be guaranteed. The proposed method is validated on a 500W buck converter and the experimental results show that the maximum estimated error of the on-state resistances of MOSFET is 0.6%, which is hundreds of times higher accuracy than conventional DT methods.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121744563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131669
Liqi Zhang, Zhicheng Guo, Soumik Sen, Chen Chen, A. Q. Huang
A 3.6kV/400A SiC half-bridge intelligent power module (IPM) is developed based on a novel series-parallel approach of lower voltage devices. Twenty-four 1200V SiC MOSFETs are integrated in the IPM together with a high isolation voltage gate power supply, gate driver and overcurrent protection. This paper proposes and analyzes the novel series-parallel approach which guarantees dynamic voltage sharing amount series connected devices and current sharing among paralleled branches. Experimental results are included to demonstrate the superior performance of the developed high power IPM.
基于新型低压器件串并联方法，研制了一种3.6kV/400A SiC半桥智能功率模块(IPM)。在IPM中集成了24个1200V SiC mosfet，以及高隔离电压栅极电源，栅极驱动器和过流保护。本文提出并分析了一种新的串并联方法，该方法既能保证串联器件的动态电压共享量，又能保证并联支路之间的电流共享。实验结果表明，所研制的高功率IPM具有优越的性能。
{"title":"A Novel Series-Parallel Design of The 3.6kV/400A SiC Austin SuperMOS","authors":"Liqi Zhang, Zhicheng Guo, Soumik Sen, Chen Chen, A. Q. Huang","doi":"10.1109/APEC43580.2023.10131669","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131669","url":null,"abstract":"A 3.6kV/400A SiC half-bridge intelligent power module (IPM) is developed based on a novel series-parallel approach of lower voltage devices. Twenty-four 1200V SiC MOSFETs are integrated in the IPM together with a high isolation voltage gate power supply, gate driver and overcurrent protection. This paper proposes and analyzes the novel series-parallel approach which guarantees dynamic voltage sharing amount series connected devices and current sharing among paralleled branches. Experimental results are included to demonstrate the superior performance of the developed high power IPM.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130152686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131499
Jeyeong Lim, Eui-Seong Han, Dong Hwan Kim, B. Lee
This paper proposes an optimal clustering algorithm considering performance deviation of parameters and data preprocessing method for reusing retired batteries. The proposed method regroups batteries by considering the density and performance deviation of the retired battery dataset through a clustering algorithm using density-based spatial clustering of applications with noise (DBSCAN). Additionally, the performance of the algorithm was improved through data preprocessing using a principal component analysis (PCA) that prevents the computational complexity and overfitting of clustering algorithm. The feasibility of the proposed algorithm is verified by comparing with general clustering algorithms such as the k-means clustering and Gaussian mixture model.
{"title":"An Optimal Clustering Algorithm for Second Use of Retired EV Batteries Using DBSCAN and PCA Schemes Considering Performance Deviation","authors":"Jeyeong Lim, Eui-Seong Han, Dong Hwan Kim, B. Lee","doi":"10.1109/APEC43580.2023.10131499","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131499","url":null,"abstract":"This paper proposes an optimal clustering algorithm considering performance deviation of parameters and data preprocessing method for reusing retired batteries. The proposed method regroups batteries by considering the density and performance deviation of the retired battery dataset through a clustering algorithm using density-based spatial clustering of applications with noise (DBSCAN). Additionally, the performance of the algorithm was improved through data preprocessing using a principal component analysis (PCA) that prevents the computational complexity and overfitting of clustering algorithm. The feasibility of the proposed algorithm is verified by comparing with general clustering algorithms such as the k-means clustering and Gaussian mixture model.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134413933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131293
Ruomu Hao, Bradford Houska, Decheng Yan, Kartavya Agarwal, Aniruddh Marellapudi, Shreyas Kulkarni, J. Benzaquen, D. Divan
Energy access to off-grid communities has been historically limited by the availability and cost of the bulk power system interconnection. Modern technologies with steep, sustained learning rates, e.g., solar and batteries, are capable of disrupting this trend and making energy available equitably across the population, especially if solar and storage are combined to create a dispatchable resource. Nonetheless, a cost-effective and scalable solution that integrates solar, storage, and output ac power remains the key roadblock toward distributed energy access. In this paper, a single single-stage, isolated, bi-directional micro-inverter design with reduced switch and sensor count, which interfaces with the battery, PV, and grid, is presented. It excludes large DC-link capacitors, which are commonly seen among prevailing PV converter options, and retains efficiency benefits from its design and operation. With a power rating of 1-kW, this converter can be stacked easily to scale up the total system power rating due to its current-source inverter nature. Throughout this paper, the operating principle, design, and control of the proposed micro-inverter are presented. Lastly, A 1-kVA/480-Vac hardware prototype is built to demonstrate the proposed microinverter.
从历史上看，离网社区的能源获取一直受到大量电力系统互联的可用性和成本的限制。具有快速、持续学习率的现代技术，例如太阳能和电池，能够打破这一趋势，使能源在整个人口中公平地获得，特别是如果太阳能和存储相结合，创造一种可调度的资源。然而，集成太阳能、储能和输出交流电源的经济、可扩展的解决方案仍然是实现分布式能源接入的关键障碍。本文提出了一种单级、隔离、双向的微型逆变器设计，减少了开关和传感器的数量，并与电池、光伏和电网相连接。它不包括大型直流连接电容器，这是常见的PV转换器选项，并保留其设计和操作的效率优势。该转换器的额定功率为1kw，由于其电流源逆变器的特性，可以很容易地堆叠以扩大系统的总额定功率。本文介绍了该微型逆变器的工作原理、设计和控制。最后，建立了一个1 kva /480 vac的硬件样机来演示所提出的微型逆变器。
{"title":"A Single-Stage Isolated Bi-directional Micro-inverter Building Block for Off-grid Energy Access","authors":"Ruomu Hao, Bradford Houska, Decheng Yan, Kartavya Agarwal, Aniruddh Marellapudi, Shreyas Kulkarni, J. Benzaquen, D. Divan","doi":"10.1109/APEC43580.2023.10131293","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131293","url":null,"abstract":"Energy access to off-grid communities has been historically limited by the availability and cost of the bulk power system interconnection. Modern technologies with steep, sustained learning rates, e.g., solar and batteries, are capable of disrupting this trend and making energy available equitably across the population, especially if solar and storage are combined to create a dispatchable resource. Nonetheless, a cost-effective and scalable solution that integrates solar, storage, and output ac power remains the key roadblock toward distributed energy access. In this paper, a single single-stage, isolated, bi-directional micro-inverter design with reduced switch and sensor count, which interfaces with the battery, PV, and grid, is presented. It excludes large DC-link capacitors, which are commonly seen among prevailing PV converter options, and retains efficiency benefits from its design and operation. With a power rating of 1-kW, this converter can be stacked easily to scale up the total system power rating due to its current-source inverter nature. Throughout this paper, the operating principle, design, and control of the proposed micro-inverter are presented. Lastly, A 1-kVA/480-Vac hardware prototype is built to demonstrate the proposed microinverter.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131712509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：